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From: "Michel Dänzer" <michel-otUistvHUpPR7s880joybQ@public.gmane.org>
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Subject: [PATCH] drm/amdgpu: Fix RLC safe mode test in gfx_v9_0_enter_rlc_safe_mode
Date: Fri, 20 Jul 2018 18:33:01 +0200	[thread overview]
Message-ID: <20180720163301.9376-1-michel@daenzer.net> (raw)

From: Michel Dänzer <michel.daenzer@amd.com>

We were testing the register offset, instead of the value stored in the
register, therefore always timing out the loop.

This reduces suspend time of the system in the bug report below by ~600
ms.

Bugzilla: https://bugs.freedesktop.org/107277
Tested-by: Paul Menzel <pmenzel@molgen.mpg.de>
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 9ab39117cc4e..ef00d14f8645 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3490,7 +3490,7 @@ static void gfx_v9_0_enter_rlc_safe_mode(struct amdgpu_device *adev)
 
 		/* wait for RLC_SAFE_MODE */
 		for (i = 0; i < adev->usec_timeout; i++) {
-			if (!REG_GET_FIELD(SOC15_REG_OFFSET(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
+			if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
 				break;
 			udelay(1);
 		}
-- 
2.18.0

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             reply	other threads:[~2018-07-20 16:33 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-07-20 16:33 Michel Dänzer [this message]
     [not found] ` <20180720163301.9376-1-michel-otUistvHUpPR7s880joybQ@public.gmane.org>
2018-07-20 16:35   ` [PATCH] drm/amdgpu: Fix RLC safe mode test in gfx_v9_0_enter_rlc_safe_mode Deucher, Alexander
2018-07-23  6:33   ` Zhang, Jerry (Junwei)
2018-07-24 17:20   ` Paul Menzel
     [not found]     ` <cd8a8d33-2fa5-6cdc-fe62-86a38f04c207-KUpvgZVWgV9o1qOY/usvUg@public.gmane.org>
2018-07-24 17:24       ` Michel Dänzer

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