From: Wei Liu <wei.liu2@citrix.com>
To: Andrew Cooper <andrew.cooper3@citrix.com>
Cc: "Sergey Dyasli" <sergey.dyasli@citrix.com>,
"Roger Pau Monné" <roger.pau@citrix.com>,
"Wei Liu" <wei.liu2@citrix.com>,
"Jan Beulich" <JBeulich@suse.com>,
Xen-devel <xen-devel@lists.xen.org>
Subject: Re: [PATCH] x86/hvm: Disallow unknown MSR_EFER bits
Date: Mon, 23 Jul 2018 15:33:23 +0100 [thread overview]
Message-ID: <20180723143323.bxfczp6wodzh7m5h@citrix.com> (raw)
In-Reply-To: <1532353790-28875-1-git-send-email-andrew.cooper3@citrix.com>
On Mon, Jul 23, 2018 at 02:49:50PM +0100, Andrew Cooper wrote:
> It turns out that nothing ever prevented HVM guests from trying to set unknown
> EFER bits. Generally, this results in a vmentry failure.
>
> For Intel hardware, all implemented bits are covered by the checks.
>
> For AMD hardware, the only EFER bit which isn't covered by the checks is TCE
> (which AFAICT is specific to AMD Fam15/16 hardware). We never advertise TCE
> in CPUID, but it isn't a security problem to have TCE unexpected enabled in
> guest context.
>
> Disallow the setting of bits outside of the EFER_KNOWN_MASK, which prevents
> any vmentry failures for guests, yielding #GP instead.
>
> Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Wei Liu <wei.liu2@citrix.com>
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prev parent reply other threads:[~2018-07-23 14:33 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-23 13:49 [PATCH] x86/hvm: Disallow unknown MSR_EFER bits Andrew Cooper
2018-07-23 14:11 ` Roger Pau Monné
2018-07-24 10:13 ` Jan Beulich
2018-07-23 14:33 ` Wei Liu [this message]
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