From mboxrd@z Thu Jan 1 00:00:00 1970 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 25 Jul 2018 14:23:24 +0200 (CEST) Received: from mail.bootlin.com ([62.4.15.54]:41638 "EHLO mail.bootlin.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S23992289AbeGYMXVdkyZC (ORCPT ); Wed, 25 Jul 2018 14:23:21 +0200 Received: by mail.bootlin.com (Postfix, from userid 110) id 84858207A8; Wed, 25 Jul 2018 14:23:15 +0200 (CEST) Received: from localhost.localdomain (unknown [80.255.6.130]) by mail.bootlin.com (Postfix) with ESMTPSA id 1BB93206A6; Wed, 25 Jul 2018 14:23:05 +0200 (CEST) From: Quentin Schulz To: alexandre.belloni@bootlin.com, robh+dt@kernel.org, mark.rutland@arm.com Cc: ralf@linux-mips.org, paul.burton@mips.com, jhogan@kernel.org, linux-mips@linux-mips.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, thomas.petazzoni@bootlin.com, Quentin Schulz Subject: [PATCH] MIPS: mscc: ocelot: add MIIM1 bus Date: Wed, 25 Jul 2018 14:22:41 +0200 Message-Id: <20180725122241.31370-1-quentin.schulz@bootlin.com> X-Mailer: git-send-email 2.14.1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 65134 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: quentin.schulz@bootlin.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips There is an additional MIIM (MDIO) bus in this SoC so let's declare it in the dtsi. This bus requires GPIO 14 and 15 pins that need to be muxed. There is no support for internal PHY reset on this bus on the contrary of MIIM0 so there is only one register address space and not two. Signed-off-by: Quentin Schulz --- arch/mips/boot/dts/mscc/ocelot.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/mips/boot/dts/mscc/ocelot.dtsi b/arch/mips/boot/dts/mscc/ocelot.dtsi index 7096915f26e0..d7f0e3551500 100644 --- a/arch/mips/boot/dts/mscc/ocelot.dtsi +++ b/arch/mips/boot/dts/mscc/ocelot.dtsi @@ -178,6 +178,11 @@ pins = "GPIO_12", "GPIO_13"; function = "uart2"; }; + + miim1: miim1 { + pins = "GPIO_14", "GPIO_15"; + function = "miim1"; + }; }; mdio0: mdio@107009c { @@ -201,5 +206,16 @@ reg = <3>; }; }; + + mdio1: mdio@10700c0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "mscc,ocelot-miim"; + reg = <0x10700c0 0x24>; + interrupts = <15>; + pinctrl-names = "default"; + pinctrl-0 = <&miim1>; + status = "disabled"; + }; }; }; -- 2.14.1