Re: [PATCH] iommu/arm-smmu-v3: sync the OVACKFLG to PRIQ consumer register

[Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org>]

On Fri, Jul 27, 2018 at 05:41:46PM +0800, Zhangshaokun wrote:
> I saw it in your trees, is it necessary to Cc stable version?

I don't think so, given that we don't actually support PRI upstream.

Will

> On 2018/7/23 20:56, Shaokun Zhang wrote:
> > From: Miao Zhong <zhongmiao-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
> > 
> > When PRI queue occurs overflow, driver should update the OVACKFLG to
> > the PRIQ consumer register, otherwise subsequent PRI requests will not
> > be processed.
> > 
> > Cc: Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org>
> > Cc: Robin Murphy <robin.murphy-5wv7dgnIgG8@public.gmane.org> 
> > Signed-off-by: Miao Zhong <zhongmiao-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
> > ---
> >  drivers/iommu/arm-smmu-v3.c | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c
> > index 1d64710..deacc15 100644
> > --- a/drivers/iommu/arm-smmu-v3.c
> > +++ b/drivers/iommu/arm-smmu-v3.c
> > @@ -1301,6 +1301,7 @@ static irqreturn_t arm_smmu_priq_thread(int irq, void *dev)
> >  
> >  	/* Sync our overflow flag, as we believe we're up to speed */
> >  	q->cons = Q_OVF(q, q->prod) | Q_WRP(q, q->cons) | Q_IDX(q, q->cons);
> > +	writel(q->cons, q->cons_reg);
> >  	return IRQ_HANDLED;
> >  }
> >  
> > 
>