Re: [PATCH 1/2] drm/i915/icl: Implement HSDIV_RATIO of MG_CLKTOP2_HSCLKCTL_PORT reg as separate divider value defines

From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/2] drm/i915/icl: Implement HSDIV_RATIO of MG_CLKTOP2_HSCLKCTL_PORT reg as separate divider value defines
Date: Fri, 27 Jul 2018 22:13:28 -0700	[thread overview]
Message-ID: <20180728051327.GA14046@intel.com> (raw)
In-Reply-To: <20180727200457.16560-1-paulo.r.zanoni@intel.com>

On Fri, Jul 27, 2018 at 01:04:56PM -0700, Paulo Zanoni wrote:
> From: Manasi Navare <manasi.d.navare@intel.com>
> 
> The register value of Divider Ratio for high speed divider
> (hsdiv_ratio) in MG_CLKTOP2_HSCLKCTL_PORT register is not same as the
> actual numerical value of the divider. So this patch implements
> separate divider value defines for that field.
> icl_mg_pll_find_divisors() can use these defines instead of magic
> register values.
> 
> The new defines are going to be used in the next patch.
> 
> v2 (from Paulo):
>  * Rebase.
>  * Make it look a little more like the rest of our code.
> 
> Cc: James Ausmus <james.ausmus@intel.com>
> Suggested-by: James Ausmus <james.ausmus@intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h       |  5 ++++-
>  drivers/gpu/drm/i915/intel_dpll_mgr.c | 10 +++++-----
>  2 files changed, 9 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 5530c470f30d..e04ac47d53db 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9452,8 +9452,11 @@ enum skl_power_gate {
>  #define   MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK	(0x1 << 16)
>  #define   MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(x)	((x) << 14)
>  #define   MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK	(0x3 << 14)
> -#define   MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO(x)		((x) << 12)
>  #define   MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK		(0x3 << 12)
> +#define   MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2		(0 << 12)
> +#define   MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3		(1 << 12)
> +#define   MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5		(2 << 12)
> +#define   MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7		(3 << 12)
>  #define   MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(x)		((x) << 8)
>  #define   MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK		(0xf << 8)
>  #define MG_CLKTOP2_HSCLKCTL(port) _MMIO_PORT((port) - PORT_C, \
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 7e5e6eb5dfe2..300c374fc721 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -2662,16 +2662,16 @@ static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
>  				MISSING_CASE(div1);
>  				/* fall through */
>  			case 2:
> -				hsdiv = 0;
> +				hsdiv = MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2;
>  				break;
>  			case 3:
> -				hsdiv = 1;
> +				hsdiv = MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3;
>  				break;
>  			case 5:
> -				hsdiv = 2;
> +				hsdiv = MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5;
>  				break;
>  			case 7:
> -				hsdiv = 3;
> +				hsdiv = MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7;
>  				break;
>  			}
>  
> @@ -2685,7 +2685,7 @@ static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
>  			state->mg_clktop2_hsclkctl =
>  				MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(tlinedrv) |
>  				MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL(inputsel) |
> -				MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO(hsdiv) |
> +				hsdiv |
>  				MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(div2);
>  
>  			return true;
> -- 
> 2.17.1
> 
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