diff for duplicates of <20180730200232.GA31755@xps15> diff --git a/a/1.txt b/N1/1.txt index 3197b22..5ef5024 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -16,12 +16,12 @@ On Fri, Jul 27, 2018 at 11:15:28AM +0100, Suzuki K Poulose wrote: > > e.g, with the existing bindings we get : > -> port at 0{ // Output port 0 +> port@0{ // Output port 0 > reg = <0>; > ... > }; > -> port at 1{ +> port@1{ > reg = <0>; // Input port 0 > endpoint { > slave-mode; @@ -30,7 +30,7 @@ On Fri, Jul 27, 2018 at 11:15:28AM +0100, Suzuki K Poulose wrote: > }; > > With the new enforcement in the DT rules, mismatches in label and address -> are not allowed (as see in the case for port at 1). So, we need a new mechanism +> are not allowed (as see in the case for port@1). So, we need a new mechanism > to describe the hardware port number reliably. > > Also, we relied on an undocumented "slave-mode" property (see the above @@ -55,14 +55,14 @@ On Fri, Jul 27, 2018 at 11:15:28AM +0100, Suzuki K Poulose wrote: > where the members are port number and the direction respectively. > e.g > -> port at 0{ +> port@0{ > reg = <0>; > endpoint { > coresight,hwid = <0 1>; // Port # 0, Output > } > }; > -> port at 1{ +> port@1{ > reg = <1>; > endpoint { > coresight,hwid = <0 0>; // Port # 0, Input @@ -82,7 +82,7 @@ On Fri, Jul 27, 2018 at 11:15:28AM +0100, Suzuki K Poulose wrote: > > e.g, > -> port at 0{ +> port@0{ > reg = <0>; > endpoint { > direction = <1>; // Output @@ -90,7 +90,7 @@ On Fri, Jul 27, 2018 at 11:15:28AM +0100, Suzuki K Poulose wrote: > } > }; > -> port at 1{ +> port@1{ > reg = <1>; > endpoint { > direction = <0>; // Input @@ -112,12 +112,12 @@ On Fri, Jul 27, 2018 at 11:15:28AM +0100, Suzuki K Poulose wrote: > > out-ports { // Output ports for this component > -> port at 0 { // Outport 0 +> port@0 { // Outport 0 > reg = 0; > endpoint { ... }; > }; > -> port at 1 { // Outport 1 +> port@1 { // Outport 1 > reg = 1; > endpoint { ... }; > }; @@ -125,12 +125,12 @@ On Fri, Jul 27, 2018 at 11:15:28AM +0100, Suzuki K Poulose wrote: > }; > > in-ports { // Input ports for this component -> port at 0 { // Inport 0 +> port@0 { // Inport 0 > reg = 0; > endpoint { ... }; > }; > -> port at 1 { // Inport 1 +> port@1 { // Inport 1 > reg = 1; > endpoint { ... }; > }; diff --git a/a/content_digest b/N1/content_digest index b6c734b..f9a7d58 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,8 +1,20 @@ "ref\01532686537-12380-1-git-send-email-suzuki.poulose@arm.com\0" - "From\0mathieu.poirier@linaro.org (Mathieu Poirier)\0" - "Subject\0[PATCH v3 0/9] coresight: Update device tree bindings\0" + "From\0Mathieu Poirier <mathieu.poirier@linaro.org>\0" + "Subject\0Re: [PATCH v3 0/9] coresight: Update device tree bindings\0" "Date\0Mon, 30 Jul 2018 14:02:32 -0600\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Suzuki K Poulose <suzuki.poulose@arm.com>\0" + "Cc\0linux-arm-kernel@lists.infradead.org" + linux-kernel@vger.kernel.org + mike.leach@linaro.org + robert.walker@arm.com + coresight@lists.linaro.org + robh@kernel.org + frowand.list@gmail.com + devicetree@vger.kernel.org + matt.sealey@arm.com + charles.garcia-tobin@arm.com + john.horley@arm.com + " al.grant@arm.com\0" "\00:1\0" "b\0" "On Fri, Jul 27, 2018 at 11:15:28AM +0100, Suzuki K Poulose wrote:\n" @@ -23,12 +35,12 @@ "> \n" "> e.g, with the existing bindings we get :\n" "> \n" - "> \tport at 0{\t\t\t\t// Output port 0\n" + "> \tport@0{\t\t\t\t// Output port 0\n" "> \t\treg = <0>;\n" "> \t\t...\n" "> \t};\n" "> \n" - "> \tport at 1{\n" + "> \tport@1{\n" "> \t\treg = <0>;\t\t// Input port 0\n" "> \t\tendpoint {\n" "> \t\t\tslave-mode;\n" @@ -37,7 +49,7 @@ "> \t};\n" "> \n" "> With the new enforcement in the DT rules, mismatches in label and address\n" - "> are not allowed (as see in the case for port at 1). So, we need a new mechanism\n" + "> are not allowed (as see in the case for port@1). So, we need a new mechanism\n" "> to describe the hardware port number reliably.\n" "> \n" "> Also, we relied on an undocumented \"slave-mode\" property (see the above\n" @@ -62,14 +74,14 @@ "> where the members are port number and the direction respectively.\n" "> \te.g\n" "> \n" - "> \tport at 0{\n" + "> \tport@0{\n" "> \t\treg = <0>;\n" "> \t\tendpoint {\n" "> \t\t\tcoresight,hwid = <0 1>;\t// Port # 0, Output\n" "> \t\t}\n" "> \t};\n" "> \n" - "> \tport at 1{\n" + "> \tport@1{\n" "> \t\treg = <1>;\n" "> \t\tendpoint {\n" "> \t\t\tcoresight,hwid = <0 0>;\t// Port # 0, Input\n" @@ -89,7 +101,7 @@ "> \n" "> \te.g,\n" "> \n" - "> \tport at 0{\n" + "> \tport@0{\n" "> \t\treg = <0>;\n" "> \t\tendpoint {\n" "> \t\t\tdirection = <1>;\t// Output\n" @@ -97,7 +109,7 @@ "> \t\t}\n" "> \t};\n" "> \n" - "> \tport at 1{\n" + "> \tport@1{\n" "> \t\treg = <1>;\n" "> \t\tendpoint {\n" "> \t\t\tdirection = <0>;\t// Input\n" @@ -119,12 +131,12 @@ "> \n" "> \tout-ports {\t\t\t\t// Output ports for this component\n" "> \n" - "> \t\tport at 0 {\t\t\t// Outport 0\n" + "> \t\tport@0 {\t\t\t// Outport 0\n" "> \t\t reg = 0;\n" "> \t\t endpoint { ... };\n" "> \t\t};\n" "> \n" - "> \t\tport at 1 {\t\t\t// Outport 1\n" + "> \t\tport@1 {\t\t\t// Outport 1\n" "> \t\t reg = 1;\n" "> \t\t endpoint { ... };\n" "> \t\t};\n" @@ -132,12 +144,12 @@ "> \t};\n" "> \n" "> \tin-ports {\t\t\t\t// Input ports for this component\n" - "> \t\tport at 0 {\t\t\t// Inport 0\n" + "> \t\tport@0 {\t\t\t// Inport 0\n" "> \t\t reg = 0;\n" "> \t\t endpoint { ... };\n" "> \t\t};\n" "> \n" - "> \t\tport at 1 {\t\t\t// Inport 1\n" + "> \t\tport@1 {\t\t\t// Inport 1\n" "> \t\t reg = 1;\n" "> \t\t endpoint { ... };\n" "> \t\t};\n" @@ -211,4 +223,4 @@ "> 2.7.4\n" > -70f6c1f692d14ee079cd1bad047c37987c2c9e3d354750da01bcfbcf8975ce1c +36b979bc614ce0823dca0f3f63357e5cc9d9023a7f17051bbfb8cc4e4d954529
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