Re: [PATCH v4 1/3] drm/i915: make PCH_GMBUS* definitions private to gvt

From: Zhenyu Wang <zhenyuw@linux.intel.com>
To: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: daniel.vetter@ffwll.ch, intel-gfx@lists.freedesktop.org,
	Rodrigo Vivi <rodrigo.vivi@intel.com>,
	intel-gvt-dev@lists.freedesktop.org
Subject: Re: [PATCH v4 1/3] drm/i915: make PCH_GMBUS* definitions private to gvt
Date: Tue, 31 Jul 2018 10:45:28 +0800	[thread overview]
Message-ID: <20180731024528.GH22630@zhen-hp.sh.intel.com> (raw)
In-Reply-To: <20180727193647.8639-1-lucas.demarchi@intel.com>

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On 2018.07.27 12:36:45 -0700, Lucas De Marchi wrote:
> This is the only place that they are being used - the others use the
> GMBUS* macros that rely on dev_priv being already properly initialized.
>

Reviewed-by: Zhenyu Wang <zhenyuw@linux.intel.com>

thanks!

> Cc: intel-gvt-dev@lists.freedesktop.org
> Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/gvt/reg.h  | 7 +++++++
>  drivers/gpu/drm/i915/i915_reg.h | 7 -------
>  2 files changed, 7 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gvt/reg.h b/drivers/gpu/drm/i915/gvt/reg.h
> index d4f7ce6dc1d7..fd5fd25d0a0f 100644
> --- a/drivers/gpu/drm/i915/gvt/reg.h
> +++ b/drivers/gpu/drm/i915/gvt/reg.h
> @@ -77,4 +77,11 @@
>  #define _RING_CTL_BUF_SIZE(ctl) (((ctl) & RB_TAIL_SIZE_MASK) + \
>  		I915_GTT_PAGE_SIZE)
>  
> +#define PCH_GMBUS0	_MMIO(0xc5100)
> +#define PCH_GMBUS1	_MMIO(0xc5104)
> +#define PCH_GMBUS2	_MMIO(0xc5108)
> +#define PCH_GMBUS3	_MMIO(0xc510c)
> +#define PCH_GMBUS4	_MMIO(0xc5110)
> +#define PCH_GMBUS5	_MMIO(0xc5120)
> +
>  #endif
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 5530c470f30d..07606677168c 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7875,13 +7875,6 @@ enum {
>  #define PCH_GPIOE               _MMIO(0xc5020)
>  #define PCH_GPIOF               _MMIO(0xc5024)
>  
> -#define PCH_GMBUS0		_MMIO(0xc5100)
> -#define PCH_GMBUS1		_MMIO(0xc5104)
> -#define PCH_GMBUS2		_MMIO(0xc5108)
> -#define PCH_GMBUS3		_MMIO(0xc510c)
> -#define PCH_GMBUS4		_MMIO(0xc5110)
> -#define PCH_GMBUS5		_MMIO(0xc5120)
> -
>  #define _PCH_DPLL_A              0xc6014
>  #define _PCH_DPLL_B              0xc6018
>  #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
> -- 
> 2.17.1
> 
> _______________________________________________
> intel-gvt-dev mailing list
> intel-gvt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gvt-dev

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