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* [PATCH] drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming
@ 2018-08-06 17:33 Anusha Srivatsa
  2018-08-06 18:02 ` ✓ Fi.CI.BAT: success for " Patchwork
                   ` (2 more replies)
  0 siblings, 3 replies; 4+ messages in thread
From: Anusha Srivatsa @ 2018-08-06 17:33 UTC (permalink / raw)
  To: intel-gfx

Add the newly added slice_row_per_frame parameter
in the Picture Parameter Set registers.

Credits to Manasi for noticing bSpec change.

Suggested-by: Manasi Navare <manasi.d.navare@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4b656f3..f868684 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10683,6 +10683,7 @@ enum skl_power_gate {
 #define ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
 							   _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB, \
 							   _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC)
+#define  DSC_SLICE_ROW_PER_FRAME(slice_row_per_frame)	((slice_row_per_frame) << 20)
 #define  DSC_SLICE_PER_LINE(slice_per_line)		((slice_per_line) << 16)
 #define  DSC_SLICE_CHUNK_SIZE(slice_chunk_size)		((slice_chunk_size) << 0)
 
-- 
2.7.4

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^ permalink raw reply related	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2018-08-06 20:52 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2018-08-06 17:33 [PATCH] drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming Anusha Srivatsa
2018-08-06 18:02 ` ✓ Fi.CI.BAT: success for " Patchwork
2018-08-06 18:53 ` [PATCH] " Manasi Navare
2018-08-06 20:52 ` ✓ Fi.CI.IGT: success for " Patchwork

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