From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [v9,4/4] dmaengine: fsl-edma: add ColdFire mcf5441x edma support From: Angelo Dureghello Message-Id: <20180811112649.20752-4-angelo@sysam.it> Date: Sat, 11 Aug 2018 13:26:49 +0200 To: vinod.koul@linaro.org Cc: dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-m68k@vger.kernel.org, stefan@agner.ch, krzk@kernel.org, Angelo Dureghello List-ID: VGhpcyBwYXRjaCBhZGRzIHN1cHBvcnQgZm9yIENvbGRGaXJlIG1jZjU0NDF4LWZhbWlseSBlZG1h Cm1vZHVsZS4KClRoZSBDb2xkRmlyZSBlZG1hIG1vZHVsZSBpcyBzbGlnaHRseSBkaWZmZXJlbnQg ZnJvbSBmc2wtZWRtYSwKc28gYSBuZXcgZHJpdmVyIGlzIGFkZGVkLiBCdXQgbW9zdCBvZiB0aGUg Y29kZSBpcyBjb21tb24KYmV0d2VlbiBmc2wtZWRtYSBhbmQgbWNmLWVkbWEgc28gaXQgaGFzIGJl ZW4gY29sbGVjdGVkIGludG8gYQpzZXBhcmF0ZSBjb21tb24gbW9kdWxlIGZzbC1lZG1hLWNvbW1v biAocGF0Y2ggMS8zKS4KClNpZ25lZC1vZmYtYnk6IEFuZ2VsbyBEdXJlZ2hlbGxvIDxhbmdlbG9A c3lzYW0uaXQ+Ci0tLQpDaGFuZ2VzIGZvciB2ODoKLSBwYXRjaCByZXdyaXR0ZW4gZnJvbSBzY3Jh dGNoLCB0aGlzIHBhdGNoICgzLzMpIGhhcyBqdXN0IGJlZW4gYWRkZWQuCgpDaGFuZ2VzIGZvciB2 OToKLSBhZGQgY29tcGlsZSB0ZXN0IGZvciBLY29uZmlnLAotIGZpeCBpbmNsdWRlIGd1YXJkLgot LS0KIGRyaXZlcnMvZG1hL0tjb25maWcgICAgICAgICAgICAgICAgICAgICAgICB8ICAxMSArCiBk cml2ZXJzL2RtYS9NYWtlZmlsZSAgICAgICAgICAgICAgICAgICAgICAgfCAgIDEgKwogZHJpdmVy cy9kbWEvZnNsLWVkbWEtY29tbW9uLmMgICAgICAgICAgICAgIHwgIDI0ICstCiBkcml2ZXJzL2Rt YS9tY2YtZWRtYS5jICAgICAgICAgICAgICAgICAgICAgfCAzMTUgKysrKysrKysrKysrKysrKysr KysrCiBpbmNsdWRlL2xpbnV4L3BsYXRmb3JtX2RhdGEvZG1hLW1jZi1lZG1hLmggfCAgMzggKysr CiA1IGZpbGVzIGNoYW5nZWQsIDM4NSBpbnNlcnRpb25zKCspLCA0IGRlbGV0aW9ucygtKQogY3Jl YXRlIG1vZGUgMTAwNjQ0IGRyaXZlcnMvZG1hL21jZi1lZG1hLmMKIGNyZWF0ZSBtb2RlIDEwMDY0 NCBpbmNsdWRlL2xpbnV4L3BsYXRmb3JtX2RhdGEvZG1hLW1jZi1lZG1hLmgKCmRpZmYgLS1naXQg YS9kcml2ZXJzL2RtYS9LY29uZmlnIGIvZHJpdmVycy9kbWEvS2NvbmZpZwppbmRleCBjYTE2ODBh ZmEyMGEuLjQ1Y2E1ZTU1Njc3NCAxMDA2NDQKLS0tIGEvZHJpdmVycy9kbWEvS2NvbmZpZworKysg Yi9kcml2ZXJzL2RtYS9LY29uZmlnCkBAIC0zMjAsNiArMzIwLDE3IEBAIGNvbmZpZyBMUEMxOFhY X0RNQU1VWAogCSAgRW5hYmxlIHN1cHBvcnQgZm9yIERNQSBvbiBOWFAgTFBDMTh4eC80M3h4IHBs YXRmb3JtcwogCSAgd2l0aCBQTDA4MCBhbmQgbXVsdGlwbGV4ZWQgRE1BIHJlcXVlc3QgbGluZXMu CiAKK2NvbmZpZyBNQ0ZfRURNQQorCXRyaXN0YXRlICJGcmVlc2NhbGUgZURNQSBlbmdpbmUgc3Vw cG9ydCwgQ29sZEZpcmUgbWNmNTQ0MXggU29DcyIKKwlkZXBlbmRzIG9uIE01NDQxeCB8fCBDT01Q SUxFX1RFU1QKKwlzZWxlY3QgRE1BX0VOR0lORQorCXNlbGVjdCBETUFfVklSVFVBTF9DSEFOTkVM UworCWhlbHAKKwkgIFN1cHBvcnQgdGhlIEZyZWVzY2FsZSBDb2xkRmlyZSBlRE1BIGVuZ2luZSwg NjQtY2hhbm5lbAorCSAgaW1wbGVtZW50YXRpb24gdGhhdCBwZXJmb3JtcyBjb21wbGV4IGRhdGEg dHJhbnNmZXJzIHdpdGgKKwkgIG1pbmltYWwgaW50ZXJ2ZW50aW9uIGZyb20gYSBob3N0IHByb2Nl c3Nvci4KKwkgIFRoaXMgbW9kdWxlIGNhbiBiZSBmb3VuZCBvbiBGcmVlc2NhbGUgQ29sZEZpcmUg bWNmNTQ0MXggU29Dcy4KKwogY29uZmlnIE1NUF9QRE1BCiAJYm9vbCAiTU1QIFBETUEgc3VwcG9y dCIKIAlkZXBlbmRzIG9uIEFSQ0hfTU1QIHx8IEFSQ0hfUFhBIHx8IENPTVBJTEVfVEVTVApkaWZm IC0tZ2l0IGEvZHJpdmVycy9kbWEvTWFrZWZpbGUgYi9kcml2ZXJzL2RtYS9NYWtlZmlsZQppbmRl eCA2NjAyMmY1OWZjYTQuLmQ5N2YzMTdmNGIzNCAxMDA2NDQKLS0tIGEvZHJpdmVycy9kbWEvTWFr ZWZpbGUKKysrIGIvZHJpdmVycy9kbWEvTWFrZWZpbGUKQEAgLTMyLDYgKzMyLDcgQEAgb2JqLSQo Q09ORklHX0RXX0RNQUNfQ09SRSkgKz0gZHcvCiBvYmotJChDT05GSUdfRVA5M1hYX0RNQSkgKz0g ZXA5M3h4X2RtYS5vCiBvYmotJChDT05GSUdfRlNMX0RNQSkgKz0gZnNsZG1hLm8KIG9iai0kKENP TkZJR19GU0xfRURNQSkgKz0gZnNsLWVkbWEubyBmc2wtZWRtYS1jb21tb24ubworb2JqLSQoQ09O RklHX01DRl9FRE1BKSArPSBtY2YtZWRtYS5vIGZzbC1lZG1hLWNvbW1vbi5vCiBvYmotJChDT05G SUdfRlNMX1JBSUQpICs9IGZzbF9yYWlkLm8KIG9iai0kKENPTkZJR19IU1VfRE1BKSArPSBoc3Uv CiBvYmotJChDT05GSUdfSU1HX01EQ19ETUEpICs9IGltZy1tZGMtZG1hLm8KZGlmZiAtLWdpdCBh L2RyaXZlcnMvZG1hL2ZzbC1lZG1hLWNvbW1vbi5jIGIvZHJpdmVycy9kbWEvZnNsLWVkbWEtY29t bW9uLmMKaW5kZXggMjI3MDM0ZGUyNTZlLi44YmE4MGY0YjZmNTUgMTAwNjQ0Ci0tLSBhL2RyaXZl cnMvZG1hL2ZzbC1lZG1hLWNvbW1vbi5jCisrKyBiL2RyaXZlcnMvZG1hL2ZzbC1lZG1hLWNvbW1v bi5jCkBAIC00Niw4ICs0NiwxNiBAQCBzdGF0aWMgdm9pZCBmc2xfZWRtYV9lbmFibGVfcmVxdWVz dChzdHJ1Y3QgZnNsX2VkbWFfY2hhbiAqZnNsX2NoYW4pCiAJc3RydWN0IGVkbWFfcmVncyAqcmVn cyA9ICZmc2xfY2hhbi0+ZWRtYS0+cmVnczsKIAl1MzIgY2ggPSBmc2xfY2hhbi0+dmNoYW4uY2hh bi5jaGFuX2lkOwogCi0JZWRtYV93cml0ZWIoZnNsX2NoYW4tPmVkbWEsIEVETUFfU0VFSV9TRUVJ KGNoKSwgcmVncy0+c2VlaSk7Ci0JZWRtYV93cml0ZWIoZnNsX2NoYW4tPmVkbWEsIGNoLCByZWdz LT5zZXJxKTsKKwlpZiAoZnNsX2NoYW4tPmVkbWEtPnZlcnNpb24gPT0gdjEpIHsKKwkJZWRtYV93 cml0ZWIoZnNsX2NoYW4tPmVkbWEsIEVETUFfU0VFSV9TRUVJKGNoKSwgcmVncy0+c2VlaSk7CisJ CWVkbWFfd3JpdGViKGZzbF9jaGFuLT5lZG1hLCBjaCwgcmVncy0+c2VycSk7CisJfSBlbHNlIHsK KwkJLyogQ29sZEZpcmUgaXMgYmlnIGVuZGlhbiwgYW5kIGFjY2Vzc2VzIG5hdGl2ZWx5CisJCSAq IGJpZyBlbmRpYW4gSS9PIHBlcmlwaGVyYWxzCisJCSAqLworCQlpb3dyaXRlOChFRE1BX1NFRUlf U0VFSShjaCksIHJlZ3MtPnNlZWkpOworCQlpb3dyaXRlOChjaCwgcmVncy0+c2VycSk7CisJfQog fQogCiB2b2lkIGZzbF9lZG1hX2Rpc2FibGVfcmVxdWVzdChzdHJ1Y3QgZnNsX2VkbWFfY2hhbiAq ZnNsX2NoYW4pCkBAIC01NSw4ICs2MywxNiBAQCB2b2lkIGZzbF9lZG1hX2Rpc2FibGVfcmVxdWVz dChzdHJ1Y3QgZnNsX2VkbWFfY2hhbiAqZnNsX2NoYW4pCiAJc3RydWN0IGVkbWFfcmVncyAqcmVn cyA9ICZmc2xfY2hhbi0+ZWRtYS0+cmVnczsKIAl1MzIgY2ggPSBmc2xfY2hhbi0+dmNoYW4uY2hh bi5jaGFuX2lkOwogCi0JZWRtYV93cml0ZWIoZnNsX2NoYW4tPmVkbWEsIGNoLCByZWdzLT5jZXJx KTsKLQllZG1hX3dyaXRlYihmc2xfY2hhbi0+ZWRtYSwgRURNQV9DRUVJX0NFRUkoY2gpLCByZWdz LT5jZWVpKTsKKwlpZiAoZnNsX2NoYW4tPmVkbWEtPnZlcnNpb24gPT0gdjEpIHsKKwkJZWRtYV93 cml0ZWIoZnNsX2NoYW4tPmVkbWEsIGNoLCByZWdzLT5jZXJxKTsKKwkJZWRtYV93cml0ZWIoZnNs X2NoYW4tPmVkbWEsIEVETUFfQ0VFSV9DRUVJKGNoKSwgcmVncy0+Y2VlaSk7CisJfSBlbHNlIHsK KwkJLyogQ29sZEZpcmUgaXMgYmlnIGVuZGlhbiwgYW5kIGFjY2Vzc2VzIG5hdGl2ZWx5CisJCSAq IGJpZyBlbmRpYW4gSS9PIHBlcmlwaGVyYWxzCisJCSAqLworCQlpb3dyaXRlOChjaCwgcmVncy0+ Y2VycSk7CisJCWlvd3JpdGU4KEVETUFfQ0VFSV9DRUVJKGNoKSwgcmVncy0+Y2VlaSk7CisJfQog fQogRVhQT1JUX1NZTUJPTF9HUEwoZnNsX2VkbWFfZGlzYWJsZV9yZXF1ZXN0KTsKIApkaWZmIC0t Z2l0IGEvZHJpdmVycy9kbWEvbWNmLWVkbWEuYyBiL2RyaXZlcnMvZG1hL21jZi1lZG1hLmMKbmV3 IGZpbGUgbW9kZSAxMDA2NDQKaW5kZXggMDAwMDAwMDAwMDAwLi5kNGIyZmQ4NzFmZjQKLS0tIC9k ZXYvbnVsbAorKysgYi9kcml2ZXJzL2RtYS9tY2YtZWRtYS5jCkBAIC0wLDAgKzEsMzE1IEBACisv LyBTUERYLUxpY2Vuc2UtSWRlbnRpZmllcjogR1BMLTIuMCsKKy8vCisvLyBDb3B5cmlnaHQgKGMp IDIwMTMtMjAxNCBGcmVlc2NhbGUgU2VtaWNvbmR1Y3RvciwgSW5jCisvLyBDb3B5cmlnaHQgKGMp IDIwMTcgU3lzYW0sIEFuZ2VsbyBEdXJlZ2hlbGxvICA8YW5nZWxvQHN5c2FtLml0PgorCisjaW5j bHVkZSA8bGludXgvbW9kdWxlLmg+CisjaW5jbHVkZSA8bGludXgvaW50ZXJydXB0Lmg+CisjaW5j bHVkZSA8bGludXgvZG1hZW5naW5lLmg+CisjaW5jbHVkZSA8bGludXgvcGxhdGZvcm1fZGV2aWNl Lmg+CisjaW5jbHVkZSA8bGludXgvcGxhdGZvcm1fZGF0YS9kbWEtbWNmLWVkbWEuaD4KKworI2lu Y2x1ZGUgImZzbC1lZG1hLWNvbW1vbi5oIgorCisjZGVmaW5lIEVETUFfQ0hBTk5FTFMJCTY0Cisj ZGVmaW5lIEVETUFfTUFTS19DSCh4KQkJKCh4KSAmIEdFTk1BU0soNSwgMCkpCisKK3N0YXRpYyBp cnFyZXR1cm5fdCBtY2ZfZWRtYV90eF9oYW5kbGVyKGludCBpcnEsIHZvaWQgKmRldl9pZCkKK3sK KwlzdHJ1Y3QgZnNsX2VkbWFfZW5naW5lICptY2ZfZWRtYSA9IGRldl9pZDsKKwlzdHJ1Y3QgZWRt YV9yZWdzICpyZWdzID0gJm1jZl9lZG1hLT5yZWdzOworCXVuc2lnbmVkIGludCBjaDsKKwlzdHJ1 Y3QgZnNsX2VkbWFfY2hhbiAqbWNmX2NoYW47CisJdTY0IGludG1hcDsKKworCWludG1hcCA9IGlv cmVhZDMyKHJlZ3MtPmludGgpOworCWludG1hcCA8PD0gMzI7CisJaW50bWFwIHw9IGlvcmVhZDMy KHJlZ3MtPmludGwpOworCWlmICghaW50bWFwKQorCQlyZXR1cm4gSVJRX05PTkU7CisKKwlmb3Ig KGNoID0gMDsgY2ggPCBtY2ZfZWRtYS0+bl9jaGFuczsgY2grKykgeworCQlpZiAoaW50bWFwICYg QklUKGNoKSkgeworCQkJaW93cml0ZTgoRURNQV9NQVNLX0NIKGNoKSwgcmVncy0+Y2ludCk7CisK KwkJCW1jZl9jaGFuID0gJm1jZl9lZG1hLT5jaGFuc1tjaF07CisKKwkJCXNwaW5fbG9jaygmbWNm X2NoYW4tPnZjaGFuLmxvY2spOworCQkJaWYgKCFtY2ZfY2hhbi0+ZWRlc2MtPmlzY3ljbGljKSB7 CisJCQkJbGlzdF9kZWwoJm1jZl9jaGFuLT5lZGVzYy0+dmRlc2Mubm9kZSk7CisJCQkJdmNoYW5f Y29va2llX2NvbXBsZXRlKCZtY2ZfY2hhbi0+ZWRlc2MtPnZkZXNjKTsKKwkJCQltY2ZfY2hhbi0+ ZWRlc2MgPSBOVUxMOworCQkJCW1jZl9jaGFuLT5zdGF0dXMgPSBETUFfQ09NUExFVEU7CisJCQkJ bWNmX2NoYW4tPmlkbGUgPSB0cnVlOworCQkJfSBlbHNlIHsKKwkJCQl2Y2hhbl9jeWNsaWNfY2Fs bGJhY2soJm1jZl9jaGFuLT5lZGVzYy0+dmRlc2MpOworCQkJfQorCisJCQlpZiAoIW1jZl9jaGFu LT5lZGVzYykKKwkJCQlmc2xfZWRtYV94ZmVyX2Rlc2MobWNmX2NoYW4pOworCisJCQlzcGluX3Vu bG9jaygmbWNmX2NoYW4tPnZjaGFuLmxvY2spOworCQl9CisJfQorCisJcmV0dXJuIElSUV9IQU5E TEVEOworfQorCitzdGF0aWMgaXJxcmV0dXJuX3QgbWNmX2VkbWFfZXJyX2hhbmRsZXIoaW50IGly cSwgdm9pZCAqZGV2X2lkKQoreworCXN0cnVjdCBmc2xfZWRtYV9lbmdpbmUgKm1jZl9lZG1hID0g ZGV2X2lkOworCXN0cnVjdCBlZG1hX3JlZ3MgKnJlZ3MgPSAmbWNmX2VkbWEtPnJlZ3M7CisJdW5z aWduZWQgaW50IGVyciwgY2g7CisKKwllcnIgPSBpb3JlYWQzMihyZWdzLT5lcnJsKTsKKwlpZiAo IWVycikKKwkJcmV0dXJuIElSUV9OT05FOworCisJZm9yIChjaCA9IDA7IGNoIDwgKEVETUFfQ0hB Tk5FTFMgLyAyKTsgY2grKykgeworCQlpZiAoZXJyICYgQklUKGNoKSkgeworCQkJZnNsX2VkbWFf ZGlzYWJsZV9yZXF1ZXN0KCZtY2ZfZWRtYS0+Y2hhbnNbY2hdKTsKKwkJCWlvd3JpdGU4KEVETUFf Q0VSUl9DRVJSKGNoKSwgcmVncy0+Y2Vycik7CisJCQltY2ZfZWRtYS0+Y2hhbnNbY2hdLnN0YXR1 cyA9IERNQV9FUlJPUjsKKwkJCW1jZl9lZG1hLT5jaGFuc1tjaF0uaWRsZSA9IHRydWU7CisJCX0K Kwl9CisKKwllcnIgPSBpb3JlYWQzMihyZWdzLT5lcnJoKTsKKwlpZiAoIWVycikKKwkJcmV0dXJu IElSUV9OT05FOworCisJZm9yIChjaCA9IChFRE1BX0NIQU5ORUxTIC8gMik7IGNoIDwgRURNQV9D SEFOTkVMUzsgY2grKykgeworCQlpZiAoZXJyICYgKEJJVChjaCAtIChFRE1BX0NIQU5ORUxTIC8g MikpKSkgeworCQkJZnNsX2VkbWFfZGlzYWJsZV9yZXF1ZXN0KCZtY2ZfZWRtYS0+Y2hhbnNbY2hd KTsKKwkJCWlvd3JpdGU4KEVETUFfQ0VSUl9DRVJSKGNoKSwgcmVncy0+Y2Vycik7CisJCQltY2Zf ZWRtYS0+Y2hhbnNbY2hdLnN0YXR1cyA9IERNQV9FUlJPUjsKKwkJCW1jZl9lZG1hLT5jaGFuc1tj aF0uaWRsZSA9IHRydWU7CisJCX0KKwl9CisKKwlyZXR1cm4gSVJRX0hBTkRMRUQ7Cit9CisKK3N0 YXRpYyBpbnQgbWNmX2VkbWFfaXJxX2luaXQoc3RydWN0IHBsYXRmb3JtX2RldmljZSAqcGRldiwK KwkJCQlzdHJ1Y3QgZnNsX2VkbWFfZW5naW5lICptY2ZfZWRtYSkKK3sKKwlpbnQgcmV0ID0gMCwg aTsKKwlzdHJ1Y3QgcmVzb3VyY2UgKnJlczsKKworCXJlcyA9IHBsYXRmb3JtX2dldF9yZXNvdXJj ZV9ieW5hbWUocGRldiwKKwkJCQlJT1JFU09VUkNFX0lSUSwgImVkbWEtdHgtMDAtMTUiKTsKKwlp ZiAoIXJlcykKKwkJcmV0dXJuIC0xOworCisJZm9yIChyZXQgPSAwLCBpID0gcmVzLT5zdGFydDsg aSA8PSByZXMtPmVuZDsgKytpKQorCQlyZXQgfD0gcmVxdWVzdF9pcnEoaSwgbWNmX2VkbWFfdHhf aGFuZGxlciwgMCwgImVETUEiLCBtY2ZfZWRtYSk7CisJaWYgKHJldCkKKwkJcmV0dXJuIHJldDsK KworCXJlcyA9IHBsYXRmb3JtX2dldF9yZXNvdXJjZV9ieW5hbWUocGRldiwKKwkJCUlPUkVTT1VS Q0VfSVJRLCAiZWRtYS10eC0xNi01NSIpOworCWlmICghcmVzKQorCQlyZXR1cm4gLTE7CisKKwlm b3IgKHJldCA9IDAsIGkgPSByZXMtPnN0YXJ0OyBpIDw9IHJlcy0+ZW5kOyArK2kpCisJCXJldCB8 PSByZXF1ZXN0X2lycShpLCBtY2ZfZWRtYV90eF9oYW5kbGVyLCAwLCAiZURNQSIsIG1jZl9lZG1h KTsKKwlpZiAocmV0KQorCQlyZXR1cm4gcmV0OworCisJcmV0ID0gcGxhdGZvcm1fZ2V0X2lycV9i eW5hbWUocGRldiwgImVkbWEtdHgtNTYtNjMiKTsKKwlpZiAocmV0ICE9IC1FTlhJTykgeworCQly ZXQgPSByZXF1ZXN0X2lycShyZXQsIG1jZl9lZG1hX3R4X2hhbmRsZXIsCisJCQkJICAwLCAiZURN QSIsIG1jZl9lZG1hKTsKKwkJaWYgKHJldCkKKwkJCXJldHVybiByZXQ7CisJfQorCisJcmV0ID0g cGxhdGZvcm1fZ2V0X2lycV9ieW5hbWUocGRldiwgImVkbWEtZXJyIik7CisJaWYgKHJldCAhPSAt RU5YSU8pIHsKKwkJcmV0ID0gcmVxdWVzdF9pcnEocmV0LCBtY2ZfZWRtYV9lcnJfaGFuZGxlciwK KwkJCQkgIDAsICJlRE1BIiwgbWNmX2VkbWEpOworCQlpZiAocmV0KQorCQkJcmV0dXJuIHJldDsK Kwl9CisKKwlyZXR1cm4gMDsKK30KKworc3RhdGljIHZvaWQgbWNmX2VkbWFfaXJxX2ZyZWUoc3Ry dWN0IHBsYXRmb3JtX2RldmljZSAqcGRldiwKKwkJCQlzdHJ1Y3QgZnNsX2VkbWFfZW5naW5lICpt Y2ZfZWRtYSkKK3sKKwlpbnQgaXJxOworCXN0cnVjdCByZXNvdXJjZSAqcmVzOworCisJcmVzID0g cGxhdGZvcm1fZ2V0X3Jlc291cmNlX2J5bmFtZShwZGV2LAorCQkJSU9SRVNPVVJDRV9JUlEsICJl ZG1hLXR4LTAwLTE1Iik7CisJaWYgKHJlcykgeworCQlmb3IgKGlycSA9IHJlcy0+c3RhcnQ7IGly cSA8PSByZXMtPmVuZDsgaXJxKyspCisJCQlmcmVlX2lycShpcnEsIG1jZl9lZG1hKTsKKwl9CisK KwlyZXMgPSBwbGF0Zm9ybV9nZXRfcmVzb3VyY2VfYnluYW1lKHBkZXYsCisJCQlJT1JFU09VUkNF X0lSUSwgImVkbWEtdHgtMTYtNTUiKTsKKwlpZiAocmVzKSB7CisJCWZvciAoaXJxID0gcmVzLT5z dGFydDsgaXJxIDw9IHJlcy0+ZW5kOyBpcnErKykKKwkJCWZyZWVfaXJxKGlycSwgbWNmX2VkbWEp OworCX0KKworCWlycSA9IHBsYXRmb3JtX2dldF9pcnFfYnluYW1lKHBkZXYsICJlZG1hLXR4LTU2 LTYzIik7CisJaWYgKGlycSAhPSAtRU5YSU8pCisJCWZyZWVfaXJxKGlycSwgbWNmX2VkbWEpOwor CisJaXJxID0gcGxhdGZvcm1fZ2V0X2lycV9ieW5hbWUocGRldiwgImVkbWEtZXJyIik7CisJaWYg KGlycSAhPSAtRU5YSU8pCisJCWZyZWVfaXJxKGlycSwgbWNmX2VkbWEpOworfQorCitzdGF0aWMg aW50IG1jZl9lZG1hX3Byb2JlKHN0cnVjdCBwbGF0Zm9ybV9kZXZpY2UgKnBkZXYpCit7CisJc3Ry dWN0IG1jZl9lZG1hX3BsYXRmb3JtX2RhdGEgKnBkYXRhOworCXN0cnVjdCBmc2xfZWRtYV9lbmdp bmUgKm1jZl9lZG1hOworCXN0cnVjdCBmc2xfZWRtYV9jaGFuICptY2ZfY2hhbjsKKwlzdHJ1Y3Qg ZWRtYV9yZWdzICpyZWdzOworCXN0cnVjdCByZXNvdXJjZSAqcmVzOworCWludCByZXQsIGksIGxl biwgY2hhbnM7CisKKwlwZGF0YSA9IGRldl9nZXRfcGxhdGRhdGEoJnBkZXYtPmRldik7CisJaWYg KCFwZGF0YSkKKwkJcmV0dXJuIFBUUl9FUlIocGRhdGEpOworCisJY2hhbnMgPSBwZGF0YS0+ZG1h X2NoYW5uZWxzOworCWxlbiA9IHNpemVvZigqbWNmX2VkbWEpICsgc2l6ZW9mKCptY2ZfY2hhbikg KiBjaGFuczsKKwltY2ZfZWRtYSA9IGRldm1fa3phbGxvYygmcGRldi0+ZGV2LCBsZW4sIEdGUF9L RVJORUwpOworCWlmICghbWNmX2VkbWEpCisJCXJldHVybiAtRU5PTUVNOworCisJbWNmX2VkbWEt Pm5fY2hhbnMgPSBjaGFuczsKKworCS8qIFNldCB1cCB2ZXJzaW9uIGZvciBDb2xkRmlyZSBlZG1h ICovCisJbWNmX2VkbWEtPnZlcnNpb24gPSB2MjsKKwltY2ZfZWRtYS0+YmlnX2VuZGlhbiA9IDE7 CisKKwlpZiAoIW1jZl9lZG1hLT5uX2NoYW5zKSB7CisJCWRldl9pbmZvKCZwZGV2LT5kZXYsICJz ZXR0aW5nIGRlZmF1bHQgY2hhbm5lbCBudW1iZXIgdG8gNjQiKTsKKwkJbWNmX2VkbWEtPm5fY2hh bnMgPSA2NDsKKwl9CisKKwltdXRleF9pbml0KCZtY2ZfZWRtYS0+ZnNsX2VkbWFfbXV0ZXgpOwor CisJcmVzID0gcGxhdGZvcm1fZ2V0X3Jlc291cmNlKHBkZXYsIElPUkVTT1VSQ0VfTUVNLCAwKTsK KworCW1jZl9lZG1hLT5tZW1iYXNlID0gZGV2bV9pb3JlbWFwX3Jlc291cmNlKCZwZGV2LT5kZXYs IHJlcyk7CisJaWYgKElTX0VSUihtY2ZfZWRtYS0+bWVtYmFzZSkpCisJCXJldHVybiBQVFJfRVJS KG1jZl9lZG1hLT5tZW1iYXNlKTsKKworCWZzbF9lZG1hX3NldHVwX3JlZ3MobWNmX2VkbWEpOwor CXJlZ3MgPSAmbWNmX2VkbWEtPnJlZ3M7CisKKwlJTklUX0xJU1RfSEVBRCgmbWNmX2VkbWEtPmRt YV9kZXYuY2hhbm5lbHMpOworCWZvciAoaSA9IDA7IGkgPCBtY2ZfZWRtYS0+bl9jaGFuczsgaSsr KSB7CisJCXN0cnVjdCBmc2xfZWRtYV9jaGFuICptY2ZfY2hhbiA9ICZtY2ZfZWRtYS0+Y2hhbnNb aV07CisKKwkJbWNmX2NoYW4tPmVkbWEgPSBtY2ZfZWRtYTsKKwkJbWNmX2NoYW4tPnNsYXZlX2lk ID0gaTsKKwkJbWNmX2NoYW4tPmlkbGUgPSB0cnVlOworCQltY2ZfY2hhbi0+dmNoYW4uZGVzY19m cmVlID0gZnNsX2VkbWFfZnJlZV9kZXNjOworCQl2Y2hhbl9pbml0KCZtY2ZfY2hhbi0+dmNoYW4s ICZtY2ZfZWRtYS0+ZG1hX2Rldik7CisJCWlvd3JpdGUzMigweDAsICZyZWdzLT50Y2RbaV0uY3Ny KTsKKwl9CisKKwlpb3dyaXRlMzIofjAsIHJlZ3MtPmludGgpOworCWlvd3JpdGUzMih+MCwgcmVn cy0+aW50bCk7CisKKwlyZXQgPSBtY2ZfZWRtYV9pcnFfaW5pdChwZGV2LCBtY2ZfZWRtYSk7CisJ aWYgKHJldCkKKwkJcmV0dXJuIHJldDsKKworCWRtYV9jYXBfc2V0KERNQV9QUklWQVRFLCBtY2Zf ZWRtYS0+ZG1hX2Rldi5jYXBfbWFzayk7CisJZG1hX2NhcF9zZXQoRE1BX1NMQVZFLCBtY2ZfZWRt YS0+ZG1hX2Rldi5jYXBfbWFzayk7CisJZG1hX2NhcF9zZXQoRE1BX0NZQ0xJQywgbWNmX2VkbWEt PmRtYV9kZXYuY2FwX21hc2spOworCisJbWNmX2VkbWEtPmRtYV9kZXYuZGV2ID0gJnBkZXYtPmRl djsKKwltY2ZfZWRtYS0+ZG1hX2Rldi5kZXZpY2VfYWxsb2NfY2hhbl9yZXNvdXJjZXMgPQorCQkJ ZnNsX2VkbWFfYWxsb2NfY2hhbl9yZXNvdXJjZXM7CisJbWNmX2VkbWEtPmRtYV9kZXYuZGV2aWNl X2ZyZWVfY2hhbl9yZXNvdXJjZXMgPQorCQkJZnNsX2VkbWFfZnJlZV9jaGFuX3Jlc291cmNlczsK KwltY2ZfZWRtYS0+ZG1hX2Rldi5kZXZpY2VfY29uZmlnID0gZnNsX2VkbWFfc2xhdmVfY29uZmln OworCW1jZl9lZG1hLT5kbWFfZGV2LmRldmljZV9wcmVwX2RtYV9jeWNsaWMgPQorCQkJZnNsX2Vk bWFfcHJlcF9kbWFfY3ljbGljOworCW1jZl9lZG1hLT5kbWFfZGV2LmRldmljZV9wcmVwX3NsYXZl X3NnID0gZnNsX2VkbWFfcHJlcF9zbGF2ZV9zZzsKKwltY2ZfZWRtYS0+ZG1hX2Rldi5kZXZpY2Vf dHhfc3RhdHVzID0gZnNsX2VkbWFfdHhfc3RhdHVzOworCW1jZl9lZG1hLT5kbWFfZGV2LmRldmlj ZV9wYXVzZSA9IGZzbF9lZG1hX3BhdXNlOworCW1jZl9lZG1hLT5kbWFfZGV2LmRldmljZV9yZXN1 bWUgPSBmc2xfZWRtYV9yZXN1bWU7CisJbWNmX2VkbWEtPmRtYV9kZXYuZGV2aWNlX3Rlcm1pbmF0 ZV9hbGwgPSBmc2xfZWRtYV90ZXJtaW5hdGVfYWxsOworCW1jZl9lZG1hLT5kbWFfZGV2LmRldmlj ZV9pc3N1ZV9wZW5kaW5nID0gZnNsX2VkbWFfaXNzdWVfcGVuZGluZzsKKworCW1jZl9lZG1hLT5k bWFfZGV2LnNyY19hZGRyX3dpZHRocyA9IEZTTF9FRE1BX0JVU1dJRFRIUzsKKwltY2ZfZWRtYS0+ ZG1hX2Rldi5kc3RfYWRkcl93aWR0aHMgPSBGU0xfRURNQV9CVVNXSURUSFM7CisJbWNmX2VkbWEt PmRtYV9kZXYuZGlyZWN0aW9ucyA9CisJCQlCSVQoRE1BX0RFVl9UT19NRU0pIHwgQklUKERNQV9N RU1fVE9fREVWKTsKKworCW1jZl9lZG1hLT5kbWFfZGV2LmZpbHRlci5mbiA9IG1jZl9lZG1hX2Zp bHRlcl9mbjsKKwltY2ZfZWRtYS0+ZG1hX2Rldi5maWx0ZXIubWFwID0gcGRhdGEtPnNsYXZlX21h cDsKKwltY2ZfZWRtYS0+ZG1hX2Rldi5maWx0ZXIubWFwY250ID0gcGRhdGEtPnNsYXZlY250Owor CisJcGxhdGZvcm1fc2V0X2RydmRhdGEocGRldiwgbWNmX2VkbWEpOworCisJcmV0ID0gZG1hX2Fz eW5jX2RldmljZV9yZWdpc3RlcigmbWNmX2VkbWEtPmRtYV9kZXYpOworCWlmIChyZXQpIHsKKwkJ ZGV2X2VycigmcGRldi0+ZGV2LAorCQkJIkNhbid0IHJlZ2lzdGVyIEZyZWVzY2FsZSBlRE1BIGVu Z2luZS4gKCVkKVxuIiwgcmV0KTsKKwkJcmV0dXJuIHJldDsKKwl9CisKKwkvKiBFbmFibGUgcm91 bmQgcm9iaW4gYXJiaXRyYXRpb24gKi8KKwlpb3dyaXRlMzIoRURNQV9DUl9FUkdBIHwgRURNQV9D Ul9FUkNBLCByZWdzLT5jcik7CisKKwlyZXR1cm4gMDsKK30KKworc3RhdGljIGludCBtY2ZfZWRt YV9yZW1vdmUoc3RydWN0IHBsYXRmb3JtX2RldmljZSAqcGRldikKK3sKKwlzdHJ1Y3QgZnNsX2Vk bWFfZW5naW5lICptY2ZfZWRtYSA9IHBsYXRmb3JtX2dldF9kcnZkYXRhKHBkZXYpOworCisJbWNm X2VkbWFfaXJxX2ZyZWUocGRldiwgbWNmX2VkbWEpOworCWZzbF9lZG1hX2NsZWFudXBfdmNoYW4o Jm1jZl9lZG1hLT5kbWFfZGV2KTsKKwlkbWFfYXN5bmNfZGV2aWNlX3VucmVnaXN0ZXIoJm1jZl9l ZG1hLT5kbWFfZGV2KTsKKworCXJldHVybiAwOworfQorCitzdGF0aWMgc3RydWN0IHBsYXRmb3Jt X2RyaXZlciBtY2ZfZWRtYV9kcml2ZXIgPSB7CisJLmRyaXZlcgkJPSB7CisJCS5uYW1lCT0gIm1j Zi1lZG1hIiwKKwl9LAorCS5wcm9iZQkJPSBtY2ZfZWRtYV9wcm9iZSwKKwkucmVtb3ZlCQk9IG1j Zl9lZG1hX3JlbW92ZSwKK307CisKK2Jvb2wgbWNmX2VkbWFfZmlsdGVyX2ZuKHN0cnVjdCBkbWFf Y2hhbiAqY2hhbiwgdm9pZCAqcGFyYW0pCit7CisJaWYgKGNoYW4tPmRldmljZS0+ZGV2LT5kcml2 ZXIgPT0gJm1jZl9lZG1hX2RyaXZlci5kcml2ZXIpIHsKKwkJc3RydWN0IGZzbF9lZG1hX2NoYW4g Km1jZl9jaGFuID0gdG9fZnNsX2VkbWFfY2hhbihjaGFuKTsKKworCQlyZXR1cm4gKG1jZl9jaGFu LT5zbGF2ZV9pZCA9PSAoaW50KXBhcmFtKTsKKwl9CisKKwlyZXR1cm4gZmFsc2U7Cit9CitFWFBP UlRfU1lNQk9MKG1jZl9lZG1hX2ZpbHRlcl9mbik7CisKK3N0YXRpYyBpbnQgX19pbml0IG1jZl9l ZG1hX2luaXQodm9pZCkKK3sKKwlyZXR1cm4gcGxhdGZvcm1fZHJpdmVyX3JlZ2lzdGVyKCZtY2Zf ZWRtYV9kcml2ZXIpOworfQorc3Vic3lzX2luaXRjYWxsKG1jZl9lZG1hX2luaXQpOworCitzdGF0 aWMgdm9pZCBfX2V4aXQgbWNmX2VkbWFfZXhpdCh2b2lkKQoreworCXBsYXRmb3JtX2RyaXZlcl91 bnJlZ2lzdGVyKCZtY2ZfZWRtYV9kcml2ZXIpOworfQorbW9kdWxlX2V4aXQobWNmX2VkbWFfZXhp dCk7CisKK01PRFVMRV9BTElBUygicGxhdGZvcm06bWNmLWVkbWEiKTsKK01PRFVMRV9ERVNDUklQ VElPTigiRnJlZXNjYWxlIGVETUEgZW5naW5lIGRyaXZlciwgQ29sZEZpcmUgZmFtaWx5Iik7CitN T0RVTEVfTElDRU5TRSgiR1BMIHYyIik7CmRpZmYgLS1naXQgYS9pbmNsdWRlL2xpbnV4L3BsYXRm b3JtX2RhdGEvZG1hLW1jZi1lZG1hLmggYi9pbmNsdWRlL2xpbnV4L3BsYXRmb3JtX2RhdGEvZG1h LW1jZi1lZG1hLmgKbmV3IGZpbGUgbW9kZSAxMDA2NDQKaW5kZXggMDAwMDAwMDAwMDAwLi5kNzE4 Y2NmYTM0MjEKLS0tIC9kZXYvbnVsbAorKysgYi9pbmNsdWRlL2xpbnV4L3BsYXRmb3JtX2RhdGEv ZG1hLW1jZi1lZG1hLmgKQEAgLTAsMCArMSwzOCBAQAorLyogU1BEWC1MaWNlbnNlLUlkZW50aWZp ZXI6IEdQTC0yLjAgKi8KKy8qCisgKiBGcmVlc2NhbGUgZURNQSBwbGF0Zm9ybSBkYXRhLCBDb2xk RmlyZSBTb0MncyBmYW1pbHkuCisgKgorICogQ29weXJpZ2h0IChjKSAyMDE3IEFuZ2VsbyBEdXJl Z2hlbGxvIDxhbmdlbG9Ac3lzYW0uaXQ+CisgKgorICogVGhpcyBwcm9ncmFtIGlzIGZyZWUgc29m dHdhcmU7IHlvdSBjYW4gcmVkaXN0cmlidXRlIGl0IGFuZC9vciBtb2RpZnkKKyAqIGl0IHVuZGVy IHRoZSB0ZXJtcyBvZiB0aGUgR05VIEdlbmVyYWwgUHVibGljIExpY2Vuc2UgdmVyc2lvbiAyIGFz CisgKiBwdWJsaXNoZWQgYnkgdGhlIEZyZWUgU29mdHdhcmUgRm91bmRhdGlvbi4KKyAqCisgKiBU aGlzIHByb2dyYW0gaXMgZGlzdHJpYnV0ZWQgaW4gdGhlIGhvcGUgdGhhdCBpdCB3aWxsIGJlIHVz ZWZ1bCwKKyAqIGJ1dCBXSVRIT1VUIEFOWSBXQVJSQU5UWTsgd2l0aG91dCBldmVuIHRoZSBpbXBs aWVkIHdhcnJhbnR5IG9mCisgKiBNRVJDSEFOVEFCSUxJVFkgb3IgRklUTkVTUyBGT1IgQSBQQVJU SUNVTEFSIFBVUlBPU0UuICBTZWUgdGhlCisgKiBHTlUgR2VuZXJhbCBQdWJsaWMgTGljZW5zZSBm b3IgbW9yZSBkZXRhaWxzLgorICovCisKKyNpZm5kZWYgX19MSU5VWF9QTEFURk9STV9EQVRBX01D Rl9FRE1BX0hfXworI2RlZmluZSBfX0xJTlVYX1BMQVRGT1JNX0RBVEFfTUNGX0VETUFfSF9fCisK K3N0cnVjdCBkbWFfc2xhdmVfbWFwOworCitib29sIG1jZl9lZG1hX2ZpbHRlcl9mbihzdHJ1Y3Qg ZG1hX2NoYW4gKmNoYW4sIHZvaWQgKnBhcmFtKTsKKworI2RlZmluZSBNQ0ZfRURNQV9GSUxURVJf UEFSQU0oY2gpCSgodm9pZCAqKWNoKQorCisvKioKKyAqIHN0cnVjdCBtY2ZfZWRtYV9wbGF0Zm9y bV9kYXRhIC0gcGxhdGZvcm0gc3BlY2lmaWMgZGF0YSBmb3IgZURNQSBlbmdpbmUKKyAqCisgKiBA dmVyCQkJVGhlIGVETUEgbW9kdWxlIHZlcnNpb24uCisgKiBAZG1hX2NoYW5uZWxzCVRoZSBudW1i ZXIgb2YgZURNQSBjaGFubmVscy4KKyAqLworc3RydWN0IG1jZl9lZG1hX3BsYXRmb3JtX2RhdGEg eworCWludCBkbWFfY2hhbm5lbHM7CisJY29uc3Qgc3RydWN0IGRtYV9zbGF2ZV9tYXAgKnNsYXZl X21hcDsKKwlpbnQgc2xhdmVjbnQ7Cit9OworCisjZW5kaWYgLyogX19MSU5VWF9QTEFURk9STV9E QVRBX01DRl9FRE1BX0hfXyAqLwo= From mboxrd@z Thu Jan 1 00:00:00 1970 From: Angelo Dureghello Subject: [PATCH v9 4/4] dmaengine: fsl-edma: add ColdFire mcf5441x edma support Date: Sat, 11 Aug 2018 13:26:49 +0200 Message-ID: <20180811112649.20752-4-angelo@sysam.it> References: <20180811112649.20752-1-angelo@sysam.it> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20180811112649.20752-1-angelo@sysam.it> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: vinod.koul@linaro.org Cc: linux-m68k@vger.kernel.org, Angelo Dureghello , krzk@kernel.org, stefan@agner.ch, dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org List-Id: linux-m68k@vger.kernel.org This patch adds support for ColdFire mcf5441x-family edma module. The ColdFire edma module is slightly different from fsl-edma, so a new driver is added. But most of the code is common between fsl-edma and mcf-edma so it has been collected into a separate common module fsl-edma-common (patch 1/3). Signed-off-by: Angelo Dureghello --- Changes for v8: - patch rewritten from scratch, this patch (3/3) has just been added. Changes for v9: - add compile test for Kconfig, - fix include guard. --- drivers/dma/Kconfig | 11 + drivers/dma/Makefile | 1 + drivers/dma/fsl-edma-common.c | 24 +- drivers/dma/mcf-edma.c | 315 +++++++++++++++++++++ include/linux/platform_data/dma-mcf-edma.h | 38 +++ 5 files changed, 385 insertions(+), 4 deletions(-) create mode 100644 drivers/dma/mcf-edma.c create mode 100644 include/linux/platform_data/dma-mcf-edma.h diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index ca1680afa20a..45ca5e556774 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -320,6 +320,17 @@ config LPC18XX_DMAMUX Enable support for DMA on NXP LPC18xx/43xx platforms with PL080 and multiplexed DMA request lines. +config MCF_EDMA + tristate "Freescale eDMA engine support, ColdFire mcf5441x SoCs" + depends on M5441x || COMPILE_TEST + select DMA_ENGINE + select DMA_VIRTUAL_CHANNELS + help + Support the Freescale ColdFire eDMA engine, 64-channel + implementation that performs complex data transfers with + minimal intervention from a host processor. + This module can be found on Freescale ColdFire mcf5441x SoCs. + config MMP_PDMA bool "MMP PDMA support" depends on ARCH_MMP || ARCH_PXA || COMPILE_TEST diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index 66022f59fca4..d97f317f4b34 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -32,6 +32,7 @@ obj-$(CONFIG_DW_DMAC_CORE) += dw/ obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o obj-$(CONFIG_FSL_DMA) += fsldma.o obj-$(CONFIG_FSL_EDMA) += fsl-edma.o fsl-edma-common.o +obj-$(CONFIG_MCF_EDMA) += mcf-edma.o fsl-edma-common.o obj-$(CONFIG_FSL_RAID) += fsl_raid.o obj-$(CONFIG_HSU_DMA) += hsu/ obj-$(CONFIG_IMG_MDC_DMA) += img-mdc-dma.o diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c index 227034de256e..8ba80f4b6f55 100644 --- a/drivers/dma/fsl-edma-common.c +++ b/drivers/dma/fsl-edma-common.c @@ -46,8 +46,16 @@ static void fsl_edma_enable_request(struct fsl_edma_chan *fsl_chan) struct edma_regs *regs = &fsl_chan->edma->regs; u32 ch = fsl_chan->vchan.chan.chan_id; - edma_writeb(fsl_chan->edma, EDMA_SEEI_SEEI(ch), regs->seei); - edma_writeb(fsl_chan->edma, ch, regs->serq); + if (fsl_chan->edma->version == v1) { + edma_writeb(fsl_chan->edma, EDMA_SEEI_SEEI(ch), regs->seei); + edma_writeb(fsl_chan->edma, ch, regs->serq); + } else { + /* ColdFire is big endian, and accesses natively + * big endian I/O peripherals + */ + iowrite8(EDMA_SEEI_SEEI(ch), regs->seei); + iowrite8(ch, regs->serq); + } } void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan) @@ -55,8 +63,16 @@ void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan) struct edma_regs *regs = &fsl_chan->edma->regs; u32 ch = fsl_chan->vchan.chan.chan_id; - edma_writeb(fsl_chan->edma, ch, regs->cerq); - edma_writeb(fsl_chan->edma, EDMA_CEEI_CEEI(ch), regs->ceei); + if (fsl_chan->edma->version == v1) { + edma_writeb(fsl_chan->edma, ch, regs->cerq); + edma_writeb(fsl_chan->edma, EDMA_CEEI_CEEI(ch), regs->ceei); + } else { + /* ColdFire is big endian, and accesses natively + * big endian I/O peripherals + */ + iowrite8(ch, regs->cerq); + iowrite8(EDMA_CEEI_CEEI(ch), regs->ceei); + } } EXPORT_SYMBOL_GPL(fsl_edma_disable_request); diff --git a/drivers/dma/mcf-edma.c b/drivers/dma/mcf-edma.c new file mode 100644 index 000000000000..d4b2fd871ff4 --- /dev/null +++ b/drivers/dma/mcf-edma.c @@ -0,0 +1,315 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright (c) 2013-2014 Freescale Semiconductor, Inc +// Copyright (c) 2017 Sysam, Angelo Dureghello + +#include +#include +#include +#include +#include + +#include "fsl-edma-common.h" + +#define EDMA_CHANNELS 64 +#define EDMA_MASK_CH(x) ((x) & GENMASK(5, 0)) + +static irqreturn_t mcf_edma_tx_handler(int irq, void *dev_id) +{ + struct fsl_edma_engine *mcf_edma = dev_id; + struct edma_regs *regs = &mcf_edma->regs; + unsigned int ch; + struct fsl_edma_chan *mcf_chan; + u64 intmap; + + intmap = ioread32(regs->inth); + intmap <<= 32; + intmap |= ioread32(regs->intl); + if (!intmap) + return IRQ_NONE; + + for (ch = 0; ch < mcf_edma->n_chans; ch++) { + if (intmap & BIT(ch)) { + iowrite8(EDMA_MASK_CH(ch), regs->cint); + + mcf_chan = &mcf_edma->chans[ch]; + + spin_lock(&mcf_chan->vchan.lock); + if (!mcf_chan->edesc->iscyclic) { + list_del(&mcf_chan->edesc->vdesc.node); + vchan_cookie_complete(&mcf_chan->edesc->vdesc); + mcf_chan->edesc = NULL; + mcf_chan->status = DMA_COMPLETE; + mcf_chan->idle = true; + } else { + vchan_cyclic_callback(&mcf_chan->edesc->vdesc); + } + + if (!mcf_chan->edesc) + fsl_edma_xfer_desc(mcf_chan); + + spin_unlock(&mcf_chan->vchan.lock); + } + } + + return IRQ_HANDLED; +} + +static irqreturn_t mcf_edma_err_handler(int irq, void *dev_id) +{ + struct fsl_edma_engine *mcf_edma = dev_id; + struct edma_regs *regs = &mcf_edma->regs; + unsigned int err, ch; + + err = ioread32(regs->errl); + if (!err) + return IRQ_NONE; + + for (ch = 0; ch < (EDMA_CHANNELS / 2); ch++) { + if (err & BIT(ch)) { + fsl_edma_disable_request(&mcf_edma->chans[ch]); + iowrite8(EDMA_CERR_CERR(ch), regs->cerr); + mcf_edma->chans[ch].status = DMA_ERROR; + mcf_edma->chans[ch].idle = true; + } + } + + err = ioread32(regs->errh); + if (!err) + return IRQ_NONE; + + for (ch = (EDMA_CHANNELS / 2); ch < EDMA_CHANNELS; ch++) { + if (err & (BIT(ch - (EDMA_CHANNELS / 2)))) { + fsl_edma_disable_request(&mcf_edma->chans[ch]); + iowrite8(EDMA_CERR_CERR(ch), regs->cerr); + mcf_edma->chans[ch].status = DMA_ERROR; + mcf_edma->chans[ch].idle = true; + } + } + + return IRQ_HANDLED; +} + +static int mcf_edma_irq_init(struct platform_device *pdev, + struct fsl_edma_engine *mcf_edma) +{ + int ret = 0, i; + struct resource *res; + + res = platform_get_resource_byname(pdev, + IORESOURCE_IRQ, "edma-tx-00-15"); + if (!res) + return -1; + + for (ret = 0, i = res->start; i <= res->end; ++i) + ret |= request_irq(i, mcf_edma_tx_handler, 0, "eDMA", mcf_edma); + if (ret) + return ret; + + res = platform_get_resource_byname(pdev, + IORESOURCE_IRQ, "edma-tx-16-55"); + if (!res) + return -1; + + for (ret = 0, i = res->start; i <= res->end; ++i) + ret |= request_irq(i, mcf_edma_tx_handler, 0, "eDMA", mcf_edma); + if (ret) + return ret; + + ret = platform_get_irq_byname(pdev, "edma-tx-56-63"); + if (ret != -ENXIO) { + ret = request_irq(ret, mcf_edma_tx_handler, + 0, "eDMA", mcf_edma); + if (ret) + return ret; + } + + ret = platform_get_irq_byname(pdev, "edma-err"); + if (ret != -ENXIO) { + ret = request_irq(ret, mcf_edma_err_handler, + 0, "eDMA", mcf_edma); + if (ret) + return ret; + } + + return 0; +} + +static void mcf_edma_irq_free(struct platform_device *pdev, + struct fsl_edma_engine *mcf_edma) +{ + int irq; + struct resource *res; + + res = platform_get_resource_byname(pdev, + IORESOURCE_IRQ, "edma-tx-00-15"); + if (res) { + for (irq = res->start; irq <= res->end; irq++) + free_irq(irq, mcf_edma); + } + + res = platform_get_resource_byname(pdev, + IORESOURCE_IRQ, "edma-tx-16-55"); + if (res) { + for (irq = res->start; irq <= res->end; irq++) + free_irq(irq, mcf_edma); + } + + irq = platform_get_irq_byname(pdev, "edma-tx-56-63"); + if (irq != -ENXIO) + free_irq(irq, mcf_edma); + + irq = platform_get_irq_byname(pdev, "edma-err"); + if (irq != -ENXIO) + free_irq(irq, mcf_edma); +} + +static int mcf_edma_probe(struct platform_device *pdev) +{ + struct mcf_edma_platform_data *pdata; + struct fsl_edma_engine *mcf_edma; + struct fsl_edma_chan *mcf_chan; + struct edma_regs *regs; + struct resource *res; + int ret, i, len, chans; + + pdata = dev_get_platdata(&pdev->dev); + if (!pdata) + return PTR_ERR(pdata); + + chans = pdata->dma_channels; + len = sizeof(*mcf_edma) + sizeof(*mcf_chan) * chans; + mcf_edma = devm_kzalloc(&pdev->dev, len, GFP_KERNEL); + if (!mcf_edma) + return -ENOMEM; + + mcf_edma->n_chans = chans; + + /* Set up version for ColdFire edma */ + mcf_edma->version = v2; + mcf_edma->big_endian = 1; + + if (!mcf_edma->n_chans) { + dev_info(&pdev->dev, "setting default channel number to 64"); + mcf_edma->n_chans = 64; + } + + mutex_init(&mcf_edma->fsl_edma_mutex); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + + mcf_edma->membase = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(mcf_edma->membase)) + return PTR_ERR(mcf_edma->membase); + + fsl_edma_setup_regs(mcf_edma); + regs = &mcf_edma->regs; + + INIT_LIST_HEAD(&mcf_edma->dma_dev.channels); + for (i = 0; i < mcf_edma->n_chans; i++) { + struct fsl_edma_chan *mcf_chan = &mcf_edma->chans[i]; + + mcf_chan->edma = mcf_edma; + mcf_chan->slave_id = i; + mcf_chan->idle = true; + mcf_chan->vchan.desc_free = fsl_edma_free_desc; + vchan_init(&mcf_chan->vchan, &mcf_edma->dma_dev); + iowrite32(0x0, ®s->tcd[i].csr); + } + + iowrite32(~0, regs->inth); + iowrite32(~0, regs->intl); + + ret = mcf_edma_irq_init(pdev, mcf_edma); + if (ret) + return ret; + + dma_cap_set(DMA_PRIVATE, mcf_edma->dma_dev.cap_mask); + dma_cap_set(DMA_SLAVE, mcf_edma->dma_dev.cap_mask); + dma_cap_set(DMA_CYCLIC, mcf_edma->dma_dev.cap_mask); + + mcf_edma->dma_dev.dev = &pdev->dev; + mcf_edma->dma_dev.device_alloc_chan_resources = + fsl_edma_alloc_chan_resources; + mcf_edma->dma_dev.device_free_chan_resources = + fsl_edma_free_chan_resources; + mcf_edma->dma_dev.device_config = fsl_edma_slave_config; + mcf_edma->dma_dev.device_prep_dma_cyclic = + fsl_edma_prep_dma_cyclic; + mcf_edma->dma_dev.device_prep_slave_sg = fsl_edma_prep_slave_sg; + mcf_edma->dma_dev.device_tx_status = fsl_edma_tx_status; + mcf_edma->dma_dev.device_pause = fsl_edma_pause; + mcf_edma->dma_dev.device_resume = fsl_edma_resume; + mcf_edma->dma_dev.device_terminate_all = fsl_edma_terminate_all; + mcf_edma->dma_dev.device_issue_pending = fsl_edma_issue_pending; + + mcf_edma->dma_dev.src_addr_widths = FSL_EDMA_BUSWIDTHS; + mcf_edma->dma_dev.dst_addr_widths = FSL_EDMA_BUSWIDTHS; + mcf_edma->dma_dev.directions = + BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); + + mcf_edma->dma_dev.filter.fn = mcf_edma_filter_fn; + mcf_edma->dma_dev.filter.map = pdata->slave_map; + mcf_edma->dma_dev.filter.mapcnt = pdata->slavecnt; + + platform_set_drvdata(pdev, mcf_edma); + + ret = dma_async_device_register(&mcf_edma->dma_dev); + if (ret) { + dev_err(&pdev->dev, + "Can't register Freescale eDMA engine. (%d)\n", ret); + return ret; + } + + /* Enable round robin arbitration */ + iowrite32(EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr); + + return 0; +} + +static int mcf_edma_remove(struct platform_device *pdev) +{ + struct fsl_edma_engine *mcf_edma = platform_get_drvdata(pdev); + + mcf_edma_irq_free(pdev, mcf_edma); + fsl_edma_cleanup_vchan(&mcf_edma->dma_dev); + dma_async_device_unregister(&mcf_edma->dma_dev); + + return 0; +} + +static struct platform_driver mcf_edma_driver = { + .driver = { + .name = "mcf-edma", + }, + .probe = mcf_edma_probe, + .remove = mcf_edma_remove, +}; + +bool mcf_edma_filter_fn(struct dma_chan *chan, void *param) +{ + if (chan->device->dev->driver == &mcf_edma_driver.driver) { + struct fsl_edma_chan *mcf_chan = to_fsl_edma_chan(chan); + + return (mcf_chan->slave_id == (int)param); + } + + return false; +} +EXPORT_SYMBOL(mcf_edma_filter_fn); + +static int __init mcf_edma_init(void) +{ + return platform_driver_register(&mcf_edma_driver); +} +subsys_initcall(mcf_edma_init); + +static void __exit mcf_edma_exit(void) +{ + platform_driver_unregister(&mcf_edma_driver); +} +module_exit(mcf_edma_exit); + +MODULE_ALIAS("platform:mcf-edma"); +MODULE_DESCRIPTION("Freescale eDMA engine driver, ColdFire family"); +MODULE_LICENSE("GPL v2"); diff --git a/include/linux/platform_data/dma-mcf-edma.h b/include/linux/platform_data/dma-mcf-edma.h new file mode 100644 index 000000000000..d718ccfa3421 --- /dev/null +++ b/include/linux/platform_data/dma-mcf-edma.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Freescale eDMA platform data, ColdFire SoC's family. + * + * Copyright (c) 2017 Angelo Dureghello + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __LINUX_PLATFORM_DATA_MCF_EDMA_H__ +#define __LINUX_PLATFORM_DATA_MCF_EDMA_H__ + +struct dma_slave_map; + +bool mcf_edma_filter_fn(struct dma_chan *chan, void *param); + +#define MCF_EDMA_FILTER_PARAM(ch) ((void *)ch) + +/** + * struct mcf_edma_platform_data - platform specific data for eDMA engine + * + * @ver The eDMA module version. + * @dma_channels The number of eDMA channels. + */ +struct mcf_edma_platform_data { + int dma_channels; + const struct dma_slave_map *slave_map; + int slavecnt; +}; + +#endif /* __LINUX_PLATFORM_DATA_MCF_EDMA_H__ */ -- 2.18.0 From mboxrd@z Thu Jan 1 00:00:00 1970 From: angelo@sysam.it (Angelo Dureghello) Date: Sat, 11 Aug 2018 13:26:49 +0200 Subject: [PATCH v9 4/4] dmaengine: fsl-edma: add ColdFire mcf5441x edma support In-Reply-To: <20180811112649.20752-1-angelo@sysam.it> References: <20180811112649.20752-1-angelo@sysam.it> Message-ID: <20180811112649.20752-4-angelo@sysam.it> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org This patch adds support for ColdFire mcf5441x-family edma module. The ColdFire edma module is slightly different from fsl-edma, so a new driver is added. But most of the code is common between fsl-edma and mcf-edma so it has been collected into a separate common module fsl-edma-common (patch 1/3). Signed-off-by: Angelo Dureghello --- Changes for v8: - patch rewritten from scratch, this patch (3/3) has just been added. Changes for v9: - add compile test for Kconfig, - fix include guard. --- drivers/dma/Kconfig | 11 + drivers/dma/Makefile | 1 + drivers/dma/fsl-edma-common.c | 24 +- drivers/dma/mcf-edma.c | 315 +++++++++++++++++++++ include/linux/platform_data/dma-mcf-edma.h | 38 +++ 5 files changed, 385 insertions(+), 4 deletions(-) create mode 100644 drivers/dma/mcf-edma.c create mode 100644 include/linux/platform_data/dma-mcf-edma.h diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index ca1680afa20a..45ca5e556774 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -320,6 +320,17 @@ config LPC18XX_DMAMUX Enable support for DMA on NXP LPC18xx/43xx platforms with PL080 and multiplexed DMA request lines. +config MCF_EDMA + tristate "Freescale eDMA engine support, ColdFire mcf5441x SoCs" + depends on M5441x || COMPILE_TEST + select DMA_ENGINE + select DMA_VIRTUAL_CHANNELS + help + Support the Freescale ColdFire eDMA engine, 64-channel + implementation that performs complex data transfers with + minimal intervention from a host processor. + This module can be found on Freescale ColdFire mcf5441x SoCs. + config MMP_PDMA bool "MMP PDMA support" depends on ARCH_MMP || ARCH_PXA || COMPILE_TEST diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index 66022f59fca4..d97f317f4b34 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -32,6 +32,7 @@ obj-$(CONFIG_DW_DMAC_CORE) += dw/ obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o obj-$(CONFIG_FSL_DMA) += fsldma.o obj-$(CONFIG_FSL_EDMA) += fsl-edma.o fsl-edma-common.o +obj-$(CONFIG_MCF_EDMA) += mcf-edma.o fsl-edma-common.o obj-$(CONFIG_FSL_RAID) += fsl_raid.o obj-$(CONFIG_HSU_DMA) += hsu/ obj-$(CONFIG_IMG_MDC_DMA) += img-mdc-dma.o diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c index 227034de256e..8ba80f4b6f55 100644 --- a/drivers/dma/fsl-edma-common.c +++ b/drivers/dma/fsl-edma-common.c @@ -46,8 +46,16 @@ static void fsl_edma_enable_request(struct fsl_edma_chan *fsl_chan) struct edma_regs *regs = &fsl_chan->edma->regs; u32 ch = fsl_chan->vchan.chan.chan_id; - edma_writeb(fsl_chan->edma, EDMA_SEEI_SEEI(ch), regs->seei); - edma_writeb(fsl_chan->edma, ch, regs->serq); + if (fsl_chan->edma->version == v1) { + edma_writeb(fsl_chan->edma, EDMA_SEEI_SEEI(ch), regs->seei); + edma_writeb(fsl_chan->edma, ch, regs->serq); + } else { + /* ColdFire is big endian, and accesses natively + * big endian I/O peripherals + */ + iowrite8(EDMA_SEEI_SEEI(ch), regs->seei); + iowrite8(ch, regs->serq); + } } void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan) @@ -55,8 +63,16 @@ void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan) struct edma_regs *regs = &fsl_chan->edma->regs; u32 ch = fsl_chan->vchan.chan.chan_id; - edma_writeb(fsl_chan->edma, ch, regs->cerq); - edma_writeb(fsl_chan->edma, EDMA_CEEI_CEEI(ch), regs->ceei); + if (fsl_chan->edma->version == v1) { + edma_writeb(fsl_chan->edma, ch, regs->cerq); + edma_writeb(fsl_chan->edma, EDMA_CEEI_CEEI(ch), regs->ceei); + } else { + /* ColdFire is big endian, and accesses natively + * big endian I/O peripherals + */ + iowrite8(ch, regs->cerq); + iowrite8(EDMA_CEEI_CEEI(ch), regs->ceei); + } } EXPORT_SYMBOL_GPL(fsl_edma_disable_request); diff --git a/drivers/dma/mcf-edma.c b/drivers/dma/mcf-edma.c new file mode 100644 index 000000000000..d4b2fd871ff4 --- /dev/null +++ b/drivers/dma/mcf-edma.c @@ -0,0 +1,315 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright (c) 2013-2014 Freescale Semiconductor, Inc +// Copyright (c) 2017 Sysam, Angelo Dureghello + +#include +#include +#include +#include +#include + +#include "fsl-edma-common.h" + +#define EDMA_CHANNELS 64 +#define EDMA_MASK_CH(x) ((x) & GENMASK(5, 0)) + +static irqreturn_t mcf_edma_tx_handler(int irq, void *dev_id) +{ + struct fsl_edma_engine *mcf_edma = dev_id; + struct edma_regs *regs = &mcf_edma->regs; + unsigned int ch; + struct fsl_edma_chan *mcf_chan; + u64 intmap; + + intmap = ioread32(regs->inth); + intmap <<= 32; + intmap |= ioread32(regs->intl); + if (!intmap) + return IRQ_NONE; + + for (ch = 0; ch < mcf_edma->n_chans; ch++) { + if (intmap & BIT(ch)) { + iowrite8(EDMA_MASK_CH(ch), regs->cint); + + mcf_chan = &mcf_edma->chans[ch]; + + spin_lock(&mcf_chan->vchan.lock); + if (!mcf_chan->edesc->iscyclic) { + list_del(&mcf_chan->edesc->vdesc.node); + vchan_cookie_complete(&mcf_chan->edesc->vdesc); + mcf_chan->edesc = NULL; + mcf_chan->status = DMA_COMPLETE; + mcf_chan->idle = true; + } else { + vchan_cyclic_callback(&mcf_chan->edesc->vdesc); + } + + if (!mcf_chan->edesc) + fsl_edma_xfer_desc(mcf_chan); + + spin_unlock(&mcf_chan->vchan.lock); + } + } + + return IRQ_HANDLED; +} + +static irqreturn_t mcf_edma_err_handler(int irq, void *dev_id) +{ + struct fsl_edma_engine *mcf_edma = dev_id; + struct edma_regs *regs = &mcf_edma->regs; + unsigned int err, ch; + + err = ioread32(regs->errl); + if (!err) + return IRQ_NONE; + + for (ch = 0; ch < (EDMA_CHANNELS / 2); ch++) { + if (err & BIT(ch)) { + fsl_edma_disable_request(&mcf_edma->chans[ch]); + iowrite8(EDMA_CERR_CERR(ch), regs->cerr); + mcf_edma->chans[ch].status = DMA_ERROR; + mcf_edma->chans[ch].idle = true; + } + } + + err = ioread32(regs->errh); + if (!err) + return IRQ_NONE; + + for (ch = (EDMA_CHANNELS / 2); ch < EDMA_CHANNELS; ch++) { + if (err & (BIT(ch - (EDMA_CHANNELS / 2)))) { + fsl_edma_disable_request(&mcf_edma->chans[ch]); + iowrite8(EDMA_CERR_CERR(ch), regs->cerr); + mcf_edma->chans[ch].status = DMA_ERROR; + mcf_edma->chans[ch].idle = true; + } + } + + return IRQ_HANDLED; +} + +static int mcf_edma_irq_init(struct platform_device *pdev, + struct fsl_edma_engine *mcf_edma) +{ + int ret = 0, i; + struct resource *res; + + res = platform_get_resource_byname(pdev, + IORESOURCE_IRQ, "edma-tx-00-15"); + if (!res) + return -1; + + for (ret = 0, i = res->start; i <= res->end; ++i) + ret |= request_irq(i, mcf_edma_tx_handler, 0, "eDMA", mcf_edma); + if (ret) + return ret; + + res = platform_get_resource_byname(pdev, + IORESOURCE_IRQ, "edma-tx-16-55"); + if (!res) + return -1; + + for (ret = 0, i = res->start; i <= res->end; ++i) + ret |= request_irq(i, mcf_edma_tx_handler, 0, "eDMA", mcf_edma); + if (ret) + return ret; + + ret = platform_get_irq_byname(pdev, "edma-tx-56-63"); + if (ret != -ENXIO) { + ret = request_irq(ret, mcf_edma_tx_handler, + 0, "eDMA", mcf_edma); + if (ret) + return ret; + } + + ret = platform_get_irq_byname(pdev, "edma-err"); + if (ret != -ENXIO) { + ret = request_irq(ret, mcf_edma_err_handler, + 0, "eDMA", mcf_edma); + if (ret) + return ret; + } + + return 0; +} + +static void mcf_edma_irq_free(struct platform_device *pdev, + struct fsl_edma_engine *mcf_edma) +{ + int irq; + struct resource *res; + + res = platform_get_resource_byname(pdev, + IORESOURCE_IRQ, "edma-tx-00-15"); + if (res) { + for (irq = res->start; irq <= res->end; irq++) + free_irq(irq, mcf_edma); + } + + res = platform_get_resource_byname(pdev, + IORESOURCE_IRQ, "edma-tx-16-55"); + if (res) { + for (irq = res->start; irq <= res->end; irq++) + free_irq(irq, mcf_edma); + } + + irq = platform_get_irq_byname(pdev, "edma-tx-56-63"); + if (irq != -ENXIO) + free_irq(irq, mcf_edma); + + irq = platform_get_irq_byname(pdev, "edma-err"); + if (irq != -ENXIO) + free_irq(irq, mcf_edma); +} + +static int mcf_edma_probe(struct platform_device *pdev) +{ + struct mcf_edma_platform_data *pdata; + struct fsl_edma_engine *mcf_edma; + struct fsl_edma_chan *mcf_chan; + struct edma_regs *regs; + struct resource *res; + int ret, i, len, chans; + + pdata = dev_get_platdata(&pdev->dev); + if (!pdata) + return PTR_ERR(pdata); + + chans = pdata->dma_channels; + len = sizeof(*mcf_edma) + sizeof(*mcf_chan) * chans; + mcf_edma = devm_kzalloc(&pdev->dev, len, GFP_KERNEL); + if (!mcf_edma) + return -ENOMEM; + + mcf_edma->n_chans = chans; + + /* Set up version for ColdFire edma */ + mcf_edma->version = v2; + mcf_edma->big_endian = 1; + + if (!mcf_edma->n_chans) { + dev_info(&pdev->dev, "setting default channel number to 64"); + mcf_edma->n_chans = 64; + } + + mutex_init(&mcf_edma->fsl_edma_mutex); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + + mcf_edma->membase = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(mcf_edma->membase)) + return PTR_ERR(mcf_edma->membase); + + fsl_edma_setup_regs(mcf_edma); + regs = &mcf_edma->regs; + + INIT_LIST_HEAD(&mcf_edma->dma_dev.channels); + for (i = 0; i < mcf_edma->n_chans; i++) { + struct fsl_edma_chan *mcf_chan = &mcf_edma->chans[i]; + + mcf_chan->edma = mcf_edma; + mcf_chan->slave_id = i; + mcf_chan->idle = true; + mcf_chan->vchan.desc_free = fsl_edma_free_desc; + vchan_init(&mcf_chan->vchan, &mcf_edma->dma_dev); + iowrite32(0x0, ®s->tcd[i].csr); + } + + iowrite32(~0, regs->inth); + iowrite32(~0, regs->intl); + + ret = mcf_edma_irq_init(pdev, mcf_edma); + if (ret) + return ret; + + dma_cap_set(DMA_PRIVATE, mcf_edma->dma_dev.cap_mask); + dma_cap_set(DMA_SLAVE, mcf_edma->dma_dev.cap_mask); + dma_cap_set(DMA_CYCLIC, mcf_edma->dma_dev.cap_mask); + + mcf_edma->dma_dev.dev = &pdev->dev; + mcf_edma->dma_dev.device_alloc_chan_resources = + fsl_edma_alloc_chan_resources; + mcf_edma->dma_dev.device_free_chan_resources = + fsl_edma_free_chan_resources; + mcf_edma->dma_dev.device_config = fsl_edma_slave_config; + mcf_edma->dma_dev.device_prep_dma_cyclic = + fsl_edma_prep_dma_cyclic; + mcf_edma->dma_dev.device_prep_slave_sg = fsl_edma_prep_slave_sg; + mcf_edma->dma_dev.device_tx_status = fsl_edma_tx_status; + mcf_edma->dma_dev.device_pause = fsl_edma_pause; + mcf_edma->dma_dev.device_resume = fsl_edma_resume; + mcf_edma->dma_dev.device_terminate_all = fsl_edma_terminate_all; + mcf_edma->dma_dev.device_issue_pending = fsl_edma_issue_pending; + + mcf_edma->dma_dev.src_addr_widths = FSL_EDMA_BUSWIDTHS; + mcf_edma->dma_dev.dst_addr_widths = FSL_EDMA_BUSWIDTHS; + mcf_edma->dma_dev.directions = + BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); + + mcf_edma->dma_dev.filter.fn = mcf_edma_filter_fn; + mcf_edma->dma_dev.filter.map = pdata->slave_map; + mcf_edma->dma_dev.filter.mapcnt = pdata->slavecnt; + + platform_set_drvdata(pdev, mcf_edma); + + ret = dma_async_device_register(&mcf_edma->dma_dev); + if (ret) { + dev_err(&pdev->dev, + "Can't register Freescale eDMA engine. (%d)\n", ret); + return ret; + } + + /* Enable round robin arbitration */ + iowrite32(EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr); + + return 0; +} + +static int mcf_edma_remove(struct platform_device *pdev) +{ + struct fsl_edma_engine *mcf_edma = platform_get_drvdata(pdev); + + mcf_edma_irq_free(pdev, mcf_edma); + fsl_edma_cleanup_vchan(&mcf_edma->dma_dev); + dma_async_device_unregister(&mcf_edma->dma_dev); + + return 0; +} + +static struct platform_driver mcf_edma_driver = { + .driver = { + .name = "mcf-edma", + }, + .probe = mcf_edma_probe, + .remove = mcf_edma_remove, +}; + +bool mcf_edma_filter_fn(struct dma_chan *chan, void *param) +{ + if (chan->device->dev->driver == &mcf_edma_driver.driver) { + struct fsl_edma_chan *mcf_chan = to_fsl_edma_chan(chan); + + return (mcf_chan->slave_id == (int)param); + } + + return false; +} +EXPORT_SYMBOL(mcf_edma_filter_fn); + +static int __init mcf_edma_init(void) +{ + return platform_driver_register(&mcf_edma_driver); +} +subsys_initcall(mcf_edma_init); + +static void __exit mcf_edma_exit(void) +{ + platform_driver_unregister(&mcf_edma_driver); +} +module_exit(mcf_edma_exit); + +MODULE_ALIAS("platform:mcf-edma"); +MODULE_DESCRIPTION("Freescale eDMA engine driver, ColdFire family"); +MODULE_LICENSE("GPL v2"); diff --git a/include/linux/platform_data/dma-mcf-edma.h b/include/linux/platform_data/dma-mcf-edma.h new file mode 100644 index 000000000000..d718ccfa3421 --- /dev/null +++ b/include/linux/platform_data/dma-mcf-edma.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Freescale eDMA platform data, ColdFire SoC's family. + * + * Copyright (c) 2017 Angelo Dureghello + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __LINUX_PLATFORM_DATA_MCF_EDMA_H__ +#define __LINUX_PLATFORM_DATA_MCF_EDMA_H__ + +struct dma_slave_map; + +bool mcf_edma_filter_fn(struct dma_chan *chan, void *param); + +#define MCF_EDMA_FILTER_PARAM(ch) ((void *)ch) + +/** + * struct mcf_edma_platform_data - platform specific data for eDMA engine + * + * @ver The eDMA module version. + * @dma_channels The number of eDMA channels. + */ +struct mcf_edma_platform_data { + int dma_channels; + const struct dma_slave_map *slave_map; + int slavecnt; +}; + +#endif /* __LINUX_PLATFORM_DATA_MCF_EDMA_H__ */ -- 2.18.0