From: Huang Rui <ray.huang-5C7GfCeVMHo@public.gmane.org>
To: Evan Quan <evan.quan-5C7GfCeVMHo@public.gmane.org>
Cc: alexander.deucher-5C7GfCeVMHo@public.gmane.org,
feifei.xu-5C7GfCeVMHo@public.gmane.org,
amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Subject: Re: [PATCH] drm/amd/powerplay: set correct base for THM/NBIF/MP1 IP
Date: Fri, 17 Aug 2018 12:11:54 +0800 [thread overview]
Message-ID: <20180817033741.GD32351@hr-amur2> (raw)
In-Reply-To: <20180817023632.29104-1-evan.quan-5C7GfCeVMHo@public.gmane.org>
On Fri, Aug 17, 2018 at 10:36:32AM +0800, Evan Quan wrote:
> Set correct address base for vega20.
>
> Change-Id: I7435980e2ca156ee2b443a97899d40aaba4876cb
> Signed-off-by: Evan Quan <evan.quan@amd.com>
The patch subject prefix should be "drm/amdgpu:"
With that fixed, patch is
Reviewed-by: Huang Rui <ray.huang@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c b/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
> index 52778de93ab0..2d4473557b0d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
> @@ -38,6 +38,7 @@ int vega20_reg_base_init(struct amdgpu_device *adev)
> adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));
> adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
> adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));
> + adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));
> adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i]));
> adev->reg_offset[VCE_HWIP][i] = (uint32_t *)(&(VCE_BASE.instance[i]));
> adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));
> @@ -46,6 +47,8 @@ int vega20_reg_base_init(struct amdgpu_device *adev)
> adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(SDMA0_BASE.instance[i]));
> adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(SDMA1_BASE.instance[i]));
> adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));
> + adev->reg_offset[NBIF_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
> + adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));
> }
> return 0;
> }
> --
> 2.18.0
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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prev parent reply other threads:[~2018-08-17 4:11 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-08-17 2:36 [PATCH] drm/amd/powerplay: set correct base for THM/NBIF/MP1 IP Evan Quan
[not found] ` <20180817023632.29104-1-evan.quan-5C7GfCeVMHo@public.gmane.org>
2018-08-17 2:53 ` Deucher, Alexander
2018-08-17 4:11 ` Huang Rui [this message]
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