From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rob Herring Subject: Re: [PATCH v2 4/4] dt-bindigs: msm: Update documentation of qcom,llcc Date: Mon, 20 Aug 2018 14:53:41 -0500 Message-ID: <20180820195341.GA3358@bogus> References: <1534550915-18230-1-git-send-email-vnkgutta@codeaurora.org> <1534550915-18230-5-git-send-email-vnkgutta@codeaurora.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: <1534550915-18230-5-git-send-email-vnkgutta@codeaurora.org> Sender: linux-kernel-owner@vger.kernel.org To: Venkata Narendra Kumar Gutta Cc: mchehab@kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, Andy Gross , David Brown , linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, tsoni@codeaurora.org, ckadabi@codeaurora.org, rishabhb@codeaurora.org, bp@alien8.de, evgreen@chromium.org List-Id: linux-arm-msm@vger.kernel.org On Fri, Aug 17, 2018 at 05:08:35PM -0700, Venkata Narendra Kumar Gutta wrote: > Add reg-names and interrupts for LLCC documentation and the usage > examples. llcc broadcast base is added in addition to llcc base, > which is used for llcc broadcast writes. Typo in the subject. This binding just landed recently and it's already being updated? Sigh. Bindings should be complete from the start. Technically, you can't add new required properties. > > Signed-off-by: Venkata Narendra Kumar Gutta > --- > Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt | 15 ++++++++++++++- > 1 file changed, 14 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt > index 5e85749..b4b1c86 100644 > --- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt > +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt > @@ -18,9 +18,22 @@ Properties: > Value Type: > Definition: Start address and the the size of the register region. > > +- reg-names: > + Usage: required > + Value Type: > + Definition: Register region names. Must be "llcc_base", "llcc_bcast_base". reg needs to be updated that there are 2 entries. > + > +- interrupts: > + Usage: required > + Definition: The interrupt is associated with the llcc edac device. > + It's used for llcc cache single and double bit error detection > + and reporting. > + > Example: > > cache-controller@1100000 { > compatible = "qcom,sdm845-llcc"; > - reg = <0x1100000 0x250000>; > + reg = <0x1100000 0x200000>, <0x1300000 0x50000> ; > + reg-names = "llcc_base", "llcc_bcast_base"; > + interrupts = ; > }; > -- > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, > a Linux Foundation Collaborative Project > From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [v2,4/4] dt-bindigs: msm: Update documentation of qcom,llcc From: Rob Herring Message-Id: <20180820195341.GA3358@bogus> Date: Mon, 20 Aug 2018 14:53:41 -0500 To: Venkata Narendra Kumar Gutta Cc: mchehab@kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, Andy Gross , David Brown , linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, tsoni@codeaurora.org, ckadabi@codeaurora.org, rishabhb@codeaurora.org, bp@alien8.de, evgreen@chromium.org List-ID: T24gRnJpLCBBdWcgMTcsIDIwMTggYXQgMDU6MDg6MzVQTSAtMDcwMCwgVmVua2F0YSBOYXJlbmRy YSBLdW1hciBHdXR0YSB3cm90ZToKPiBBZGQgcmVnLW5hbWVzIGFuZCBpbnRlcnJ1cHRzIGZvciBM TENDIGRvY3VtZW50YXRpb24gYW5kIHRoZSB1c2FnZQo+IGV4YW1wbGVzLiBsbGNjIGJyb2FkY2Fz dCBiYXNlIGlzIGFkZGVkIGluIGFkZGl0aW9uIHRvIGxsY2MgYmFzZSwKPiB3aGljaCBpcyB1c2Vk IGZvciBsbGNjIGJyb2FkY2FzdCB3cml0ZXMuCgpUeXBvIGluIHRoZSBzdWJqZWN0LgoKVGhpcyBi aW5kaW5nIGp1c3QgbGFuZGVkIHJlY2VudGx5IGFuZCBpdCdzIGFscmVhZHkgYmVpbmcgdXBkYXRl ZD8gU2lnaC4KQmluZGluZ3Mgc2hvdWxkIGJlIGNvbXBsZXRlIGZyb20gdGhlIHN0YXJ0LiBUZWNo bmljYWxseSwgeW91IGNhbid0IGFkZCAKbmV3IHJlcXVpcmVkIHByb3BlcnRpZXMuCgo+IAo+IFNp Z25lZC1vZmYtYnk6IFZlbmthdGEgTmFyZW5kcmEgS3VtYXIgR3V0dGEgPHZua2d1dHRhQGNvZGVh dXJvcmEub3JnPgo+IC0tLQo+ICBEb2N1bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGluZ3MvYXJt L21zbS9xY29tLGxsY2MudHh0IHwgMTUgKysrKysrKysrKysrKystCj4gIDEgZmlsZSBjaGFuZ2Vk LCAxNCBpbnNlcnRpb25zKCspLCAxIGRlbGV0aW9uKC0pCj4gCj4gZGlmZiAtLWdpdCBhL0RvY3Vt ZW50YXRpb24vZGV2aWNldHJlZS9iaW5kaW5ncy9hcm0vbXNtL3Fjb20sbGxjYy50eHQgYi9Eb2N1 bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGluZ3MvYXJtL21zbS9xY29tLGxsY2MudHh0Cj4gaW5k ZXggNWU4NTc0OS4uYjRiMWM4NiAxMDA2NDQKPiAtLS0gYS9Eb2N1bWVudGF0aW9uL2RldmljZXRy ZWUvYmluZGluZ3MvYXJtL21zbS9xY29tLGxsY2MudHh0Cj4gKysrIGIvRG9jdW1lbnRhdGlvbi9k ZXZpY2V0cmVlL2JpbmRpbmdzL2FybS9tc20vcWNvbSxsbGNjLnR4dAo+IEBAIC0xOCw5ICsxOCwy MiBAQCBQcm9wZXJ0aWVzOgo+ICAJVmFsdWUgVHlwZTogPHByb3AtZW5jb2RlZC1hcnJheT4KPiAg CURlZmluaXRpb246IFN0YXJ0IGFkZHJlc3MgYW5kIHRoZSB0aGUgc2l6ZSBvZiB0aGUgcmVnaXN0 ZXIgcmVnaW9uLgo+ICAKPiArLSByZWctbmFtZXM6Cj4gKyAgICAgICAgVXNhZ2U6IHJlcXVpcmVk Cj4gKyAgICAgICAgVmFsdWUgVHlwZTogPHN0cmluZ2xpc3Q+Cj4gKyAgICAgICAgRGVmaW5pdGlv bjogUmVnaXN0ZXIgcmVnaW9uIG5hbWVzLiBNdXN0IGJlICJsbGNjX2Jhc2UiLCAibGxjY19iY2Fz dF9iYXNlIi4KCnJlZyBuZWVkcyB0byBiZSB1cGRhdGVkIHRoYXQgdGhlcmUgYXJlIDIgZW50cmll cy4KCj4gKwo+ICstIGludGVycnVwdHM6Cj4gKwlVc2FnZTogcmVxdWlyZWQKPiArCURlZmluaXRp b246IFRoZSBpbnRlcnJ1cHQgaXMgYXNzb2NpYXRlZCB3aXRoIHRoZSBsbGNjIGVkYWMgZGV2aWNl Lgo+ICsJCQlJdCdzIHVzZWQgZm9yIGxsY2MgY2FjaGUgc2luZ2xlIGFuZCBkb3VibGUgYml0IGVy cm9yIGRldGVjdGlvbgo+ICsJCQlhbmQgcmVwb3J0aW5nLgo+ICsKPiAgRXhhbXBsZToKPiAgCj4g IAljYWNoZS1jb250cm9sbGVyQDExMDAwMDAgewo+ICAJCWNvbXBhdGlibGUgPSAicWNvbSxzZG04 NDUtbGxjYyI7Cj4gLQkJcmVnID0gPDB4MTEwMDAwMCAweDI1MDAwMD47Cj4gKwkJcmVnID0gPDB4 MTEwMDAwMCAweDIwMDAwMD4sIDwweDEzMDAwMDAgMHg1MDAwMD4gOwo+ICsJCXJlZy1uYW1lcyA9 ICJsbGNjX2Jhc2UiLCAibGxjY19iY2FzdF9iYXNlIjsKPiArCQlpbnRlcnJ1cHRzID0gPEdJQ19T UEkgNTgyIElSUV9UWVBFX0xFVkVMX0hJR0g+Owo+ICAJfTsKPiAtLSAKPiBUaGUgUXVhbGNvbW0g SW5ub3ZhdGlvbiBDZW50ZXIsIEluYy4gaXMgYSBtZW1iZXIgb2YgdGhlIENvZGUgQXVyb3JhIEZv cnVtLAo+IGEgTGludXggRm91bmRhdGlvbiBDb2xsYWJvcmF0aXZlIFByb2plY3QKPgo=