From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: Manasi Navare <manasi.d.navare@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915/dsc: Fix PPS register definition macros for 2nd VDSC engine
Date: Thu, 23 Aug 2018 23:07:27 -0700 [thread overview]
Message-ID: <20180824060727.GO2190@intel.com> (raw)
In-Reply-To: <20180824014807.14681-1-manasi.d.navare@intel.com>
On Thu, Aug 23, 2018 at 06:48:07PM -0700, Manasi Navare wrote:
> This patch fixes the PPS4 and PPS register definition macros that were
> resulting into an incorect MMIO address.
>
> Fixes: 2efbb2f099fb ("i915/dp/dsc: Add DSC PPS register definitions")
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
(also checked others around to see if there was similar issues,
but the rest seems right)
> ---
> drivers/gpu/drm/i915/i915_reg.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 41ab5b56ee52..64d7e675f7e8 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -10488,7 +10488,7 @@ enum skl_power_gate {
> _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB, \
> _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC)
> #define ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB, \
> _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC)
> #define DSC_INITIAL_DEC_DELAY(dec_delay) ((dec_delay) << 16)
> #define DSC_INITIAL_XMIT_DELAY(xmit_delay) ((xmit_delay) << 0)
> @@ -10503,7 +10503,7 @@ enum skl_power_gate {
> _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB, \
> _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC)
> #define ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB, \
> _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC)
> #define DSC_SCALE_DEC_INT(scale_dec) ((scale_dec) << 16)
> #define DSC_SCALE_INC_INT(scale_inc) ((scale_inc) << 0)
> --
> 2.18.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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next prev parent reply other threads:[~2018-08-24 6:07 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-08-24 1:48 [PATCH] drm/i915/dsc: Fix PPS register definition macros for 2nd VDSC engine Manasi Navare
2018-08-24 2:09 ` ✓ Fi.CI.BAT: success for " Patchwork
2018-08-24 2:59 ` ✓ Fi.CI.IGT: " Patchwork
2018-08-24 6:07 ` Rodrigo Vivi [this message]
2018-08-24 17:14 ` [PATCH] " Srivatsa, Anusha
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