From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jordan Crouse Subject: [PATCH 1/9] drm/msm/a6xx: rnndb updates for a6xx Date: Mon, 27 Aug 2018 09:11:04 -0600 Message-ID: <20180827151112.25211-2-jcrouse@codeaurora.org> References: <20180827151112.25211-1-jcrouse@codeaurora.org> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <20180827151112.25211-1-jcrouse-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: freedreno-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "Freedreno" To: freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org, georgi.djakov-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org Cc: nm-l0cyMroinI0@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-pm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, sboyd-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, linux-arm-msm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org, bjorn.andersson-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org, vireshk-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org List-Id: linux-arm-msm@vger.kernel.org VXBkYXRlIHRoZSByZWdpc3RlciBkZWZpbml0aW9ucyBmb3IgYTZ4eCBmcm9tIHRoZSBybm5kYiBk YXRhYmFzZS4KQ2hhbmdlcyBpbmNsdWRlIG5ldyBlbnVtcyBmb3IgdXBjb21pbmcgZGV2Y29yZWR1 bXAgc3VwcG9ydCwgbW92aW5nCnRoZSBQREMgYW5kIEdDQ19HWCByZWdpc3RlciBkZWZpbml0aW9u cyB0byB0aGVpciBvd24gZG9tYWluIGFuZAp2YXJpb3VzIG90aGVyIHJlZ2lzdGVyIHVwZGF0ZXMg YW5kIGFkZGl0aW9ucy4KClNpZ25lZC1vZmYtYnk6IEpvcmRhbiBDcm91c2UgPGpjcm91c2VAY29k ZWF1cm9yYS5vcmc+Ci0tLQogZHJpdmVycy9ncHUvZHJtL21zbS9hZHJlbm8vYTZ4eC54bWwuaCAg ICAgfCA2NDIgKysrKysrKysrKysrKystLS0tLS0tLQogZHJpdmVycy9ncHUvZHJtL21zbS9hZHJl bm8vYTZ4eF9nbXUueG1sLmggfCAgMjYgKy0KIDIgZmlsZXMgY2hhbmdlZCwgNDE2IGluc2VydGlv bnMoKyksIDI1MiBkZWxldGlvbnMoLSkKCmRpZmYgLS1naXQgYS9kcml2ZXJzL2dwdS9kcm0vbXNt L2FkcmVuby9hNnh4LnhtbC5oIGIvZHJpdmVycy9ncHUvZHJtL21zbS9hZHJlbm8vYTZ4eC54bWwu aAppbmRleCA4N2VhYjUxZjcwMDAuLjdhY2M1N2IyYzFiZSAxMDA2NDQKLS0tIGEvZHJpdmVycy9n cHUvZHJtL21zbS9hZHJlbm8vYTZ4eC54bWwuaAorKysgYi9kcml2ZXJzL2dwdS9kcm0vbXNtL2Fk cmVuby9hNnh4LnhtbC5oCkBAIC04LDE3ICs4LDE3IEBAIFRoaXMgZmlsZSB3YXMgZ2VuZXJhdGVk IGJ5IHRoZSBydWxlcy1uZy1uZyBoZWFkZXJnZW4gdG9vbCBpbiB0aGlzIGdpdCByZXBvc2l0b3J5 CiBnaXQgY2xvbmUgaHR0cHM6Ly9naXRodWIuY29tL2ZyZWVkcmVuby9lbnZ5dG9vbHMuZ2l0CiAK IFRoZSBydWxlcy1uZy1uZyBzb3VyY2UgZmlsZXMgdGhpcyBoZWFkZXIgd2FzIGdlbmVyYXRlZCBm cm9tIGFyZToKLS0gL2hvbWUvcm9iY2xhcmsvc3JjL2Vudnl0b29scy9ybm5kYi9hZHJlbm8ueG1s ICAgICAgICAgICAgICAgKCAgICA1MDEgYnl0ZXMsIGZyb20gMjAxOC0wNy0wMyAxOTozNzoxMykK LS0gL2hvbWUvcm9iY2xhcmsvc3JjL2Vudnl0b29scy9ybm5kYi9mcmVlZHJlbm9fY29weXJpZ2h0 LnhtbCAgKCAgIDE1NzIgYnl0ZXMsIGZyb20gMjAxOC0wNy0wMyAxOTozNzoxMykKLS0gL2hvbWUv cm9iY2xhcmsvc3JjL2Vudnl0b29scy9ybm5kYi9hZHJlbm8vYTJ4eC54bWwgICAgICAgICAgKCAg MzY4MDUgYnl0ZXMsIGZyb20gMjAxOC0wNy0wMyAxOTozNzoxMykKLS0gL2hvbWUvcm9iY2xhcmsv c3JjL2Vudnl0b29scy9ybm5kYi9hZHJlbm8vYWRyZW5vX2NvbW1vbi54bWwgKCAgMTM2MzQgYnl0 ZXMsIGZyb20gMjAxOC0wNy0wMyAxOTozNzoxMykKLS0gL2hvbWUvcm9iY2xhcmsvc3JjL2Vudnl0 b29scy9ybm5kYi9hZHJlbm8vYWRyZW5vX3BtNC54bWwgICAgKCAgNDIzOTMgYnl0ZXMsIGZyb20g MjAxOC0wOC0wNiAxODo0NTo0NSkKLS0gL2hvbWUvcm9iY2xhcmsvc3JjL2Vudnl0b29scy9ybm5k Yi9hZHJlbm8vYTN4eC54bWwgICAgICAgICAgKCAgODM4NDAgYnl0ZXMsIGZyb20gMjAxOC0wNy0w MyAxOTozNzoxMykKLS0gL2hvbWUvcm9iY2xhcmsvc3JjL2Vudnl0b29scy9ybm5kYi9hZHJlbm8v YTR4eC54bWwgICAgICAgICAgKCAxMTIwODYgYnl0ZXMsIGZyb20gMjAxOC0wNy0wMyAxOTozNzox MykKLS0gL2hvbWUvcm9iY2xhcmsvc3JjL2Vudnl0b29scy9ybm5kYi9hZHJlbm8vYTV4eC54bWwg ICAgICAgICAgKCAxNDcyNDAgYnl0ZXMsIGZyb20gMjAxOC0wOC0wNiAxODo0NTo0NSkKLS0gL2hv bWUvcm9iY2xhcmsvc3JjL2Vudnl0b29scy9ybm5kYi9hZHJlbm8vYTZ4eC54bWwgICAgICAgICAg KCAxMDE2MjcgYnl0ZXMsIGZyb20gMjAxOC0wOC0wNiAxODo0NTo0NSkKLS0gL2hvbWUvcm9iY2xh cmsvc3JjL2Vudnl0b29scy9ybm5kYi9hZHJlbm8vYTZ4eF9nbXUueG1sICAgICAgKCAgMTA0MzEg Ynl0ZXMsIGZyb20gMjAxOC0wNy0wMyAxOTozNzoxMykKLS0gL2hvbWUvcm9iY2xhcmsvc3JjL2Vu dnl0b29scy9ybm5kYi9hZHJlbm8vb2NtZW0ueG1sICAgICAgICAgKCAgIDE3NzMgYnl0ZXMsIGZy b20gMjAxOC0wNy0wMyAxOTozNzoxMykKKy0gLi9hZHJlbm8ueG1sICAgICAgICAgICAgICAgKCAg ICA1MDEgYnl0ZXMsIGZyb20gMjAxOC0wNS0yMyAxNjo1MTo1NykKKy0gLi9mcmVlZHJlbm9fY29w eXJpZ2h0LnhtbCAgKCAgIDE1NzIgYnl0ZXMsIGZyb20gMjAxNi0xMC0yNCAyMToxMjoyNykKKy0g Li9hZHJlbm8vYTJ4eC54bWwgICAgICAgICAgKCAgMzY4MDUgYnl0ZXMsIGZyb20gMjAxOC0wNS0y MyAxNjo1MTo1NykKKy0gLi9hZHJlbm8vYWRyZW5vX2NvbW1vbi54bWwgKCAgMTM2MzQgYnl0ZXMs IGZyb20gMjAxOC0wNS0yMyAxNjo1MTo1NykKKy0gLi9hZHJlbm8vYWRyZW5vX3BtNC54bWwgICAg KCAgNDIzOTMgYnl0ZXMsIGZyb20gMjAxOC0wOC0xNiAxNjo1NjoxNCkKKy0gLi9hZHJlbm8vYTN4 eC54bWwgICAgICAgICAgKCAgODM4NDAgYnl0ZXMsIGZyb20gMjAxNy0xMi0wNSAxODoyMDoyNykK Ky0gLi9hZHJlbm8vYTR4eC54bWwgICAgICAgICAgKCAxMTIwODYgYnl0ZXMsIGZyb20gMjAxOC0w NS0yMyAxNjo1MTo1NykKKy0gLi9hZHJlbm8vYTV4eC54bWwgICAgICAgICAgKCAxNDcyNDAgYnl0 ZXMsIGZyb20gMjAxOC0wOC0xNiAxNjo1NjoxNCkKKy0gLi9hZHJlbm8vYTZ4eC54bWwgICAgICAg ICAgKCAxMDc1MjEgYnl0ZXMsIGZyb20gMjAxOC0wOC0xNiAxNzo0NDo1MCkKKy0gLi9hZHJlbm8v YTZ4eF9nbXUueG1sICAgICAgKCAgMTA0MzEgYnl0ZXMsIGZyb20gMjAxOC0wOC0xNiAxNzo0NDoy NikKKy0gLi9hZHJlbm8vb2NtZW0ueG1sICAgICAgICAgKCAgIDE3NzMgYnl0ZXMsIGZyb20gMjAx Ni0xMC0yNCAyMToxMjoyNykKIAogQ29weXJpZ2h0IChDKSAyMDEzLTIwMTggYnkgdGhlIGZvbGxv d2luZyBhdXRob3JzOgogLSBSb2IgQ2xhcmsgPHJvYmRjbGFya0BnbWFpbC5jb20+IChyb2JjbGFy aykKQEAgLTI3Miw2ICsyNzIsOTggQEAgZW51bSBhNnh4X2NwX3BlcmZjb3VudGVyX3NlbGVjdCB7 CiAJUEVSRl9DUF9BTFdBWVNfQ09VTlQgPSAwLAogfTsKIAorZW51bSBhNnh4X3NoYWRlcl9pZCB7 CisJQTZYWF9UUDBfVE1PX0RBVEEgPSA5LAorCUE2WFhfVFAwX1NNT19EQVRBID0gMTAsCisJQTZY WF9UUDBfTUlQTUFQX0JBU0VfREFUQSA9IDExLAorCUE2WFhfVFAxX1RNT19EQVRBID0gMjUsCisJ QTZYWF9UUDFfU01PX0RBVEEgPSAyNiwKKwlBNlhYX1RQMV9NSVBNQVBfQkFTRV9EQVRBID0gMjcs CisJQTZYWF9TUF9JTlNUX0RBVEEgPSA0MSwKKwlBNlhYX1NQX0xCXzBfREFUQSA9IDQyLAorCUE2 WFhfU1BfTEJfMV9EQVRBID0gNDMsCisJQTZYWF9TUF9MQl8yX0RBVEEgPSA0NCwKKwlBNlhYX1NQ X0xCXzNfREFUQSA9IDQ1LAorCUE2WFhfU1BfTEJfNF9EQVRBID0gNDYsCisJQTZYWF9TUF9MQl81 X0RBVEEgPSA0NywKKwlBNlhYX1NQX0NCX0JJTkRMRVNTX0RBVEEgPSA0OCwKKwlBNlhYX1NQX0NC X0xFR0FDWV9EQVRBID0gNDksCisJQTZYWF9TUF9VQVZfREFUQSA9IDUwLAorCUE2WFhfU1BfSU5T VF9UQUcgPSA1MSwKKwlBNlhYX1NQX0NCX0JJTkRMRVNTX1RBRyA9IDUyLAorCUE2WFhfU1BfVE1P X1VNT19UQUcgPSA1MywKKwlBNlhYX1NQX1NNT19UQUcgPSA1NCwKKwlBNlhYX1NQX1NUQVRFX0RB VEEgPSA1NSwKKwlBNlhYX0hMU1FfQ0hVTktfQ1ZTX1JBTSA9IDczLAorCUE2WFhfSExTUV9DSFVO S19DUFNfUkFNID0gNzQsCisJQTZYWF9ITFNRX0NIVU5LX0NWU19SQU1fVEFHID0gNzUsCisJQTZY WF9ITFNRX0NIVU5LX0NQU19SQU1fVEFHID0gNzYsCisJQTZYWF9ITFNRX0lDQl9DVlNfQ0JfQkFT RV9UQUcgPSA3NywKKwlBNlhYX0hMU1FfSUNCX0NQU19DQl9CQVNFX1RBRyA9IDc4LAorCUE2WFhf SExTUV9DVlNfTUlTQ19SQU0gPSA4MCwKKwlBNlhYX0hMU1FfQ1BTX01JU0NfUkFNID0gODEsCisJ QTZYWF9ITFNRX0lOU1RfUkFNID0gODIsCisJQTZYWF9ITFNRX0dGWF9DVlNfQ09OU1RfUkFNID0g ODMsCisJQTZYWF9ITFNRX0dGWF9DUFNfQ09OU1RfUkFNID0gODQsCisJQTZYWF9ITFNRX0NWU19N SVNDX1JBTV9UQUcgPSA4NSwKKwlBNlhYX0hMU1FfQ1BTX01JU0NfUkFNX1RBRyA9IDg2LAorCUE2 WFhfSExTUV9JTlNUX1JBTV9UQUcgPSA4NywKKwlBNlhYX0hMU1FfR0ZYX0NWU19DT05TVF9SQU1f VEFHID0gODgsCisJQTZYWF9ITFNRX0dGWF9DUFNfQ09OU1RfUkFNX1RBRyA9IDg5LAorCUE2WFhf SExTUV9QV1JfUkVTVF9SQU0gPSA5MCwKKwlBNlhYX0hMU1FfUFdSX1JFU1RfVEFHID0gOTEsCisJ QTZYWF9ITFNRX0RBVEFQQVRIX01FVEEgPSA5NiwKKwlBNlhYX0hMU1FfRlJPTlRFTkRfTUVUQSA9 IDk3LAorCUE2WFhfSExTUV9JTkRJUkVDVF9NRVRBID0gOTgsCisJQTZYWF9ITFNRX0JBQ0tFTkRf TUVUQSA9IDk5LAorfTsKKworZW51bSBhNnh4X2RlYnVnYnVzX2lkIHsKKwlBNlhYX0RCR0JVU19D UCA9IDEsCisJQTZYWF9EQkdCVVNfUkJCTSA9IDIsCisJQTZYWF9EQkdCVVNfVkJJRiA9IDMsCisJ QTZYWF9EQkdCVVNfSExTUSA9IDQsCisJQTZYWF9EQkdCVVNfVUNIRSA9IDUsCisJQTZYWF9EQkdC VVNfRFBNID0gNiwKKwlBNlhYX0RCR0JVU19URVNTID0gNywKKwlBNlhYX0RCR0JVU19QQyA9IDgs CisJQTZYWF9EQkdCVVNfVkZEUCA9IDksCisJQTZYWF9EQkdCVVNfVlBDID0gMTAsCisJQTZYWF9E QkdCVVNfVFNFID0gMTEsCisJQTZYWF9EQkdCVVNfUkFTID0gMTIsCisJQTZYWF9EQkdCVVNfVlND ID0gMTMsCisJQTZYWF9EQkdCVVNfQ09NID0gMTQsCisJQTZYWF9EQkdCVVNfTFJaID0gMTYsCisJ QTZYWF9EQkdCVVNfQTJEID0gMTcsCisJQTZYWF9EQkdCVVNfQ0NVRkNIRSA9IDE4LAorCUE2WFhf REJHQlVTX0dNVV9DWCA9IDE5LAorCUE2WFhfREJHQlVTX1JCUCA9IDIwLAorCUE2WFhfREJHQlVT X0RDUyA9IDIxLAorCUE2WFhfREJHQlVTX0RCR0MgPSAyMiwKKwlBNlhYX0RCR0JVU19DWCA9IDIz LAorCUE2WFhfREJHQlVTX0dNVV9HWCA9IDI0LAorCUE2WFhfREJHQlVTX1RQRkNIRSA9IDI1LAor CUE2WFhfREJHQlVTX0dCSUZfR1ggPSAyNiwKKwlBNlhYX0RCR0JVU19HUEMgPSAyOSwKKwlBNlhY X0RCR0JVU19MQVJDID0gMzAsCisJQTZYWF9EQkdCVVNfSExTUV9TUFRQID0gMzEsCisJQTZYWF9E QkdCVVNfUkJfMCA9IDMyLAorCUE2WFhfREJHQlVTX1JCXzEgPSAzMywKKwlBNlhYX0RCR0JVU19V Q0hFX1dSQVBQRVIgPSAzNiwKKwlBNlhYX0RCR0JVU19DQ1VfMCA9IDQwLAorCUE2WFhfREJHQlVT X0NDVV8xID0gNDEsCisJQTZYWF9EQkdCVVNfVkZEXzAgPSA1NiwKKwlBNlhYX0RCR0JVU19WRkRf MSA9IDU3LAorCUE2WFhfREJHQlVTX1ZGRF8yID0gNTgsCisJQTZYWF9EQkdCVVNfVkZEXzMgPSA1 OSwKKwlBNlhYX0RCR0JVU19TUF8wID0gNjQsCisJQTZYWF9EQkdCVVNfU1BfMSA9IDY1LAorCUE2 WFhfREJHQlVTX1RQTDFfMCA9IDcyLAorCUE2WFhfREJHQlVTX1RQTDFfMSA9IDczLAorCUE2WFhf REJHQlVTX1RQTDFfMiA9IDc0LAorCUE2WFhfREJHQlVTX1RQTDFfMyA9IDc1LAorfTsKKwogZW51 bSBhNnh4X3RleF9maWx0ZXIgewogCUE2WFhfVEVYX05FQVJFU1QgPSAwLAogCUE2WFhfVEVYX0xJ TkVBUiA9IDEsCkBAIC0xNzY1LDEyICsxODU3LDM5IEBAIHN0YXRpYyBpbmxpbmUgdWludDMyX3Qg QTZYWF9VQ0hFX0NMSUVOVF9QRl9QRVJGU0VMKHVpbnQzMl90IHZhbCkKIAogI2RlZmluZSBSRUdf QTZYWF9WQklGX1ZFUlNJT04JCQkJCTB4MDAwMDMwMDAKIAorI2RlZmluZSBSRUdfQTZYWF9WQklG X0NMS09OCQkJCQkweDAwMDAzMDAxCisjZGVmaW5lIEE2WFhfVkJJRl9DTEtPTl9GT1JDRV9PTl9U RVNUQlVTCQkJMHgwMDAwMDAwMgorCiAjZGVmaW5lIFJFR19BNlhYX1ZCSUZfR0FURV9PRkZfV1JS RVFfRU4JCQkJMHgwMDAwMzAyYQogCiAjZGVmaW5lIFJFR19BNlhYX1ZCSUZfWElOX0hBTFRfQ1RS TDAJCQkJMHgwMDAwMzA4MAogCiAjZGVmaW5lIFJFR19BNlhYX1ZCSUZfWElOX0hBTFRfQ1RSTDEJ CQkJMHgwMDAwMzA4MQogCisjZGVmaW5lIFJFR19BNlhYX1ZCSUZfVEVTVF9CVVNfT1VUX0NUUkwJ CQkJMHgwMDAwMzA4NAorCisjZGVmaW5lIFJFR19BNlhYX1ZCSUZfVEVTVF9CVVMxX0NUUkwwCQkJ CTB4MDAwMDMwODUKKworI2RlZmluZSBSRUdfQTZYWF9WQklGX1RFU1RfQlVTMV9DVFJMMQkJCQkw eDAwMDAzMDg2CisjZGVmaW5lIEE2WFhfVkJJRl9URVNUX0JVUzFfQ1RSTDFfREFUQV9TRUxfX01B U0sJCTB4MDAwMDAwMGYKKyNkZWZpbmUgQTZYWF9WQklGX1RFU1RfQlVTMV9DVFJMMV9EQVRBX1NF TF9fU0hJRlQJCTAKK3N0YXRpYyBpbmxpbmUgdWludDMyX3QgQTZYWF9WQklGX1RFU1RfQlVTMV9D VFJMMV9EQVRBX1NFTCh1aW50MzJfdCB2YWwpCit7CisJcmV0dXJuICgodmFsKSA8PCBBNlhYX1ZC SUZfVEVTVF9CVVMxX0NUUkwxX0RBVEFfU0VMX19TSElGVCkgJiBBNlhYX1ZCSUZfVEVTVF9CVVMx X0NUUkwxX0RBVEFfU0VMX19NQVNLOworfQorCisjZGVmaW5lIFJFR19BNlhYX1ZCSUZfVEVTVF9C VVMyX0NUUkwwCQkJCTB4MDAwMDMwODcKKworI2RlZmluZSBSRUdfQTZYWF9WQklGX1RFU1RfQlVT Ml9DVFJMMQkJCQkweDAwMDAzMDg4CisjZGVmaW5lIEE2WFhfVkJJRl9URVNUX0JVUzJfQ1RSTDFf REFUQV9TRUxfX01BU0sJCTB4MDAwMDAxZmYKKyNkZWZpbmUgQTZYWF9WQklGX1RFU1RfQlVTMl9D VFJMMV9EQVRBX1NFTF9fU0hJRlQJCTAKK3N0YXRpYyBpbmxpbmUgdWludDMyX3QgQTZYWF9WQklG X1RFU1RfQlVTMl9DVFJMMV9EQVRBX1NFTCh1aW50MzJfdCB2YWwpCit7CisJcmV0dXJuICgodmFs KSA8PCBBNlhYX1ZCSUZfVEVTVF9CVVMyX0NUUkwxX0RBVEFfU0VMX19TSElGVCkgJiBBNlhYX1ZC SUZfVEVTVF9CVVMyX0NUUkwxX0RBVEFfU0VMX19NQVNLOworfQorCisjZGVmaW5lIFJFR19BNlhY X1ZCSUZfVEVTVF9CVVNfT1VUCQkJCTB4MDAwMDMwOGMKKwogI2RlZmluZSBSRUdfQTZYWF9WQklG X1BFUkZfQ05UX1NFTDAJCQkJMHgwMDAwMzBkMAogCiAjZGVmaW5lIFJFR19BNlhYX1ZCSUZfUEVS Rl9DTlRfU0VMMQkJCQkweDAwMDAzMGQxCkBAIC0xODEzLDIyOCArMTkzMiw2IEBAIHN0YXRpYyBp bmxpbmUgdWludDMyX3QgQTZYWF9VQ0hFX0NMSUVOVF9QRl9QRVJGU0VMKHVpbnQzMl90IHZhbCkK IAogI2RlZmluZSBSRUdfQTZYWF9WQklGX1BFUkZfUFdSX0NOVF9ISUdIMgkJCTB4MDAwMDMxMWEK IAotI2RlZmluZSBSRUdfQTZYWF9DWF9EQkdDX0NGR19EQkdCVVNfU0VMX0EJCQkweDAwMDE4NDAw Ci0KLSNkZWZpbmUgUkVHX0E2WFhfQ1hfREJHQ19DRkdfREJHQlVTX1NFTF9CCQkJMHgwMDAxODQw MQotCi0jZGVmaW5lIFJFR19BNlhYX0NYX0RCR0NfQ0ZHX0RCR0JVU19TRUxfQwkJCTB4MDAwMTg0 MDIKLQotI2RlZmluZSBSRUdfQTZYWF9DWF9EQkdDX0NGR19EQkdCVVNfU0VMX0QJCQkweDAwMDE4 NDAzCi0jZGVmaW5lIEE2WFhfQ1hfREJHQ19DRkdfREJHQlVTX1NFTF9EX1BJTkdfSU5ERVhfX01B U0sJCTB4MDAwMDAwZmYKLSNkZWZpbmUgQTZYWF9DWF9EQkdDX0NGR19EQkdCVVNfU0VMX0RfUElO R19JTkRFWF9fU0hJRlQJCTAKLXN0YXRpYyBpbmxpbmUgdWludDMyX3QgQTZYWF9DWF9EQkdDX0NG R19EQkdCVVNfU0VMX0RfUElOR19JTkRFWCh1aW50MzJfdCB2YWwpCi17Ci0JcmV0dXJuICgodmFs KSA8PCBBNlhYX0NYX0RCR0NfQ0ZHX0RCR0JVU19TRUxfRF9QSU5HX0lOREVYX19TSElGVCkgJiBB NlhYX0NYX0RCR0NfQ0ZHX0RCR0JVU19TRUxfRF9QSU5HX0lOREVYX19NQVNLOwotfQotI2RlZmlu ZSBBNlhYX0NYX0RCR0NfQ0ZHX0RCR0JVU19TRUxfRF9QSU5HX0JMS19TRUxfX01BU0sJMHgwMDAw ZmYwMAotI2RlZmluZSBBNlhYX0NYX0RCR0NfQ0ZHX0RCR0JVU19TRUxfRF9QSU5HX0JMS19TRUxf X1NISUZUCTgKLXN0YXRpYyBpbmxpbmUgdWludDMyX3QgQTZYWF9DWF9EQkdDX0NGR19EQkdCVVNf U0VMX0RfUElOR19CTEtfU0VMKHVpbnQzMl90IHZhbCkKLXsKLQlyZXR1cm4gKCh2YWwpIDw8IEE2 WFhfQ1hfREJHQ19DRkdfREJHQlVTX1NFTF9EX1BJTkdfQkxLX1NFTF9fU0hJRlQpICYgQTZYWF9D WF9EQkdDX0NGR19EQkdCVVNfU0VMX0RfUElOR19CTEtfU0VMX19NQVNLOwotfQotCi0jZGVmaW5l IFJFR19BNlhYX0NYX0RCR0NfQ0ZHX0RCR0JVU19DTlRMVAkJCTB4MDAwMTg0MDQKLSNkZWZpbmUg QTZYWF9DWF9EQkdDX0NGR19EQkdCVVNfQ05UTFRfVFJBQ0VFTl9fTUFTSwkJMHgwMDAwMDAzZgot I2RlZmluZSBBNlhYX0NYX0RCR0NfQ0ZHX0RCR0JVU19DTlRMVF9UUkFDRUVOX19TSElGVAkJMAot c3RhdGljIGlubGluZSB1aW50MzJfdCBBNlhYX0NYX0RCR0NfQ0ZHX0RCR0JVU19DTlRMVF9UUkFD RUVOKHVpbnQzMl90IHZhbCkKLXsKLQlyZXR1cm4gKCh2YWwpIDw8IEE2WFhfQ1hfREJHQ19DRkdf REJHQlVTX0NOVExUX1RSQUNFRU5fX1NISUZUKSAmIEE2WFhfQ1hfREJHQ19DRkdfREJHQlVTX0NO VExUX1RSQUNFRU5fX01BU0s7Ci19Ci0jZGVmaW5lIEE2WFhfQ1hfREJHQ19DRkdfREJHQlVTX0NO VExUX0dSQU5VX19NQVNLCQkweDAwMDA3MDAwCi0jZGVmaW5lIEE2WFhfQ1hfREJHQ19DRkdfREJH QlVTX0NOVExUX0dSQU5VX19TSElGVAkJMTIKLXN0YXRpYyBpbmxpbmUgdWludDMyX3QgQTZYWF9D WF9EQkdDX0NGR19EQkdCVVNfQ05UTFRfR1JBTlUodWludDMyX3QgdmFsKQotewotCXJldHVybiAo KHZhbCkgPDwgQTZYWF9DWF9EQkdDX0NGR19EQkdCVVNfQ05UTFRfR1JBTlVfX1NISUZUKSAmIEE2 WFhfQ1hfREJHQ19DRkdfREJHQlVTX0NOVExUX0dSQU5VX19NQVNLOwotfQotI2RlZmluZSBBNlhY X0NYX0RCR0NfQ0ZHX0RCR0JVU19DTlRMVF9TRUdUX19NQVNLCQkweGYwMDAwMDAwCi0jZGVmaW5l IEE2WFhfQ1hfREJHQ19DRkdfREJHQlVTX0NOVExUX1NFR1RfX1NISUZUCQkyOAotc3RhdGljIGlu bGluZSB1aW50MzJfdCBBNlhYX0NYX0RCR0NfQ0ZHX0RCR0JVU19DTlRMVF9TRUdUKHVpbnQzMl90 IHZhbCkKLXsKLQlyZXR1cm4gKCh2YWwpIDw8IEE2WFhfQ1hfREJHQ19DRkdfREJHQlVTX0NOVExU X1NFR1RfX1NISUZUKSAmIEE2WFhfQ1hfREJHQ19DRkdfREJHQlVTX0NOVExUX1NFR1RfX01BU0s7 Ci19Ci0KLSNkZWZpbmUgUkVHX0E2WFhfQ1hfREJHQ19DRkdfREJHQlVTX0NOVExNCQkJMHgwMDAx ODQwNQotI2RlZmluZSBBNlhYX0NYX0RCR0NfQ0ZHX0RCR0JVU19DTlRMTV9FTkFCTEVfX01BU0sJ CTB4MGYwMDAwMDAKLSNkZWZpbmUgQTZYWF9DWF9EQkdDX0NGR19EQkdCVVNfQ05UTE1fRU5BQkxF X19TSElGVAkJMjQKLXN0YXRpYyBpbmxpbmUgdWludDMyX3QgQTZYWF9DWF9EQkdDX0NGR19EQkdC VVNfQ05UTE1fRU5BQkxFKHVpbnQzMl90IHZhbCkKLXsKLQlyZXR1cm4gKCh2YWwpIDw8IEE2WFhf Q1hfREJHQ19DRkdfREJHQlVTX0NOVExNX0VOQUJMRV9fU0hJRlQpICYgQTZYWF9DWF9EQkdDX0NG R19EQkdCVVNfQ05UTE1fRU5BQkxFX19NQVNLOwotfQotCi0jZGVmaW5lIFJFR19BNlhYX0NYX0RC R0NfQ0ZHX0RCR0JVU19JVlRMXzAJCQkweDAwMDE4NDA4Ci0KLSNkZWZpbmUgUkVHX0E2WFhfQ1hf REJHQ19DRkdfREJHQlVTX0lWVExfMQkJCTB4MDAwMTg0MDkKLQotI2RlZmluZSBSRUdfQTZYWF9D WF9EQkdDX0NGR19EQkdCVVNfSVZUTF8yCQkJMHgwMDAxODQwYQotCi0jZGVmaW5lIFJFR19BNlhY X0NYX0RCR0NfQ0ZHX0RCR0JVU19JVlRMXzMJCQkweDAwMDE4NDBiCi0KLSNkZWZpbmUgUkVHX0E2 WFhfQ1hfREJHQ19DRkdfREJHQlVTX01BU0tMXzAJCQkweDAwMDE4NDBjCi0KLSNkZWZpbmUgUkVH X0E2WFhfQ1hfREJHQ19DRkdfREJHQlVTX01BU0tMXzEJCQkweDAwMDE4NDBkCi0KLSNkZWZpbmUg UkVHX0E2WFhfQ1hfREJHQ19DRkdfREJHQlVTX01BU0tMXzIJCQkweDAwMDE4NDBlCi0KLSNkZWZp bmUgUkVHX0E2WFhfQ1hfREJHQ19DRkdfREJHQlVTX01BU0tMXzMJCQkweDAwMDE4NDBmCi0KLSNk ZWZpbmUgUkVHX0E2WFhfQ1hfREJHQ19DRkdfREJHQlVTX0JZVEVMXzAJCQkweDAwMDE4NDEwCi0j ZGVmaW5lIEE2WFhfQ1hfREJHQ19DRkdfREJHQlVTX0JZVEVMXzBfQllURUwwX19NQVNLCQkweDAw MDAwMDBmCi0jZGVmaW5lIEE2WFhfQ1hfREJHQ19DRkdfREJHQlVTX0JZVEVMXzBfQllURUwwX19T SElGVAkJMAotc3RhdGljIGlubGluZSB1aW50MzJfdCBBNlhYX0NYX0RCR0NfQ0ZHX0RCR0JVU19C WVRFTF8wX0JZVEVMMCh1aW50MzJfdCB2YWwpCi17Ci0JcmV0dXJuICgodmFsKSA8PCBBNlhYX0NY X0RCR0NfQ0ZHX0RCR0JVU19CWVRFTF8wX0JZVEVMMF9fU0hJRlQpICYgQTZYWF9DWF9EQkdDX0NG R19EQkdCVVNfQllURUxfMF9CWVRFTDBfX01BU0s7Ci19Ci0jZGVmaW5lIEE2WFhfQ1hfREJHQ19D RkdfREJHQlVTX0JZVEVMXzBfQllURUwxX19NQVNLCQkweDAwMDAwMGYwCi0jZGVmaW5lIEE2WFhf Q1hfREJHQ19DRkdfREJHQlVTX0JZVEVMXzBfQllURUwxX19TSElGVAkJNAotc3RhdGljIGlubGlu ZSB1aW50MzJfdCBBNlhYX0NYX0RCR0NfQ0ZHX0RCR0JVU19CWVRFTF8wX0JZVEVMMSh1aW50MzJf dCB2YWwpCi17Ci0JcmV0dXJuICgodmFsKSA8PCBBNlhYX0NYX0RCR0NfQ0ZHX0RCR0JVU19CWVRF TF8wX0JZVEVMMV9fU0hJRlQpICYgQTZYWF9DWF9EQkdDX0NGR19EQkdCVVNfQllURUxfMF9CWVRF TDFfX01BU0s7Ci19Ci0jZGVmaW5lIEE2WFhfQ1hfREJHQ19DRkdfREJHQlVTX0JZVEVMXzBfQllU RUwyX19NQVNLCQkweDAwMDAwZjAwCi0jZGVmaW5lIEE2WFhfQ1hfREJHQ19DRkdfREJHQlVTX0JZ VEVMXzBfQllURUwyX19TSElGVAkJOAotc3RhdGljIGlubGluZSB1aW50MzJfdCBBNlhYX0NYX0RC R0NfQ0ZHX0RCR0JVU19CWVRFTF8wX0JZVEVMMih1aW50MzJfdCB2YWwpCi17Ci0JcmV0dXJuICgo dmFsKSA8PCBBNlhYX0NYX0RCR0NfQ0ZHX0RCR0JVU19CWVRFTF8wX0JZVEVMMl9fU0hJRlQpICYg QTZYWF9DWF9EQkdDX0NGR19EQkdCVVNfQllURUxfMF9CWVRFTDJfX01BU0s7Ci19Ci0jZGVmaW5l IEE2WFhfQ1hfREJHQ19DRkdfREJHQlVTX0JZVEVMXzBfQllURUwzX19NQVNLCQkweDAwMDBmMDAw Ci0jZGVmaW5lIEE2WFhfQ1hfREJHQ19DRkdfREJHQlVTX0JZVEVMXzBfQllURUwzX19TSElGVAkJ MTIKLXN0YXRpYyBpbmxpbmUgdWludDMyX3QgQTZYWF9DWF9EQkdDX0NGR19EQkdCVVNfQllURUxf MF9CWVRFTDModWludDMyX3QgdmFsKQotewotCXJldHVybiAoKHZhbCkgPDwgQTZYWF9DWF9EQkdD X0NGR19EQkdCVVNfQllURUxfMF9CWVRFTDNfX1NISUZUKSAmIEE2WFhfQ1hfREJHQ19DRkdfREJH QlVTX0JZVEVMXzBfQllURUwzX19NQVNLOwotfQotI2RlZmluZSBBNlhYX0NYX0RCR0NfQ0ZHX0RC R0JVU19CWVRFTF8wX0JZVEVMNF9fTUFTSwkJMHgwMDBmMDAwMAotI2RlZmluZSBBNlhYX0NYX0RC R0NfQ0ZHX0RCR0JVU19CWVRFTF8wX0JZVEVMNF9fU0hJRlQJCTE2Ci1zdGF0aWMgaW5saW5lIHVp bnQzMl90IEE2WFhfQ1hfREJHQ19DRkdfREJHQlVTX0JZVEVMXzBfQllURUw0KHVpbnQzMl90IHZh bCkKLXsKLQlyZXR1cm4gKCh2YWwpIDw8IEE2WFhfQ1hfREJHQ19DRkdfREJHQlVTX0JZVEVMXzBf QllURUw0X19TSElGVCkgJiBBNlhYX0NYX0RCR0NfQ0ZHX0RCR0JVU19CWVRFTF8wX0JZVEVMNF9f TUFTSzsKLX0KLSNkZWZpbmUgQTZYWF9DWF9EQkdDX0NGR19EQkdCVVNfQllURUxfMF9CWVRFTDVf X01BU0sJCTB4MDBmMDAwMDAKLSNkZWZpbmUgQTZYWF9DWF9EQkdDX0NGR19EQkdCVVNfQllURUxf MF9CWVRFTDVfX1NISUZUCQkyMAotc3RhdGljIGlubGluZSB1aW50MzJfdCBBNlhYX0NYX0RCR0Nf Q0ZHX0RCR0JVU19CWVRFTF8wX0JZVEVMNSh1aW50MzJfdCB2YWwpCi17Ci0JcmV0dXJuICgodmFs KSA8PCBBNlhYX0NYX0RCR0NfQ0ZHX0RCR0JVU19CWVRFTF8wX0JZVEVMNV9fU0hJRlQpICYgQTZY WF9DWF9EQkdDX0NGR19EQkdCVVNfQllURUxfMF9CWVRFTDVfX01BU0s7Ci19Ci0jZGVmaW5lIEE2 WFhfQ1hfREJHQ19DRkdfREJHQlVTX0JZVEVMXzBfQllURUw2X19NQVNLCQkweDBmMDAwMDAwCi0j ZGVmaW5lIEE2WFhfQ1hfREJHQ19DRkdfREJHQlVTX0JZVEVMXzBfQllURUw2X19TSElGVAkJMjQK LXN0YXRpYyBpbmxpbmUgdWludDMyX3QgQTZYWF9DWF9EQkdDX0NGR19EQkdCVVNfQllURUxfMF9C WVRFTDYodWludDMyX3QgdmFsKQotewotCXJldHVybiAoKHZhbCkgPDwgQTZYWF9DWF9EQkdDX0NG R19EQkdCVVNfQllURUxfMF9CWVRFTDZfX1NISUZUKSAmIEE2WFhfQ1hfREJHQ19DRkdfREJHQlVT X0JZVEVMXzBfQllURUw2X19NQVNLOwotfQotI2RlZmluZSBBNlhYX0NYX0RCR0NfQ0ZHX0RCR0JV U19CWVRFTF8wX0JZVEVMN19fTUFTSwkJMHhmMDAwMDAwMAotI2RlZmluZSBBNlhYX0NYX0RCR0Nf Q0ZHX0RCR0JVU19CWVRFTF8wX0JZVEVMN19fU0hJRlQJCTI4Ci1zdGF0aWMgaW5saW5lIHVpbnQz Ml90IEE2WFhfQ1hfREJHQ19DRkdfREJHQlVTX0JZVEVMXzBfQllURUw3KHVpbnQzMl90IHZhbCkK LXsKLQlyZXR1cm4gKCh2YWwpIDw8IEE2WFhfQ1hfREJHQ19DRkdfREJHQlVTX0JZVEVMXzBfQllU RUw3X19TSElGVCkgJiBBNlhYX0NYX0RCR0NfQ0ZHX0RCR0JVU19CWVRFTF8wX0JZVEVMN19fTUFT SzsKLX0KLQotI2RlZmluZSBSRUdfQTZYWF9DWF9EQkdDX0NGR19EQkdCVVNfQllURUxfMQkJCTB4 MDAwMTg0MTEKLSNkZWZpbmUgQTZYWF9DWF9EQkdDX0NGR19EQkdCVVNfQllURUxfMV9CWVRFTDhf X01BU0sJCTB4MDAwMDAwMGYKLSNkZWZpbmUgQTZYWF9DWF9EQkdDX0NGR19EQkdCVVNfQllURUxf MV9CWVRFTDhfX1NISUZUCQkwCi1zdGF0aWMgaW5saW5lIHVpbnQzMl90IEE2WFhfQ1hfREJHQ19D RkdfREJHQlVTX0JZVEVMXzFfQllURUw4KHVpbnQzMl90IHZhbCkKLXsKLQlyZXR1cm4gKCh2YWwp IDw8IEE2WFhfQ1hfREJHQ19DRkdfREJHQlVTX0JZVEVMXzFfQllURUw4X19TSElGVCkgJiBBNlhY X0NYX0RCR0NfQ0ZHX0RCR0JVU19CWVRFTF8xX0JZVEVMOF9fTUFTSzsKLX0KLSNkZWZpbmUgQTZY WF9DWF9EQkdDX0NGR19EQkdCVVNfQllURUxfMV9CWVRFTDlfX01BU0sJCTB4MDAwMDAwZjAKLSNk ZWZpbmUgQTZYWF9DWF9EQkdDX0NGR19EQkdCVVNfQllURUxfMV9CWVRFTDlfX1NISUZUCQk0Ci1z dGF0aWMgaW5saW5lIHVpbnQzMl90IEE2WFhfQ1hfREJHQ19DRkdfREJHQlVTX0JZVEVMXzFfQllU RUw5KHVpbnQzMl90IHZhbCkKLXsKLQlyZXR1cm4gKCh2YWwpIDw8IEE2WFhfQ1hfREJHQ19DRkdf REJHQlVTX0JZVEVMXzFfQllURUw5X19TSElGVCkgJiBBNlhYX0NYX0RCR0NfQ0ZHX0RCR0JVU19C WVRFTF8xX0JZVEVMOV9fTUFTSzsKLX0KLSNkZWZpbmUgQTZYWF9DWF9EQkdDX0NGR19EQkdCVVNf QllURUxfMV9CWVRFTDEwX19NQVNLCQkweDAwMDAwZjAwCi0jZGVmaW5lIEE2WFhfQ1hfREJHQ19D RkdfREJHQlVTX0JZVEVMXzFfQllURUwxMF9fU0hJRlQJCTgKLXN0YXRpYyBpbmxpbmUgdWludDMy X3QgQTZYWF9DWF9EQkdDX0NGR19EQkdCVVNfQllURUxfMV9CWVRFTDEwKHVpbnQzMl90IHZhbCkK LXsKLQlyZXR1cm4gKCh2YWwpIDw8IEE2WFhfQ1hfREJHQ19DRkdfREJHQlVTX0JZVEVMXzFfQllU RUwxMF9fU0hJRlQpICYgQTZYWF9DWF9EQkdDX0NGR19EQkdCVVNfQllURUxfMV9CWVRFTDEwX19N QVNLOwotfQotI2RlZmluZSBBNlhYX0NYX0RCR0NfQ0ZHX0RCR0JVU19CWVRFTF8xX0JZVEVMMTFf X01BU0sJCTB4MDAwMGYwMDAKLSNkZWZpbmUgQTZYWF9DWF9EQkdDX0NGR19EQkdCVVNfQllURUxf MV9CWVRFTDExX19TSElGVAkJMTIKLXN0YXRpYyBpbmxpbmUgdWludDMyX3QgQTZYWF9DWF9EQkdD X0NGR19EQkdCVVNfQllURUxfMV9CWVRFTDExKHVpbnQzMl90IHZhbCkKLXsKLQlyZXR1cm4gKCh2 YWwpIDw8IEE2WFhfQ1hfREJHQ19DRkdfREJHQlVTX0JZVEVMXzFfQllURUwxMV9fU0hJRlQpICYg QTZYWF9DWF9EQkdDX0NGR19EQkdCVVNfQllURUxfMV9CWVRFTDExX19NQVNLOwotfQotI2RlZmlu ZSBBNlhYX0NYX0RCR0NfQ0ZHX0RCR0JVU19CWVRFTF8xX0JZVEVMMTJfX01BU0sJCTB4MDAwZjAw MDAKLSNkZWZpbmUgQTZYWF9DWF9EQkdDX0NGR19EQkdCVVNfQllURUxfMV9CWVRFTDEyX19TSElG VAkJMTYKLXN0YXRpYyBpbmxpbmUgdWludDMyX3QgQTZYWF9DWF9EQkdDX0NGR19EQkdCVVNfQllU RUxfMV9CWVRFTDEyKHVpbnQzMl90IHZhbCkKLXsKLQlyZXR1cm4gKCh2YWwpIDw8IEE2WFhfQ1hf REJHQ19DRkdfREJHQlVTX0JZVEVMXzFfQllURUwxMl9fU0hJRlQpICYgQTZYWF9DWF9EQkdDX0NG R19EQkdCVVNfQllURUxfMV9CWVRFTDEyX19NQVNLOwotfQotI2RlZmluZSBBNlhYX0NYX0RCR0Nf Q0ZHX0RCR0JVU19CWVRFTF8xX0JZVEVMMTNfX01BU0sJCTB4MDBmMDAwMDAKLSNkZWZpbmUgQTZY WF9DWF9EQkdDX0NGR19EQkdCVVNfQllURUxfMV9CWVRFTDEzX19TSElGVAkJMjAKLXN0YXRpYyBp bmxpbmUgdWludDMyX3QgQTZYWF9DWF9EQkdDX0NGR19EQkdCVVNfQllURUxfMV9CWVRFTDEzKHVp bnQzMl90IHZhbCkKLXsKLQlyZXR1cm4gKCh2YWwpIDw8IEE2WFhfQ1hfREJHQ19DRkdfREJHQlVT X0JZVEVMXzFfQllURUwxM19fU0hJRlQpICYgQTZYWF9DWF9EQkdDX0NGR19EQkdCVVNfQllURUxf MV9CWVRFTDEzX19NQVNLOwotfQotI2RlZmluZSBBNlhYX0NYX0RCR0NfQ0ZHX0RCR0JVU19CWVRF TF8xX0JZVEVMMTRfX01BU0sJCTB4MGYwMDAwMDAKLSNkZWZpbmUgQTZYWF9DWF9EQkdDX0NGR19E QkdCVVNfQllURUxfMV9CWVRFTDE0X19TSElGVAkJMjQKLXN0YXRpYyBpbmxpbmUgdWludDMyX3Qg QTZYWF9DWF9EQkdDX0NGR19EQkdCVVNfQllURUxfMV9CWVRFTDE0KHVpbnQzMl90IHZhbCkKLXsK LQlyZXR1cm4gKCh2YWwpIDw8IEE2WFhfQ1hfREJHQ19DRkdfREJHQlVTX0JZVEVMXzFfQllURUwx NF9fU0hJRlQpICYgQTZYWF9DWF9EQkdDX0NGR19EQkdCVVNfQllURUxfMV9CWVRFTDE0X19NQVNL OwotfQotI2RlZmluZSBBNlhYX0NYX0RCR0NfQ0ZHX0RCR0JVU19CWVRFTF8xX0JZVEVMMTVfX01B U0sJCTB4ZjAwMDAwMDAKLSNkZWZpbmUgQTZYWF9DWF9EQkdDX0NGR19EQkdCVVNfQllURUxfMV9C WVRFTDE1X19TSElGVAkJMjgKLXN0YXRpYyBpbmxpbmUgdWludDMyX3QgQTZYWF9DWF9EQkdDX0NG R19EQkdCVVNfQllURUxfMV9CWVRFTDE1KHVpbnQzMl90IHZhbCkKLXsKLQlyZXR1cm4gKCh2YWwp IDw8IEE2WFhfQ1hfREJHQ19DRkdfREJHQlVTX0JZVEVMXzFfQllURUwxNV9fU0hJRlQpICYgQTZY WF9DWF9EQkdDX0NGR19EQkdCVVNfQllURUxfMV9CWVRFTDE1X19NQVNLOwotfQotCi0jZGVmaW5l IFJFR19BNlhYX0NYX0RCR0NfQ0ZHX0RCR0JVU19UUkFDRV9CVUYxCQkJMHgwMDAxODQyZgotCi0j ZGVmaW5lIFJFR19BNlhYX0NYX0RCR0NfQ0ZHX0RCR0JVU19UUkFDRV9CVUYyCQkJMHgwMDAxODQz MAotCi0jZGVmaW5lIFJFR19BNlhYX1BEQ19HUFVfRU5BQkxFX1BEQwkJCQkweDAwMDIxMTQwCi0K LSNkZWZpbmUgUkVHX0E2WFhfUERDX0dQVV9TRVFfU1RBUlRfQUREUgkJCQkweDAwMDIxMTQ4Ci0K LSNkZWZpbmUgUkVHX0E2WFhfUERDX0dQVV9UQ1MwX0NPTlRST0wJCQkJMHgwMDAyMTU0MAotCi0j ZGVmaW5lIFJFR19BNlhYX1BEQ19HUFVfVENTMF9DTURfRU5BQkxFX0JBTksJCQkweDAwMDIxNTQx Ci0KLSNkZWZpbmUgUkVHX0E2WFhfUERDX0dQVV9UQ1MwX0NNRF9XQUlUX0ZPUl9DTVBMX0JBTksJ CTB4MDAwMjE1NDIKLQotI2RlZmluZSBSRUdfQTZYWF9QRENfR1BVX1RDUzBfQ01EMF9NU0dJRAkJ CTB4MDAwMjE1NDMKLQotI2RlZmluZSBSRUdfQTZYWF9QRENfR1BVX1RDUzBfQ01EMF9BRERSCQkJ CTB4MDAwMjE1NDQKLQotI2RlZmluZSBSRUdfQTZYWF9QRENfR1BVX1RDUzBfQ01EMF9EQVRBCQkJ CTB4MDAwMjE1NDUKLQotI2RlZmluZSBSRUdfQTZYWF9QRENfR1BVX1RDUzFfQ09OVFJPTAkJCQkw eDAwMDIxNTcyCi0KLSNkZWZpbmUgUkVHX0E2WFhfUERDX0dQVV9UQ1MxX0NNRF9FTkFCTEVfQkFO SwkJCTB4MDAwMjE1NzMKLQotI2RlZmluZSBSRUdfQTZYWF9QRENfR1BVX1RDUzFfQ01EX1dBSVRf Rk9SX0NNUExfQkFOSwkJMHgwMDAyMTU3NAotCi0jZGVmaW5lIFJFR19BNlhYX1BEQ19HUFVfVENT MV9DTUQwX01TR0lECQkJMHgwMDAyMTU3NQotCi0jZGVmaW5lIFJFR19BNlhYX1BEQ19HUFVfVENT MV9DTUQwX0FERFIJCQkJMHgwMDAyMTU3NgotCi0jZGVmaW5lIFJFR19BNlhYX1BEQ19HUFVfVENT MV9DTUQwX0RBVEEJCQkJMHgwMDAyMTU3NwotCi0jZGVmaW5lIFJFR19BNlhYX1BEQ19HUFVfVENT Ml9DT05UUk9MCQkJCTB4MDAwMjE1YTQKLQotI2RlZmluZSBSRUdfQTZYWF9QRENfR1BVX1RDUzJf Q01EX0VOQUJMRV9CQU5LCQkJMHgwMDAyMTVhNQotCi0jZGVmaW5lIFJFR19BNlhYX1BEQ19HUFVf VENTMl9DTURfV0FJVF9GT1JfQ01QTF9CQU5LCQkweDAwMDIxNWE2Ci0KLSNkZWZpbmUgUkVHX0E2 WFhfUERDX0dQVV9UQ1MyX0NNRDBfTVNHSUQJCQkweDAwMDIxNWE3Ci0KLSNkZWZpbmUgUkVHX0E2 WFhfUERDX0dQVV9UQ1MyX0NNRDBfQUREUgkJCQkweDAwMDIxNWE4Ci0KLSNkZWZpbmUgUkVHX0E2 WFhfUERDX0dQVV9UQ1MyX0NNRDBfREFUQQkJCQkweDAwMDIxNWE5Ci0KLSNkZWZpbmUgUkVHX0E2 WFhfUERDX0dQVV9UQ1MzX0NPTlRST0wJCQkJMHgwMDAyMTVkNgotCi0jZGVmaW5lIFJFR19BNlhY X1BEQ19HUFVfVENTM19DTURfRU5BQkxFX0JBTksJCQkweDAwMDIxNWQ3Ci0KLSNkZWZpbmUgUkVH X0E2WFhfUERDX0dQVV9UQ1MzX0NNRF9XQUlUX0ZPUl9DTVBMX0JBTksJCTB4MDAwMjE1ZDgKLQot I2RlZmluZSBSRUdfQTZYWF9QRENfR1BVX1RDUzNfQ01EMF9NU0dJRAkJCTB4MDAwMjE1ZDkKLQot I2RlZmluZSBSRUdfQTZYWF9QRENfR1BVX1RDUzNfQ01EMF9BRERSCQkJCTB4MDAwMjE1ZGEKLQot I2RlZmluZSBSRUdfQTZYWF9QRENfR1BVX1RDUzNfQ01EMF9EQVRBCQkJCTB4MDAwMjE1ZGIKLQot I2RlZmluZSBSRUdfQTZYWF9QRENfR1BVX1NFUV9NRU1fMAkJCQkweDAwMGEwMDAwCi0KICNkZWZp bmUgUkVHX0E2WFhfWDFfV0lORE9XX09GRlNFVAkJCQkweDAwMDA4OGQ0CiAjZGVmaW5lIEE2WFhf WDFfV0lORE9XX09GRlNFVF9XSU5ET1dfT0ZGU0VUX0RJU0FCTEUJCTB4ODAwMDAwMDAKICNkZWZp bmUgQTZYWF9YMV9XSU5ET1dfT0ZGU0VUX1hfX01BU0sJCQkJMHgwMDAwN2ZmZgpAQCAtMjIwMCw2 ICsyMDk3LDggQEAgc3RhdGljIGlubGluZSB1aW50MzJfdCBSRUdfQTZYWF9WU0NfU0laRV9SRUco dWludDMyX3QgaTApIHsgcmV0dXJuIDB4MDAwMDBjNzggKwogCiAjZGVmaW5lIFJFR19BNlhYX1VD SEVfVU5LTk9XTl8wRTEyCQkJCTB4MDAwMDBlMTIKIAorI2RlZmluZSBSRUdfQTZYWF9HUkFTX1VO S05PV05fODAwMAkJCQkweDAwMDA4MDAwCisKICNkZWZpbmUgUkVHX0E2WFhfR1JBU19VTktOT1dO XzgwMDEJCQkJMHgwMDAwODAwMQogCiAjZGVmaW5lIFJFR19BNlhYX0dSQVNfVU5LTk9XTl84MDA0 CQkJCTB4MDAwMDgwMDQKQEAgLTIzNDQsNiArMjI0Myw4IEBAIHN0YXRpYyBpbmxpbmUgdWludDMy X3QgQTZYWF9HUkFTX1NVX0RFUFRIX0JVRkZFUl9JTkZPX0RFUFRIX0ZPUk1BVChlbnVtIGE2eHhf ZGVwCiAKICNkZWZpbmUgUkVHX0E2WFhfR1JBU19VTktOT1dOXzgwOUIJCQkJMHgwMDAwODA5Ygog CisjZGVmaW5lIFJFR19BNlhYX0dSQVNfVU5LTk9XTl84MEEwCQkJCTB4MDAwMDgwYTAKKwogI2Rl ZmluZSBSRUdfQTZYWF9HUkFTX1JBU19NU0FBX0NOVEwJCQkJMHgwMDAwODBhMgogI2RlZmluZSBB NlhYX0dSQVNfUkFTX01TQUFfQ05UTF9TQU1QTEVTX19NQVNLCQkJMHgwMDAwMDAwMwogI2RlZmlu ZSBBNlhYX0dSQVNfUkFTX01TQUFfQ05UTF9TQU1QTEVTX19TSElGVAkJCTAKQEAgLTI0NjQsNiAr MjM2NSw4IEBAIHN0YXRpYyBpbmxpbmUgdWludDMyX3QgQTZYWF9HUkFTX1NDX1dJTkRPV19TQ0lT U09SX0JSX1kodWludDMyX3QgdmFsKQogI2RlZmluZSBBNlhYX0dSQVNfTFJaX0NOVExfTFJaX1dS SVRFCQkJCTB4MDAwMDAwMDIKICNkZWZpbmUgQTZYWF9HUkFTX0xSWl9DTlRMX0dSRUFURVIJCQkJ MHgwMDAwMDAwNAogCisjZGVmaW5lIFJFR19BNlhYX0dSQVNfVU5LTk9XTl84MTAxCQkJCTB4MDAw MDgxMDEKKwogI2RlZmluZSBSRUdfQTZYWF9HUkFTXzJEX0JMSVRfSU5GTwkJCQkweDAwMDA4MTAy CiAjZGVmaW5lIEE2WFhfR1JBU18yRF9CTElUX0lORk9fQ09MT1JfRk9STUFUX19NQVNLCQkweDAw MDAwMGZmCiAjZGVmaW5lIEE2WFhfR1JBU18yRF9CTElUX0lORk9fQ09MT1JfRk9STUFUX19TSElG VAkJMApAQCAtMjQ5NCw2ICsyMzk3LDEwIEBAIHN0YXRpYyBpbmxpbmUgdWludDMyX3QgQTZYWF9H UkFTX0xSWl9CVUZGRVJfUElUQ0hfQVJSQVlfUElUQ0godWludDMyX3QgdmFsKQogCiAjZGVmaW5l IFJFR19BNlhYX0dSQVNfTFJaX0ZBU1RfQ0xFQVJfQlVGRkVSX0JBU0VfSEkJCTB4MDAwMDgxMDcK IAorI2RlZmluZSBSRUdfQTZYWF9HUkFTX1VOS05PV05fODEwOQkJCQkweDAwMDA4MTA5CisKKyNk ZWZpbmUgUkVHX0E2WFhfR1JBU19VTktOT1dOXzgxMTAJCQkJMHgwMDAwODExMAorCiAjZGVmaW5l IFJFR19BNlhYX0dSQVNfMkRfQkxJVF9DTlRMCQkJCTB4MDAwMDg0MDAKIAogI2RlZmluZSBSRUdf QTZYWF9HUkFTXzJEX1NSQ19UTF9YCQkJCTB4MDAwMDg0MDEKQEAgLTI3NDcsNiArMjY1NCwxMCBA QCBzdGF0aWMgaW5saW5lIHVpbnQzMl90IEE2WFhfUkJfRElUSEVSX0NOVExfRElUSEVSX01PREVf TVJUNyhlbnVtIGFkcmVub19yYl9kaXRoZQogI2RlZmluZSBBNlhYX1JCX1NSR0JfQ05UTF9TUkdC X01SVDYJCQkJMHgwMDAwMDA0MAogI2RlZmluZSBBNlhYX1JCX1NSR0JfQ05UTF9TUkdCX01SVDcJ CQkJMHgwMDAwMDA4MAogCisjZGVmaW5lIFJFR19BNlhYX1JCX1VOS05PV05fODgxMAkJCQkweDAw MDA4ODEwCisKKyNkZWZpbmUgUkVHX0E2WFhfUkJfVU5LTk9XTl84ODExCQkJCTB4MDAwMDg4MTEK KwogI2RlZmluZSBSRUdfQTZYWF9SQl9VTktOT1dOXzg4MTgJCQkJMHgwMDAwODgxOAogCiAjZGVm aW5lIFJFR19BNlhYX1JCX1VOS05PV05fODgxOQkJCQkweDAwMDA4ODE5CkBAIC0zMTc3LDE0ICsz MDg4LDE0IEBAIHN0YXRpYyBpbmxpbmUgdWludDMyX3QgQTZYWF9SQl9CTElUX0RTVF9BUlJBWV9Q SVRDSCh1aW50MzJfdCB2YWwpCiAKICNkZWZpbmUgUkVHX0E2WFhfUkJfQkxJVF9JTkZPCQkJCQkw eDAwMDA4OGUzCiAjZGVmaW5lIEE2WFhfUkJfQkxJVF9JTkZPX1VOSzAJCQkJCTB4MDAwMDAwMDEK LSNkZWZpbmUgQTZYWF9SQl9CTElUX0lORk9fRkFTVF9DTEVBUgkJCQkweDAwMDAwMDAyCisjZGVm aW5lIEE2WFhfUkJfQkxJVF9JTkZPX0dNRU0JCQkJCTB4MDAwMDAwMDIKICNkZWZpbmUgQTZYWF9S Ql9CTElUX0lORk9fSU5URUdFUgkJCQkweDAwMDAwMDA0Ci0jZGVmaW5lIEE2WFhfUkJfQkxJVF9J TkZPX1VOSzMJCQkJCTB4MDAwMDAwMDgKLSNkZWZpbmUgQTZYWF9SQl9CTElUX0lORk9fTUFTS19f TUFTSwkJCQkweDAwMDAwMGYwCi0jZGVmaW5lIEE2WFhfUkJfQkxJVF9JTkZPX01BU0tfX1NISUZU CQkJCTQKLXN0YXRpYyBpbmxpbmUgdWludDMyX3QgQTZYWF9SQl9CTElUX0lORk9fTUFTSyh1aW50 MzJfdCB2YWwpCisjZGVmaW5lIEE2WFhfUkJfQkxJVF9JTkZPX0RFUFRICQkJCQkweDAwMDAwMDA4 CisjZGVmaW5lIEE2WFhfUkJfQkxJVF9JTkZPX0NMRUFSX01BU0tfX01BU0sJCQkweDAwMDAwMGYw CisjZGVmaW5lIEE2WFhfUkJfQkxJVF9JTkZPX0NMRUFSX01BU0tfX1NISUZUCQkJNAorc3RhdGlj IGlubGluZSB1aW50MzJfdCBBNlhYX1JCX0JMSVRfSU5GT19DTEVBUl9NQVNLKHVpbnQzMl90IHZh bCkKIHsKLQlyZXR1cm4gKCh2YWwpIDw8IEE2WFhfUkJfQkxJVF9JTkZPX01BU0tfX1NISUZUKSAm IEE2WFhfUkJfQkxJVF9JTkZPX01BU0tfX01BU0s7CisJcmV0dXJuICgodmFsKSA8PCBBNlhYX1JC X0JMSVRfSU5GT19DTEVBUl9NQVNLX19TSElGVCkgJiBBNlhYX1JCX0JMSVRfSU5GT19DTEVBUl9N QVNLX19NQVNLOwogfQogCiAjZGVmaW5lIFJFR19BNlhYX1JCX1VOS05PV05fODhGMAkJCQkweDAw MDA4OGYwCkBAIC0zMjc0LDEyICszMTg1LDE2IEBAIHN0YXRpYyBpbmxpbmUgdWludDMyX3QgQTZY WF9SQl8yRF9EU1RfU0laRV9QSVRDSCh1aW50MzJfdCB2YWwpCiAKICNkZWZpbmUgUkVHX0E2WFhf UkJfVU5LTk9XTl84RTAxCQkJCTB4MDAwMDhlMDEKIAorI2RlZmluZSBSRUdfQTZYWF9SQl9VTktO T1dOXzhFMDQJCQkJMHgwMDAwOGUwNAorCiAjZGVmaW5lIFJFR19BNlhYX1JCX0NDVV9DTlRMCQkJ CQkweDAwMDA4ZTA3CiAKICNkZWZpbmUgUkVHX0E2WFhfVlBDX1VOS05PV05fOTEwMQkJCQkweDAw MDA5MTAxCiAKICNkZWZpbmUgUkVHX0E2WFhfVlBDX0dTX1NJVl9DTlRMCQkJCTB4MDAwMDkxMDQK IAorI2RlZmluZSBSRUdfQTZYWF9WUENfVU5LTk9XTl85MTA3CQkJCTB4MDAwMDkxMDcKKwogI2Rl ZmluZSBSRUdfQTZYWF9WUENfVU5LTk9XTl85MTA4CQkJCTB4MDAwMDkxMDgKIAogc3RhdGljIGlu bGluZSB1aW50MzJfdCBSRUdfQTZYWF9WUENfVkFSWUlOR19JTlRFUlAodWludDMyX3QgaTApIHsg cmV0dXJuIDB4MDAwMDkyMDAgKyAweDEqaTA7IH0KQEAgLTMzODUsNiArMzMwMCw4IEBAIHN0YXRp YyBpbmxpbmUgdWludDMyX3QgQTZYWF9WUENfQ05UTF8wX05VTU5PTlBPU1ZBUih1aW50MzJfdCB2 YWwpCiAjZGVmaW5lIEE2WFhfVlBDX1NPX0JVRl9DTlRMX0JVRjMJCQkJMHgwMDAwMDIwMAogI2Rl ZmluZSBBNlhYX1ZQQ19TT19CVUZfQ05UTF9FTkFCTEUJCQkJMHgwMDAwODAwMAogCisjZGVmaW5l IFJFR19BNlhYX1ZQQ19VTktOT1dOXzkzMDYJCQkJMHgwMDAwOTMwNgorCiAjZGVmaW5lIFJFR19B NlhYX1ZQQ19VTktOT1dOXzk2MDAJCQkJMHgwMDAwOTYwMAogCiAjZGVmaW5lIFJFR19BNlhYX1ZQ Q19VTktOT1dOXzk2MDIJCQkJMHgwMDAwOTYwMgpAQCAtMzM5Nyw4ICszMzE0LDE0IEBAIHN0YXRp YyBpbmxpbmUgdWludDMyX3QgQTZYWF9WUENfQ05UTF8wX05VTU5PTlBPU1ZBUih1aW50MzJfdCB2 YWwpCiAKICNkZWZpbmUgUkVHX0E2WFhfUENfVU5LTk9XTl85ODA1CQkJCTB4MDAwMDk4MDUKIAor I2RlZmluZSBSRUdfQTZYWF9QQ19VTktOT1dOXzk4MDYJCQkJMHgwMDAwOTgwNgorCisjZGVmaW5l IFJFR19BNlhYX1BDX1VOS05PV05fOTk4MAkJCQkweDAwMDA5OTgwCisKICNkZWZpbmUgUkVHX0E2 WFhfUENfVU5LTk9XTl85OTgxCQkJCTB4MDAwMDk5ODEKIAorI2RlZmluZSBSRUdfQTZYWF9QQ19V TktOT1dOXzk5OTAJCQkJMHgwMDAwOTk5MAorCiAjZGVmaW5lIFJFR19BNlhYX1BDX1BSSU1JVElW RV9DTlRMXzAJCQkJMHgwMDAwOWIwMAogI2RlZmluZSBBNlhYX1BDX1BSSU1JVElWRV9DTlRMXzBf UFJJTUlUSVZFX1JFU1RBUlQJCTB4MDAwMDAwMDEKICNkZWZpbmUgQTZYWF9QQ19QUklNSVRJVkVf Q05UTF8wX1BST1ZPS0lOR19WVFhfTEFTVAkJMHgwMDAwMDAwMgpAQCAtMzQxMCw2ICszMzMzLDcg QEAgc3RhdGljIGlubGluZSB1aW50MzJfdCBBNlhYX1BDX1BSSU1JVElWRV9DTlRMXzFfU1RSSURF X0lOX1ZQQyh1aW50MzJfdCB2YWwpCiB7CiAJcmV0dXJuICgodmFsKSA8PCBBNlhYX1BDX1BSSU1J VElWRV9DTlRMXzFfU1RSSURFX0lOX1ZQQ19fU0hJRlQpICYgQTZYWF9QQ19QUklNSVRJVkVfQ05U TF8xX1NUUklERV9JTl9WUENfX01BU0s7CiB9CisjZGVmaW5lIEE2WFhfUENfUFJJTUlUSVZFX0NO VExfMV9QU0laRQkJCQkweDAwMDAwMTAwCiAKICNkZWZpbmUgUkVHX0E2WFhfUENfVU5LTk9XTl85 QjA2CQkJCTB4MDAwMDliMDYKIApAQCAtMzQ4OCw2ICszNDEyLDggQEAgc3RhdGljIGlubGluZSB1 aW50MzJfdCBBNlhYX1ZGRF9DT05UUk9MXzNfUkVHSURfVEVTU1kodWludDMyX3QgdmFsKQogCiAj ZGVmaW5lIFJFR19BNlhYX1ZGRF9VTktOT1dOX0EwMDgJCQkJMHgwMDAwYTAwOAogCisjZGVmaW5l IFJFR19BNlhYX1ZGRF9VTktOT1dOX0EwMDkJCQkJMHgwMDAwYTAwOQorCiAjZGVmaW5lIFJFR19B NlhYX1ZGRF9JTkRFWF9PRkZTRVQJCQkJMHgwMDAwYTAwZQogCiAjZGVmaW5lIFJFR19BNlhYX1ZG RF9JTlNUQU5DRV9TVEFSVF9PRkZTRVQJCQkweDAwMDBhMDBmCkBAIC0zNjQwLDYgKzM1NjYsOCBA QCBzdGF0aWMgaW5saW5lIHVpbnQzMl90IEE2WFhfU1BfVlNfQ1RSTF9SRUcwX1RIUkVBRFNJWkUo ZW51bSBhM3h4X3RocmVhZHNpemUgdmFsKQogI2RlZmluZSBBNlhYX1NQX1ZTX0NUUkxfUkVHMF9Q SVhMT0RFTkFCTEUJCQkweDA0MDAwMDAwCiAjZGVmaW5lIEE2WFhfU1BfVlNfQ1RSTF9SRUcwX01F UkdFRFJFR1MJCQkJMHg4MDAwMDAwMAogCisjZGVmaW5lIFJFR19BNlhYX1NQX1VOS05PV05fQTgx QgkJCQkweDAwMDBhODFiCisKICNkZWZpbmUgUkVHX0E2WFhfU1BfVlNfT0JKX1NUQVJUX0xPCQkJ CTB4MDAwMGE4MWMKIAogI2RlZmluZSBSRUdfQTZYWF9TUF9WU19PQkpfU1RBUlRfSEkJCQkJMHgw MDAwYTgxZApAQCAtMzg4NCw2ICszODEyLDggQEAgc3RhdGljIGlubGluZSB1aW50MzJfdCBBNlhY X1NQX0ZTX0NUUkxfUkVHMF9USFJFQURTSVpFKGVudW0gYTN4eF90aHJlYWRzaXplIHZhbCkKICNk ZWZpbmUgQTZYWF9TUF9GU19DVFJMX1JFRzBfUElYTE9ERU5BQkxFCQkJMHgwNDAwMDAwMAogI2Rl ZmluZSBBNlhYX1NQX0ZTX0NUUkxfUkVHMF9NRVJHRURSRUdTCQkJCTB4ODAwMDAwMDAKIAorI2Rl ZmluZSBSRUdfQTZYWF9TUF9VTktOT1dOX0E5ODIJCQkJMHgwMDAwYTk4MgorCiAjZGVmaW5lIFJF R19BNlhYX1NQX0ZTX09CSl9TVEFSVF9MTwkJCQkweDAwMDBhOTgzCiAKICNkZWZpbmUgUkVHX0E2 WFhfU1BfRlNfT0JKX1NUQVJUX0hJCQkJCTB4MDAwMGE5ODQKQEAgLTM5ODEsNiArMzkxMSw4IEBA IHN0YXRpYyBpbmxpbmUgdWludDMyX3QgQTZYWF9TUF9GU19NUlRfUkVHX0NPTE9SX0ZPUk1BVChl bnVtIGE2eHhfY29sb3JfZm10IHZhbCkKICNkZWZpbmUgQTZYWF9TUF9GU19NUlRfUkVHX0NPTE9S X1VJTlQJCQkJMHgwMDAwMDIwMAogI2RlZmluZSBBNlhYX1NQX0ZTX01SVF9SRUdfQ09MT1JfU1JH QgkJCQkweDAwMDAwNDAwCiAKKyNkZWZpbmUgUkVHX0E2WFhfU1BfVU5LTk9XTl9BOTlFCQkJCTB4 MDAwMGE5OWUKKwogI2RlZmluZSBSRUdfQTZYWF9TUF9GU19URVhfQ09VTlQJCQkJMHgwMDAwYTlh NwogCiAjZGVmaW5lIFJFR19BNlhYX1NQX1VOS05PV05fQTlBOAkJCQkweDAwMDBhOWE4CkBAIC00 MDY2LDE0ICszOTk4LDIwIEBAIHN0YXRpYyBpbmxpbmUgdWludDMyX3QgQTZYWF9TUF9GU19DT05G SUdfTlNBTVAodWludDMyX3QgdmFsKQogCiAjZGVmaW5lIFJFR19BNlhYX1NQX0ZTX0lOU1RSTEVO CQkJCQkweDAwMDBhYjA1CiAKKyNkZWZpbmUgUkVHX0E2WFhfU1BfVU5LTk9XTl9BQjIwCQkJCTB4 MDAwMGFiMjAKKwogI2RlZmluZSBSRUdfQTZYWF9TUF9VTktOT1dOX0FFMDAJCQkJMHgwMDAwYWUw MAogCisjZGVmaW5lIFJFR19BNlhYX1NQX1VOS05PV05fQUUwMwkJCQkweDAwMDBhZTAzCisKICNk ZWZpbmUgUkVHX0E2WFhfU1BfVU5LTk9XTl9BRTA0CQkJCTB4MDAwMGFlMDQKIAogI2RlZmluZSBS RUdfQTZYWF9TUF9VTktOT1dOX0FFMEYJCQkJMHgwMDAwYWUwZgogCiAjZGVmaW5lIFJFR19BNlhY X1NQX1VOS05PV05fQjE4MgkJCQkweDAwMDBiMTgyCiAKKyNkZWZpbmUgUkVHX0E2WFhfU1BfVU5L Tk9XTl9CMTgzCQkJCTB4MDAwMGIxODMKKwogI2RlZmluZSBSRUdfQTZYWF9TUF9UUF9SQVNfTVNB QV9DTlRMCQkJCTB4MDAwMGIzMDAKICNkZWZpbmUgQTZYWF9TUF9UUF9SQVNfTVNBQV9DTlRMX1NB TVBMRVNfX01BU0sJCQkweDAwMDAwMDAzCiAjZGVmaW5lIEE2WFhfU1BfVFBfUkFTX01TQUFfQ05U TF9TQU1QTEVTX19TSElGVAkJCTAKQEAgLTQwOTcsNiArNDAzNSw4IEBAIHN0YXRpYyBpbmxpbmUg dWludDMyX3QgQTZYWF9TUF9UUF9ERVNUX01TQUFfQ05UTF9TQU1QTEVTKGVudW0gYTN4eF9tc2Fh X3NhbXBsZXMKIAogI2RlZmluZSBSRUdfQTZYWF9TUF9UUF9VTktOT1dOX0IzMDQJCQkJMHgwMDAw YjMwNAogCisjZGVmaW5lIFJFR19BNlhYX1NQX1RQX1VOS05PV05fQjMwOQkJCQkweDAwMDBiMzA5 CisKICNkZWZpbmUgUkVHX0E2WFhfU1BfUFNfMkRfU1JDX0lORk8JCQkJMHgwMDAwYjRjMAogI2Rl ZmluZSBBNlhYX1NQX1BTXzJEX1NSQ19JTkZPX0NPTE9SX0ZPUk1BVF9fTUFTSwkJMHgwMDAwMDBm ZgogI2RlZmluZSBBNlhYX1NQX1BTXzJEX1NSQ19JTkZPX0NPTE9SX0ZPUk1BVF9fU0hJRlQJCTAK QEAgLTQxNjIsNiArNDEwMiw4IEBAIHN0YXRpYyBpbmxpbmUgdWludDMyX3QgQTZYWF9ITFNRX0dT X0NOVExfQ09OU1RMRU4odWludDMyX3QgdmFsKQogCXJldHVybiAoKHZhbCA+PiAyKSA8PCBBNlhY X0hMU1FfR1NfQ05UTF9DT05TVExFTl9fU0hJRlQpICYgQTZYWF9ITFNRX0dTX0NOVExfQ09OU1RM RU5fX01BU0s7CiB9CiAKKyNkZWZpbmUgUkVHX0E2WFhfSExTUV9VTktOT1dOX0I5ODAJCQkJMHgw MDAwYjk4MAorCiAjZGVmaW5lIFJFR19BNlhYX0hMU1FfQ09OVFJPTF8xX1JFRwkJCQkweDAwMDBi OTgyCiAKICNkZWZpbmUgUkVHX0E2WFhfSExTUV9DT05UUk9MXzJfUkVHCQkJCTB4MDAwMGI5ODMK QEAgLTQ1NTgsNSArNDUwMCwyMjcgQEAgc3RhdGljIGlubGluZSB1aW50MzJfdCBBNlhYX1RFWF9D T05TVF84X0JBU0VfSEkodWludDMyX3QgdmFsKQogCiAjZGVmaW5lIFJFR19BNlhYX1RFWF9DT05T VF8xNQkJCQkJMHgwMDAwMDAwZgogCisjZGVmaW5lIFJFR19BNlhYX1BEQ19HUFVfRU5BQkxFX1BE QwkJCQkweDAwMDAxMTQwCisKKyNkZWZpbmUgUkVHX0E2WFhfUERDX0dQVV9TRVFfU1RBUlRfQURE UgkJCQkweDAwMDAxMTQ4CisKKyNkZWZpbmUgUkVHX0E2WFhfUERDX0dQVV9UQ1MwX0NPTlRST0wJ CQkJMHgwMDAwMTU0MAorCisjZGVmaW5lIFJFR19BNlhYX1BEQ19HUFVfVENTMF9DTURfRU5BQkxF X0JBTksJCQkweDAwMDAxNTQxCisKKyNkZWZpbmUgUkVHX0E2WFhfUERDX0dQVV9UQ1MwX0NNRF9X QUlUX0ZPUl9DTVBMX0JBTksJCTB4MDAwMDE1NDIKKworI2RlZmluZSBSRUdfQTZYWF9QRENfR1BV X1RDUzBfQ01EMF9NU0dJRAkJCTB4MDAwMDE1NDMKKworI2RlZmluZSBSRUdfQTZYWF9QRENfR1BV X1RDUzBfQ01EMF9BRERSCQkJCTB4MDAwMDE1NDQKKworI2RlZmluZSBSRUdfQTZYWF9QRENfR1BV X1RDUzBfQ01EMF9EQVRBCQkJCTB4MDAwMDE1NDUKKworI2RlZmluZSBSRUdfQTZYWF9QRENfR1BV X1RDUzFfQ09OVFJPTAkJCQkweDAwMDAxNTcyCisKKyNkZWZpbmUgUkVHX0E2WFhfUERDX0dQVV9U Q1MxX0NNRF9FTkFCTEVfQkFOSwkJCTB4MDAwMDE1NzMKKworI2RlZmluZSBSRUdfQTZYWF9QRENf R1BVX1RDUzFfQ01EX1dBSVRfRk9SX0NNUExfQkFOSwkJMHgwMDAwMTU3NAorCisjZGVmaW5lIFJF R19BNlhYX1BEQ19HUFVfVENTMV9DTUQwX01TR0lECQkJMHgwMDAwMTU3NQorCisjZGVmaW5lIFJF R19BNlhYX1BEQ19HUFVfVENTMV9DTUQwX0FERFIJCQkJMHgwMDAwMTU3NgorCisjZGVmaW5lIFJF R19BNlhYX1BEQ19HUFVfVENTMV9DTUQwX0RBVEEJCQkJMHgwMDAwMTU3NworCisjZGVmaW5lIFJF R19BNlhYX1BEQ19HUFVfVENTMl9DT05UUk9MCQkJCTB4MDAwMDE1YTQKKworI2RlZmluZSBSRUdf QTZYWF9QRENfR1BVX1RDUzJfQ01EX0VOQUJMRV9CQU5LCQkJMHgwMDAwMTVhNQorCisjZGVmaW5l IFJFR19BNlhYX1BEQ19HUFVfVENTMl9DTURfV0FJVF9GT1JfQ01QTF9CQU5LCQkweDAwMDAxNWE2 CisKKyNkZWZpbmUgUkVHX0E2WFhfUERDX0dQVV9UQ1MyX0NNRDBfTVNHSUQJCQkweDAwMDAxNWE3 CisKKyNkZWZpbmUgUkVHX0E2WFhfUERDX0dQVV9UQ1MyX0NNRDBfQUREUgkJCQkweDAwMDAxNWE4 CisKKyNkZWZpbmUgUkVHX0E2WFhfUERDX0dQVV9UQ1MyX0NNRDBfREFUQQkJCQkweDAwMDAxNWE5 CisKKyNkZWZpbmUgUkVHX0E2WFhfUERDX0dQVV9UQ1MzX0NPTlRST0wJCQkJMHgwMDAwMTVkNgor CisjZGVmaW5lIFJFR19BNlhYX1BEQ19HUFVfVENTM19DTURfRU5BQkxFX0JBTksJCQkweDAwMDAx NWQ3CisKKyNkZWZpbmUgUkVHX0E2WFhfUERDX0dQVV9UQ1MzX0NNRF9XQUlUX0ZPUl9DTVBMX0JB TksJCTB4MDAwMDE1ZDgKKworI2RlZmluZSBSRUdfQTZYWF9QRENfR1BVX1RDUzNfQ01EMF9NU0dJ RAkJCTB4MDAwMDE1ZDkKKworI2RlZmluZSBSRUdfQTZYWF9QRENfR1BVX1RDUzNfQ01EMF9BRERS CQkJCTB4MDAwMDE1ZGEKKworI2RlZmluZSBSRUdfQTZYWF9QRENfR1BVX1RDUzNfQ01EMF9EQVRB CQkJCTB4MDAwMDE1ZGIKKworI2RlZmluZSBSRUdfQTZYWF9QRENfR1BVX1NFUV9NRU1fMAkJCQkw eDAwMDAwMDAwCisKKyNkZWZpbmUgUkVHX0E2WFhfQ1hfREJHQ19DRkdfREJHQlVTX1NFTF9BCQkJ MHgwMDAwMDAwMAorI2RlZmluZSBBNlhYX0NYX0RCR0NfQ0ZHX0RCR0JVU19TRUxfQV9QSU5HX0lO REVYX19NQVNLCQkweDAwMDAwMGZmCisjZGVmaW5lIEE2WFhfQ1hfREJHQ19DRkdfREJHQlVTX1NF TF9BX1BJTkdfSU5ERVhfX1NISUZUCQkwCitzdGF0aWMgaW5saW5lIHVpbnQzMl90IEE2WFhfQ1hf REJHQ19DRkdfREJHQlVTX1NFTF9BX1BJTkdfSU5ERVgodWludDMyX3QgdmFsKQoreworCXJldHVy biAoKHZhbCkgPDwgQTZYWF9DWF9EQkdDX0NGR19EQkdCVVNfU0VMX0FfUElOR19JTkRFWF9fU0hJ RlQpICYgQTZYWF9DWF9EQkdDX0NGR19EQkdCVVNfU0VMX0FfUElOR19JTkRFWF9fTUFTSzsKK30K KyNkZWZpbmUgQTZYWF9DWF9EQkdDX0NGR19EQkdCVVNfU0VMX0FfUElOR19CTEtfU0VMX19NQVNL CTB4MDAwMGZmMDAKKyNkZWZpbmUgQTZYWF9DWF9EQkdDX0NGR19EQkdCVVNfU0VMX0FfUElOR19C TEtfU0VMX19TSElGVAk4CitzdGF0aWMgaW5saW5lIHVpbnQzMl90IEE2WFhfQ1hfREJHQ19DRkdf REJHQlVTX1NFTF9BX1BJTkdfQkxLX1NFTCh1aW50MzJfdCB2YWwpCit7CisJcmV0dXJuICgodmFs KSA8PCBBNlhYX0NYX0RCR0NfQ0ZHX0RCR0JVU19TRUxfQV9QSU5HX0JMS19TRUxfX1NISUZUKSAm IEE2WFhfQ1hfREJHQ19DRkdfREJHQlVTX1NFTF9BX1BJTkdfQkxLX1NFTF9fTUFTSzsKK30KKwor I2RlZmluZSBSRUdfQTZYWF9DWF9EQkdDX0NGR19EQkdCVVNfU0VMX0IJCQkweDAwMDAwMDAxCisK KyNkZWZpbmUgUkVHX0E2WFhfQ1hfREJHQ19DRkdfREJHQlVTX1NFTF9DCQkJMHgwMDAwMDAwMgor CisjZGVmaW5lIFJFR19BNlhYX0NYX0RCR0NfQ0ZHX0RCR0JVU19TRUxfRAkJCTB4MDAwMDAwMDMK KworI2RlZmluZSBSRUdfQTZYWF9DWF9EQkdDX0NGR19EQkdCVVNfQ05UTFQJCQkweDAwMDAwMDA0 CisjZGVmaW5lIEE2WFhfQ1hfREJHQ19DRkdfREJHQlVTX0NOVExUX1RSQUNFRU5fX01BU0sJCTB4 MDAwMDAwM2YKKyNkZWZpbmUgQTZYWF9DWF9EQkdDX0NGR19EQkdCVVNfQ05UTFRfVFJBQ0VFTl9f U0hJRlQJCTAKK3N0YXRpYyBpbmxpbmUgdWludDMyX3QgQTZYWF9DWF9EQkdDX0NGR19EQkdCVVNf Q05UTFRfVFJBQ0VFTih1aW50MzJfdCB2YWwpCit7CisJcmV0dXJuICgodmFsKSA8PCBBNlhYX0NY X0RCR0NfQ0ZHX0RCR0JVU19DTlRMVF9UUkFDRUVOX19TSElGVCkgJiBBNlhYX0NYX0RCR0NfQ0ZH X0RCR0JVU19DTlRMVF9UUkFDRUVOX19NQVNLOworfQorI2RlZmluZSBBNlhYX0NYX0RCR0NfQ0ZH X0RCR0JVU19DTlRMVF9HUkFOVV9fTUFTSwkJMHgwMDAwNzAwMAorI2RlZmluZSBBNlhYX0NYX0RC R0NfQ0ZHX0RCR0JVU19DTlRMVF9HUkFOVV9fU0hJRlQJCTEyCitzdGF0aWMgaW5saW5lIHVpbnQz Ml90IEE2WFhfQ1hfREJHQ19DRkdfREJHQlVTX0NOVExUX0dSQU5VKHVpbnQzMl90IHZhbCkKK3sK KwlyZXR1cm4gKCh2YWwpIDw8IEE2WFhfQ1hfREJHQ19DRkdfREJHQlVTX0NOVExUX0dSQU5VX19T SElGVCkgJiBBNlhYX0NYX0RCR0NfQ0ZHX0RCR0JVU19DTlRMVF9HUkFOVV9fTUFTSzsKK30KKyNk ZWZpbmUgQTZYWF9DWF9EQkdDX0NGR19EQkdCVVNfQ05UTFRfU0VHVF9fTUFTSwkJMHhmMDAwMDAw MAorI2RlZmluZSBBNlhYX0NYX0RCR0NfQ0ZHX0RCR0JVU19DTlRMVF9TRUdUX19TSElGVAkJMjgK K3N0YXRpYyBpbmxpbmUgdWludDMyX3QgQTZYWF9DWF9EQkdDX0NGR19EQkdCVVNfQ05UTFRfU0VH VCh1aW50MzJfdCB2YWwpCit7CisJcmV0dXJuICgodmFsKSA8PCBBNlhYX0NYX0RCR0NfQ0ZHX0RC R0JVU19DTlRMVF9TRUdUX19TSElGVCkgJiBBNlhYX0NYX0RCR0NfQ0ZHX0RCR0JVU19DTlRMVF9T RUdUX19NQVNLOworfQorCisjZGVmaW5lIFJFR19BNlhYX0NYX0RCR0NfQ0ZHX0RCR0JVU19DTlRM TQkJCTB4MDAwMDAwMDUKKyNkZWZpbmUgQTZYWF9DWF9EQkdDX0NGR19EQkdCVVNfQ05UTE1fRU5B QkxFX19NQVNLCQkweDBmMDAwMDAwCisjZGVmaW5lIEE2WFhfQ1hfREJHQ19DRkdfREJHQlVTX0NO VExNX0VOQUJMRV9fU0hJRlQJCTI0CitzdGF0aWMgaW5saW5lIHVpbnQzMl90IEE2WFhfQ1hfREJH Q19DRkdfREJHQlVTX0NOVExNX0VOQUJMRSh1aW50MzJfdCB2YWwpCit7CisJcmV0dXJuICgodmFs KSA8PCBBNlhYX0NYX0RCR0NfQ0ZHX0RCR0JVU19DTlRMTV9FTkFCTEVfX1NISUZUKSAmIEE2WFhf Q1hfREJHQ19DRkdfREJHQlVTX0NOVExNX0VOQUJMRV9fTUFTSzsKK30KKworI2RlZmluZSBSRUdf QTZYWF9DWF9EQkdDX0NGR19EQkdCVVNfSVZUTF8wCQkJMHgwMDAwMDAwOAorCisjZGVmaW5lIFJF R19BNlhYX0NYX0RCR0NfQ0ZHX0RCR0JVU19JVlRMXzEJCQkweDAwMDAwMDA5CisKKyNkZWZpbmUg UkVHX0E2WFhfQ1hfREJHQ19DRkdfREJHQlVTX0lWVExfMgkJCTB4MDAwMDAwMGEKKworI2RlZmlu ZSBSRUdfQTZYWF9DWF9EQkdDX0NGR19EQkdCVVNfSVZUTF8zCQkJMHgwMDAwMDAwYgorCisjZGVm aW5lIFJFR19BNlhYX0NYX0RCR0NfQ0ZHX0RCR0JVU19NQVNLTF8wCQkJMHgwMDAwMDAwYworCisj ZGVmaW5lIFJFR19BNlhYX0NYX0RCR0NfQ0ZHX0RCR0JVU19NQVNLTF8xCQkJMHgwMDAwMDAwZAor CisjZGVmaW5lIFJFR19BNlhYX0NYX0RCR0NfQ0ZHX0RCR0JVU19NQVNLTF8yCQkJMHgwMDAwMDAw ZQorCisjZGVmaW5lIFJFR19BNlhYX0NYX0RCR0NfQ0ZHX0RCR0JVU19NQVNLTF8zCQkJMHgwMDAw MDAwZgorCisjZGVmaW5lIFJFR19BNlhYX0NYX0RCR0NfQ0ZHX0RCR0JVU19CWVRFTF8wCQkJMHgw MDAwMDAxMAorI2RlZmluZSBBNlhYX0NYX0RCR0NfQ0ZHX0RCR0JVU19CWVRFTF8wX0JZVEVMMF9f TUFTSwkJMHgwMDAwMDAwZgorI2RlZmluZSBBNlhYX0NYX0RCR0NfQ0ZHX0RCR0JVU19CWVRFTF8w X0JZVEVMMF9fU0hJRlQJCTAKK3N0YXRpYyBpbmxpbmUgdWludDMyX3QgQTZYWF9DWF9EQkdDX0NG R19EQkdCVVNfQllURUxfMF9CWVRFTDAodWludDMyX3QgdmFsKQoreworCXJldHVybiAoKHZhbCkg PDwgQTZYWF9DWF9EQkdDX0NGR19EQkdCVVNfQllURUxfMF9CWVRFTDBfX1NISUZUKSAmIEE2WFhf Q1hfREJHQ19DRkdfREJHQlVTX0JZVEVMXzBfQllURUwwX19NQVNLOworfQorI2RlZmluZSBBNlhY X0NYX0RCR0NfQ0ZHX0RCR0JVU19CWVRFTF8wX0JZVEVMMV9fTUFTSwkJMHgwMDAwMDBmMAorI2Rl ZmluZSBBNlhYX0NYX0RCR0NfQ0ZHX0RCR0JVU19CWVRFTF8wX0JZVEVMMV9fU0hJRlQJCTQKK3N0 YXRpYyBpbmxpbmUgdWludDMyX3QgQTZYWF9DWF9EQkdDX0NGR19EQkdCVVNfQllURUxfMF9CWVRF TDEodWludDMyX3QgdmFsKQoreworCXJldHVybiAoKHZhbCkgPDwgQTZYWF9DWF9EQkdDX0NGR19E QkdCVVNfQllURUxfMF9CWVRFTDFfX1NISUZUKSAmIEE2WFhfQ1hfREJHQ19DRkdfREJHQlVTX0JZ VEVMXzBfQllURUwxX19NQVNLOworfQorI2RlZmluZSBBNlhYX0NYX0RCR0NfQ0ZHX0RCR0JVU19C WVRFTF8wX0JZVEVMMl9fTUFTSwkJMHgwMDAwMGYwMAorI2RlZmluZSBBNlhYX0NYX0RCR0NfQ0ZH X0RCR0JVU19CWVRFTF8wX0JZVEVMMl9fU0hJRlQJCTgKK3N0YXRpYyBpbmxpbmUgdWludDMyX3Qg QTZYWF9DWF9EQkdDX0NGR19EQkdCVVNfQllURUxfMF9CWVRFTDIodWludDMyX3QgdmFsKQorewor CXJldHVybiAoKHZhbCkgPDwgQTZYWF9DWF9EQkdDX0NGR19EQkdCVVNfQllURUxfMF9CWVRFTDJf X1NISUZUKSAmIEE2WFhfQ1hfREJHQ19DRkdfREJHQlVTX0JZVEVMXzBfQllURUwyX19NQVNLOwor fQorI2RlZmluZSBBNlhYX0NYX0RCR0NfQ0ZHX0RCR0JVU19CWVRFTF8wX0JZVEVMM19fTUFTSwkJ MHgwMDAwZjAwMAorI2RlZmluZSBBNlhYX0NYX0RCR0NfQ0ZHX0RCR0JVU19CWVRFTF8wX0JZVEVM M19fU0hJRlQJCTEyCitzdGF0aWMgaW5saW5lIHVpbnQzMl90IEE2WFhfQ1hfREJHQ19DRkdfREJH QlVTX0JZVEVMXzBfQllURUwzKHVpbnQzMl90IHZhbCkKK3sKKwlyZXR1cm4gKCh2YWwpIDw8IEE2 WFhfQ1hfREJHQ19DRkdfREJHQlVTX0JZVEVMXzBfQllURUwzX19TSElGVCkgJiBBNlhYX0NYX0RC R0NfQ0ZHX0RCR0JVU19CWVRFTF8wX0JZVEVMM19fTUFTSzsKK30KKyNkZWZpbmUgQTZYWF9DWF9E QkdDX0NGR19EQkdCVVNfQllURUxfMF9CWVRFTDRfX01BU0sJCTB4MDAwZjAwMDAKKyNkZWZpbmUg QTZYWF9DWF9EQkdDX0NGR19EQkdCVVNfQllURUxfMF9CWVRFTDRfX1NISUZUCQkxNgorc3RhdGlj IGlubGluZSB1aW50MzJfdCBBNlhYX0NYX0RCR0NfQ0ZHX0RCR0JVU19CWVRFTF8wX0JZVEVMNCh1 aW50MzJfdCB2YWwpCit7CisJcmV0dXJuICgodmFsKSA8PCBBNlhYX0NYX0RCR0NfQ0ZHX0RCR0JV U19CWVRFTF8wX0JZVEVMNF9fU0hJRlQpICYgQTZYWF9DWF9EQkdDX0NGR19EQkdCVVNfQllURUxf MF9CWVRFTDRfX01BU0s7Cit9CisjZGVmaW5lIEE2WFhfQ1hfREJHQ19DRkdfREJHQlVTX0JZVEVM XzBfQllURUw1X19NQVNLCQkweDAwZjAwMDAwCisjZGVmaW5lIEE2WFhfQ1hfREJHQ19DRkdfREJH QlVTX0JZVEVMXzBfQllURUw1X19TSElGVAkJMjAKK3N0YXRpYyBpbmxpbmUgdWludDMyX3QgQTZY WF9DWF9EQkdDX0NGR19EQkdCVVNfQllURUxfMF9CWVRFTDUodWludDMyX3QgdmFsKQoreworCXJl dHVybiAoKHZhbCkgPDwgQTZYWF9DWF9EQkdDX0NGR19EQkdCVVNfQllURUxfMF9CWVRFTDVfX1NI SUZUKSAmIEE2WFhfQ1hfREJHQ19DRkdfREJHQlVTX0JZVEVMXzBfQllURUw1X19NQVNLOworfQor I2RlZmluZSBBNlhYX0NYX0RCR0NfQ0ZHX0RCR0JVU19CWVRFTF8wX0JZVEVMNl9fTUFTSwkJMHgw ZjAwMDAwMAorI2RlZmluZSBBNlhYX0NYX0RCR0NfQ0ZHX0RCR0JVU19CWVRFTF8wX0JZVEVMNl9f U0hJRlQJCTI0CitzdGF0aWMgaW5saW5lIHVpbnQzMl90IEE2WFhfQ1hfREJHQ19DRkdfREJHQlVT X0JZVEVMXzBfQllURUw2KHVpbnQzMl90IHZhbCkKK3sKKwlyZXR1cm4gKCh2YWwpIDw8IEE2WFhf Q1hfREJHQ19DRkdfREJHQlVTX0JZVEVMXzBfQllURUw2X19TSElGVCkgJiBBNlhYX0NYX0RCR0Nf Q0ZHX0RCR0JVU19CWVRFTF8wX0JZVEVMNl9fTUFTSzsKK30KKyNkZWZpbmUgQTZYWF9DWF9EQkdD X0NGR19EQkdCVVNfQllURUxfMF9CWVRFTDdfX01BU0sJCTB4ZjAwMDAwMDAKKyNkZWZpbmUgQTZY WF9DWF9EQkdDX0NGR19EQkdCVVNfQllURUxfMF9CWVRFTDdfX1NISUZUCQkyOAorc3RhdGljIGlu bGluZSB1aW50MzJfdCBBNlhYX0NYX0RCR0NfQ0ZHX0RCR0JVU19CWVRFTF8wX0JZVEVMNyh1aW50 MzJfdCB2YWwpCit7CisJcmV0dXJuICgodmFsKSA8PCBBNlhYX0NYX0RCR0NfQ0ZHX0RCR0JVU19C WVRFTF8wX0JZVEVMN19fU0hJRlQpICYgQTZYWF9DWF9EQkdDX0NGR19EQkdCVVNfQllURUxfMF9C WVRFTDdfX01BU0s7Cit9CisKKyNkZWZpbmUgUkVHX0E2WFhfQ1hfREJHQ19DRkdfREJHQlVTX0JZ VEVMXzEJCQkweDAwMDAwMDExCisjZGVmaW5lIEE2WFhfQ1hfREJHQ19DRkdfREJHQlVTX0JZVEVM XzFfQllURUw4X19NQVNLCQkweDAwMDAwMDBmCisjZGVmaW5lIEE2WFhfQ1hfREJHQ19DRkdfREJH QlVTX0JZVEVMXzFfQllURUw4X19TSElGVAkJMAorc3RhdGljIGlubGluZSB1aW50MzJfdCBBNlhY X0NYX0RCR0NfQ0ZHX0RCR0JVU19CWVRFTF8xX0JZVEVMOCh1aW50MzJfdCB2YWwpCit7CisJcmV0 dXJuICgodmFsKSA8PCBBNlhYX0NYX0RCR0NfQ0ZHX0RCR0JVU19CWVRFTF8xX0JZVEVMOF9fU0hJ RlQpICYgQTZYWF9DWF9EQkdDX0NGR19EQkdCVVNfQllURUxfMV9CWVRFTDhfX01BU0s7Cit9Cisj ZGVmaW5lIEE2WFhfQ1hfREJHQ19DRkdfREJHQlVTX0JZVEVMXzFfQllURUw5X19NQVNLCQkweDAw MDAwMGYwCisjZGVmaW5lIEE2WFhfQ1hfREJHQ19DRkdfREJHQlVTX0JZVEVMXzFfQllURUw5X19T SElGVAkJNAorc3RhdGljIGlubGluZSB1aW50MzJfdCBBNlhYX0NYX0RCR0NfQ0ZHX0RCR0JVU19C WVRFTF8xX0JZVEVMOSh1aW50MzJfdCB2YWwpCit7CisJcmV0dXJuICgodmFsKSA8PCBBNlhYX0NY X0RCR0NfQ0ZHX0RCR0JVU19CWVRFTF8xX0JZVEVMOV9fU0hJRlQpICYgQTZYWF9DWF9EQkdDX0NG R19EQkdCVVNfQllURUxfMV9CWVRFTDlfX01BU0s7Cit9CisjZGVmaW5lIEE2WFhfQ1hfREJHQ19D RkdfREJHQlVTX0JZVEVMXzFfQllURUwxMF9fTUFTSwkJMHgwMDAwMGYwMAorI2RlZmluZSBBNlhY X0NYX0RCR0NfQ0ZHX0RCR0JVU19CWVRFTF8xX0JZVEVMMTBfX1NISUZUCQk4CitzdGF0aWMgaW5s aW5lIHVpbnQzMl90IEE2WFhfQ1hfREJHQ19DRkdfREJHQlVTX0JZVEVMXzFfQllURUwxMCh1aW50 MzJfdCB2YWwpCit7CisJcmV0dXJuICgodmFsKSA8PCBBNlhYX0NYX0RCR0NfQ0ZHX0RCR0JVU19C WVRFTF8xX0JZVEVMMTBfX1NISUZUKSAmIEE2WFhfQ1hfREJHQ19DRkdfREJHQlVTX0JZVEVMXzFf QllURUwxMF9fTUFTSzsKK30KKyNkZWZpbmUgQTZYWF9DWF9EQkdDX0NGR19EQkdCVVNfQllURUxf MV9CWVRFTDExX19NQVNLCQkweDAwMDBmMDAwCisjZGVmaW5lIEE2WFhfQ1hfREJHQ19DRkdfREJH QlVTX0JZVEVMXzFfQllURUwxMV9fU0hJRlQJCTEyCitzdGF0aWMgaW5saW5lIHVpbnQzMl90IEE2 WFhfQ1hfREJHQ19DRkdfREJHQlVTX0JZVEVMXzFfQllURUwxMSh1aW50MzJfdCB2YWwpCit7CisJ cmV0dXJuICgodmFsKSA8PCBBNlhYX0NYX0RCR0NfQ0ZHX0RCR0JVU19CWVRFTF8xX0JZVEVMMTFf X1NISUZUKSAmIEE2WFhfQ1hfREJHQ19DRkdfREJHQlVTX0JZVEVMXzFfQllURUwxMV9fTUFTSzsK K30KKyNkZWZpbmUgQTZYWF9DWF9EQkdDX0NGR19EQkdCVVNfQllURUxfMV9CWVRFTDEyX19NQVNL CQkweDAwMGYwMDAwCisjZGVmaW5lIEE2WFhfQ1hfREJHQ19DRkdfREJHQlVTX0JZVEVMXzFfQllU RUwxMl9fU0hJRlQJCTE2CitzdGF0aWMgaW5saW5lIHVpbnQzMl90IEE2WFhfQ1hfREJHQ19DRkdf REJHQlVTX0JZVEVMXzFfQllURUwxMih1aW50MzJfdCB2YWwpCit7CisJcmV0dXJuICgodmFsKSA8 PCBBNlhYX0NYX0RCR0NfQ0ZHX0RCR0JVU19CWVRFTF8xX0JZVEVMMTJfX1NISUZUKSAmIEE2WFhf Q1hfREJHQ19DRkdfREJHQlVTX0JZVEVMXzFfQllURUwxMl9fTUFTSzsKK30KKyNkZWZpbmUgQTZY WF9DWF9EQkdDX0NGR19EQkdCVVNfQllURUxfMV9CWVRFTDEzX19NQVNLCQkweDAwZjAwMDAwCisj ZGVmaW5lIEE2WFhfQ1hfREJHQ19DRkdfREJHQlVTX0JZVEVMXzFfQllURUwxM19fU0hJRlQJCTIw CitzdGF0aWMgaW5saW5lIHVpbnQzMl90IEE2WFhfQ1hfREJHQ19DRkdfREJHQlVTX0JZVEVMXzFf QllURUwxMyh1aW50MzJfdCB2YWwpCit7CisJcmV0dXJuICgodmFsKSA8PCBBNlhYX0NYX0RCR0Nf Q0ZHX0RCR0JVU19CWVRFTF8xX0JZVEVMMTNfX1NISUZUKSAmIEE2WFhfQ1hfREJHQ19DRkdfREJH QlVTX0JZVEVMXzFfQllURUwxM19fTUFTSzsKK30KKyNkZWZpbmUgQTZYWF9DWF9EQkdDX0NGR19E QkdCVVNfQllURUxfMV9CWVRFTDE0X19NQVNLCQkweDBmMDAwMDAwCisjZGVmaW5lIEE2WFhfQ1hf REJHQ19DRkdfREJHQlVTX0JZVEVMXzFfQllURUwxNF9fU0hJRlQJCTI0CitzdGF0aWMgaW5saW5l IHVpbnQzMl90IEE2WFhfQ1hfREJHQ19DRkdfREJHQlVTX0JZVEVMXzFfQllURUwxNCh1aW50MzJf dCB2YWwpCit7CisJcmV0dXJuICgodmFsKSA8PCBBNlhYX0NYX0RCR0NfQ0ZHX0RCR0JVU19CWVRF TF8xX0JZVEVMMTRfX1NISUZUKSAmIEE2WFhfQ1hfREJHQ19DRkdfREJHQlVTX0JZVEVMXzFfQllU RUwxNF9fTUFTSzsKK30KKyNkZWZpbmUgQTZYWF9DWF9EQkdDX0NGR19EQkdCVVNfQllURUxfMV9C WVRFTDE1X19NQVNLCQkweGYwMDAwMDAwCisjZGVmaW5lIEE2WFhfQ1hfREJHQ19DRkdfREJHQlVT X0JZVEVMXzFfQllURUwxNV9fU0hJRlQJCTI4CitzdGF0aWMgaW5saW5lIHVpbnQzMl90IEE2WFhf Q1hfREJHQ19DRkdfREJHQlVTX0JZVEVMXzFfQllURUwxNSh1aW50MzJfdCB2YWwpCit7CisJcmV0 dXJuICgodmFsKSA8PCBBNlhYX0NYX0RCR0NfQ0ZHX0RCR0JVU19CWVRFTF8xX0JZVEVMMTVfX1NI SUZUKSAmIEE2WFhfQ1hfREJHQ19DRkdfREJHQlVTX0JZVEVMXzFfQllURUwxNV9fTUFTSzsKK30K KworI2RlZmluZSBSRUdfQTZYWF9DWF9EQkdDX0NGR19EQkdCVVNfVFJBQ0VfQlVGMQkJCTB4MDAw MDAwMmYKKworI2RlZmluZSBSRUdfQTZYWF9DWF9EQkdDX0NGR19EQkdCVVNfVFJBQ0VfQlVGMgkJ CTB4MDAwMDAwMzAKKwogCiAjZW5kaWYgLyogQTZYWF9YTUwgKi8KZGlmZiAtLWdpdCBhL2RyaXZl cnMvZ3B1L2RybS9tc20vYWRyZW5vL2E2eHhfZ211LnhtbC5oIGIvZHJpdmVycy9ncHUvZHJtL21z bS9hZHJlbm8vYTZ4eF9nbXUueG1sLmgKaW5kZXggZWY2ODA5OGQyYWRjLi44M2ZmY2NlZjI1MDYg MTAwNjQ0Ci0tLSBhL2RyaXZlcnMvZ3B1L2RybS9tc20vYWRyZW5vL2E2eHhfZ211LnhtbC5oCisr KyBiL2RyaXZlcnMvZ3B1L2RybS9tc20vYWRyZW5vL2E2eHhfZ211LnhtbC5oCkBAIC04LDE3ICs4 LDE3IEBAIFRoaXMgZmlsZSB3YXMgZ2VuZXJhdGVkIGJ5IHRoZSBydWxlcy1uZy1uZyBoZWFkZXJn ZW4gdG9vbCBpbiB0aGlzIGdpdCByZXBvc2l0b3J5CiBnaXQgY2xvbmUgaHR0cHM6Ly9naXRodWIu Y29tL2ZyZWVkcmVuby9lbnZ5dG9vbHMuZ2l0CiAKIFRoZSBydWxlcy1uZy1uZyBzb3VyY2UgZmls ZXMgdGhpcyBoZWFkZXIgd2FzIGdlbmVyYXRlZCBmcm9tIGFyZToKLS0gL2hvbWUvcm9iY2xhcmsv c3JjL2Vudnl0b29scy9ybm5kYi9hZHJlbm8ueG1sICAgICAgICAgICAgICAgKCAgICA1MDEgYnl0 ZXMsIGZyb20gMjAxOC0wNy0wMyAxOTozNzoxMykKLS0gL2hvbWUvcm9iY2xhcmsvc3JjL2Vudnl0 b29scy9ybm5kYi9mcmVlZHJlbm9fY29weXJpZ2h0LnhtbCAgKCAgIDE1NzIgYnl0ZXMsIGZyb20g MjAxOC0wNy0wMyAxOTozNzoxMykKLS0gL2hvbWUvcm9iY2xhcmsvc3JjL2Vudnl0b29scy9ybm5k Yi9hZHJlbm8vYTJ4eC54bWwgICAgICAgICAgKCAgMzY4MDUgYnl0ZXMsIGZyb20gMjAxOC0wNy0w MyAxOTozNzoxMykKLS0gL2hvbWUvcm9iY2xhcmsvc3JjL2Vudnl0b29scy9ybm5kYi9hZHJlbm8v YWRyZW5vX2NvbW1vbi54bWwgKCAgMTM2MzQgYnl0ZXMsIGZyb20gMjAxOC0wNy0wMyAxOTozNzox MykKLS0gL2hvbWUvcm9iY2xhcmsvc3JjL2Vudnl0b29scy9ybm5kYi9hZHJlbm8vYWRyZW5vX3Bt NC54bWwgICAgKCAgNDIzOTMgYnl0ZXMsIGZyb20gMjAxOC0wOC0wNiAxODo0NTo0NSkKLS0gL2hv bWUvcm9iY2xhcmsvc3JjL2Vudnl0b29scy9ybm5kYi9hZHJlbm8vYTN4eC54bWwgICAgICAgICAg KCAgODM4NDAgYnl0ZXMsIGZyb20gMjAxOC0wNy0wMyAxOTozNzoxMykKLS0gL2hvbWUvcm9iY2xh cmsvc3JjL2Vudnl0b29scy9ybm5kYi9hZHJlbm8vYTR4eC54bWwgICAgICAgICAgKCAxMTIwODYg Ynl0ZXMsIGZyb20gMjAxOC0wNy0wMyAxOTozNzoxMykKLS0gL2hvbWUvcm9iY2xhcmsvc3JjL2Vu dnl0b29scy9ybm5kYi9hZHJlbm8vYTV4eC54bWwgICAgICAgICAgKCAxNDcyNDAgYnl0ZXMsIGZy b20gMjAxOC0wOC0wNiAxODo0NTo0NSkKLS0gL2hvbWUvcm9iY2xhcmsvc3JjL2Vudnl0b29scy9y bm5kYi9hZHJlbm8vYTZ4eC54bWwgICAgICAgICAgKCAxMDE2MjcgYnl0ZXMsIGZyb20gMjAxOC0w OC0wNiAxODo0NTo0NSkKLS0gL2hvbWUvcm9iY2xhcmsvc3JjL2Vudnl0b29scy9ybm5kYi9hZHJl bm8vYTZ4eF9nbXUueG1sICAgICAgKCAgMTA0MzEgYnl0ZXMsIGZyb20gMjAxOC0wNy0wMyAxOToz NzoxMykKLS0gL2hvbWUvcm9iY2xhcmsvc3JjL2Vudnl0b29scy9ybm5kYi9hZHJlbm8vb2NtZW0u eG1sICAgICAgICAgKCAgIDE3NzMgYnl0ZXMsIGZyb20gMjAxOC0wNy0wMyAxOTozNzoxMykKKy0g Li9hZHJlbm8ueG1sICAgICAgICAgICAgICAgKCAgICA1MDEgYnl0ZXMsIGZyb20gMjAxOC0wNS0y MyAxNjo1MTo1NykKKy0gLi9mcmVlZHJlbm9fY29weXJpZ2h0LnhtbCAgKCAgIDE1NzIgYnl0ZXMs IGZyb20gMjAxNi0xMC0yNCAyMToxMjoyNykKKy0gLi9hZHJlbm8vYTJ4eC54bWwgICAgICAgICAg KCAgMzY4MDUgYnl0ZXMsIGZyb20gMjAxOC0wNS0yMyAxNjo1MTo1NykKKy0gLi9hZHJlbm8vYWRy ZW5vX2NvbW1vbi54bWwgKCAgMTM2MzQgYnl0ZXMsIGZyb20gMjAxOC0wNS0yMyAxNjo1MTo1NykK Ky0gLi9hZHJlbm8vYWRyZW5vX3BtNC54bWwgICAgKCAgNDIzOTMgYnl0ZXMsIGZyb20gMjAxOC0w OC0xNiAxNjo1NjoxNCkKKy0gLi9hZHJlbm8vYTN4eC54bWwgICAgICAgICAgKCAgODM4NDAgYnl0 ZXMsIGZyb20gMjAxNy0xMi0wNSAxODoyMDoyNykKKy0gLi9hZHJlbm8vYTR4eC54bWwgICAgICAg ICAgKCAxMTIwODYgYnl0ZXMsIGZyb20gMjAxOC0wNS0yMyAxNjo1MTo1NykKKy0gLi9hZHJlbm8v YTV4eC54bWwgICAgICAgICAgKCAxNDcyNDAgYnl0ZXMsIGZyb20gMjAxOC0wOC0xNiAxNjo1Njox NCkKKy0gLi9hZHJlbm8vYTZ4eC54bWwgICAgICAgICAgKCAxMDc1NzAgYnl0ZXMsIGZyb20gMjAx OC0wOC0xNiAxNzozMjoxOCkKKy0gLi9hZHJlbm8vYTZ4eF9nbXUueG1sICAgICAgKCAgMTA0MzEg Ynl0ZXMsIGZyb20gMjAxOC0wOC0xNiAxNzozNTo1NSkKKy0gLi9hZHJlbm8vb2NtZW0ueG1sICAg ICAgICAgKCAgIDE3NzMgYnl0ZXMsIGZyb20gMjAxNi0xMC0yNCAyMToxMjoyNykKIAogQ29weXJp Z2h0IChDKSAyMDEzLTIwMTggYnkgdGhlIGZvbGxvd2luZyBhdXRob3JzOgogLSBSb2IgQ2xhcmsg PHJvYmRjbGFya0BnbWFpbC5jb20+IChyb2JjbGFyaykKQEAgLTE2Nyw4ICsxNjcsOCBAQCBzdGF0 aWMgaW5saW5lIHVpbnQzMl90IEE2WFhfR01VX1BXUl9DT0xfSU5URVJfRlJBTUVfQ1RSTF9NSU5f UEFTU19MRU5HVEgodWludDMyXwogI2RlZmluZSBSRUdfQTZYWF9HTVVfU1BUUFJBQ19QV1JfQ0xL X1NUQVRVUwkJCTB4MDAwMDUwZDAKICNkZWZpbmUgQTZYWF9HTVVfU1BUUFJBQ19QV1JfQ0xLX1NU QVRVU19TUFRQUkFDX0dEU0NfUE9XRVJJTkdfT0ZGCTB4MDAwMDAwMDEKICNkZWZpbmUgQTZYWF9H TVVfU1BUUFJBQ19QV1JfQ0xLX1NUQVRVU19TUFRQUkFDX0dEU0NfUE9XRVJJTkdfT04JMHgwMDAw MDAwMgotI2RlZmluZSBBNlhYX0dNVV9TUFRQUkFDX1BXUl9DTEtfU1RBVFVTX1NQVFBSQUNfR0RT Q19QT1dFUl9PTgkweDAwMDAwMDA0Ci0jZGVmaW5lIEE2WFhfR01VX1NQVFBSQUNfUFdSX0NMS19T VEFUVVNfU1BUUFJBQ19HRFNDX1BPV0VSX09GRgkweDAwMDAwMDA4CisjZGVmaW5lIEE2WFhfR01V X1NQVFBSQUNfUFdSX0NMS19TVEFUVVNfU1BUUFJBQ19HRFNDX1BPV0VSX09GRgkweDAwMDAwMDA0 CisjZGVmaW5lIEE2WFhfR01VX1NQVFBSQUNfUFdSX0NMS19TVEFUVVNfU1BUUFJBQ19HRFNDX1BP V0VSX09OCTB4MDAwMDAwMDgKICNkZWZpbmUgQTZYWF9HTVVfU1BUUFJBQ19QV1JfQ0xLX1NUQVRV U19TUF9DTE9DS19PRkYJCTB4MDAwMDAwMTAKICNkZWZpbmUgQTZYWF9HTVVfU1BUUFJBQ19QV1Jf Q0xLX1NUQVRVU19HTVVfVVBfUE9XRVJfU1RBVEUJMHgwMDAwMDAyMAogI2RlZmluZSBBNlhYX0dN VV9TUFRQUkFDX1BXUl9DTEtfU1RBVFVTX0dYX0hNX0dEU0NfUE9XRVJfT0ZGCTB4MDAwMDAwNDAK LS0gCjIuMTguMAoKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X18KRnJlZWRyZW5vIG1haWxpbmcgbGlzdApGcmVlZHJlbm9AbGlzdHMuZnJlZWRlc2t0b3Aub3Jn Cmh0dHBzOi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vZnJlZWRyZW5v Cg== From mboxrd@z Thu Jan 1 00:00:00 1970 From: jcrouse@codeaurora.org (Jordan Crouse) Date: Mon, 27 Aug 2018 09:11:04 -0600 Subject: [PATCH 1/9] drm/msm/a6xx: rnndb updates for a6xx In-Reply-To: <20180827151112.25211-1-jcrouse@codeaurora.org> References: <20180827151112.25211-1-jcrouse@codeaurora.org> Message-ID: <20180827151112.25211-2-jcrouse@codeaurora.org> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Update the register definitions for a6xx from the rnndb database. Changes include new enums for upcoming devcoredump support, moving the PDC and GCC_GX register definitions to their own domain and various other register updates and additions. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/a6xx.xml.h | 642 ++++++++++++++-------- drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h | 26 +- 2 files changed, 416 insertions(+), 252 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx.xml.h b/drivers/gpu/drm/msm/adreno/a6xx.xml.h index 87eab51f7000..7acc57b2c1be 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx.xml.h +++ b/drivers/gpu/drm/msm/adreno/a6xx.xml.h @@ -8,17 +8,17 @@ This file was generated by the rules-ng-ng headergen tool in this git repository git clone https://github.com/freedreno/envytools.git The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13) -- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13) -- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 36805 bytes, from 2018-07-03 19:37:13) -- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 13634 bytes, from 2018-07-03 19:37:13) -- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 42393 bytes, from 2018-08-06 18:45:45) -- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13) -- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13) -- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-08-06 18:45:45) -- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 101627 bytes, from 2018-08-06 18:45:45) -- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-07-03 19:37:13) -- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13) +- ./adreno.xml ( 501 bytes, from 2018-05-23 16:51:57) +- ./freedreno_copyright.xml ( 1572 bytes, from 2016-10-24 21:12:27) +- ./adreno/a2xx.xml ( 36805 bytes, from 2018-05-23 16:51:57) +- ./adreno/adreno_common.xml ( 13634 bytes, from 2018-05-23 16:51:57) +- ./adreno/adreno_pm4.xml ( 42393 bytes, from 2018-08-16 16:56:14) +- ./adreno/a3xx.xml ( 83840 bytes, from 2017-12-05 18:20:27) +- ./adreno/a4xx.xml ( 112086 bytes, from 2018-05-23 16:51:57) +- ./adreno/a5xx.xml ( 147240 bytes, from 2018-08-16 16:56:14) +- ./adreno/a6xx.xml ( 107521 bytes, from 2018-08-16 17:44:50) +- ./adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-08-16 17:44:26) +- ./adreno/ocmem.xml ( 1773 bytes, from 2016-10-24 21:12:27) Copyright (C) 2013-2018 by the following authors: - Rob Clark (robclark) @@ -272,6 +272,98 @@ enum a6xx_cp_perfcounter_select { PERF_CP_ALWAYS_COUNT = 0, }; +enum a6xx_shader_id { + A6XX_TP0_TMO_DATA = 9, + A6XX_TP0_SMO_DATA = 10, + A6XX_TP0_MIPMAP_BASE_DATA = 11, + A6XX_TP1_TMO_DATA = 25, + A6XX_TP1_SMO_DATA = 26, + A6XX_TP1_MIPMAP_BASE_DATA = 27, + A6XX_SP_INST_DATA = 41, + A6XX_SP_LB_0_DATA = 42, + A6XX_SP_LB_1_DATA = 43, + A6XX_SP_LB_2_DATA = 44, + A6XX_SP_LB_3_DATA = 45, + A6XX_SP_LB_4_DATA = 46, + A6XX_SP_LB_5_DATA = 47, + A6XX_SP_CB_BINDLESS_DATA = 48, + A6XX_SP_CB_LEGACY_DATA = 49, + A6XX_SP_UAV_DATA = 50, + A6XX_SP_INST_TAG = 51, + A6XX_SP_CB_BINDLESS_TAG = 52, + A6XX_SP_TMO_UMO_TAG = 53, + A6XX_SP_SMO_TAG = 54, + A6XX_SP_STATE_DATA = 55, + A6XX_HLSQ_CHUNK_CVS_RAM = 73, + A6XX_HLSQ_CHUNK_CPS_RAM = 74, + A6XX_HLSQ_CHUNK_CVS_RAM_TAG = 75, + A6XX_HLSQ_CHUNK_CPS_RAM_TAG = 76, + A6XX_HLSQ_ICB_CVS_CB_BASE_TAG = 77, + A6XX_HLSQ_ICB_CPS_CB_BASE_TAG = 78, + A6XX_HLSQ_CVS_MISC_RAM = 80, + A6XX_HLSQ_CPS_MISC_RAM = 81, + A6XX_HLSQ_INST_RAM = 82, + A6XX_HLSQ_GFX_CVS_CONST_RAM = 83, + A6XX_HLSQ_GFX_CPS_CONST_RAM = 84, + A6XX_HLSQ_CVS_MISC_RAM_TAG = 85, + A6XX_HLSQ_CPS_MISC_RAM_TAG = 86, + A6XX_HLSQ_INST_RAM_TAG = 87, + A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG = 88, + A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG = 89, + A6XX_HLSQ_PWR_REST_RAM = 90, + A6XX_HLSQ_PWR_REST_TAG = 91, + A6XX_HLSQ_DATAPATH_META = 96, + A6XX_HLSQ_FRONTEND_META = 97, + A6XX_HLSQ_INDIRECT_META = 98, + A6XX_HLSQ_BACKEND_META = 99, +}; + +enum a6xx_debugbus_id { + A6XX_DBGBUS_CP = 1, + A6XX_DBGBUS_RBBM = 2, + A6XX_DBGBUS_VBIF = 3, + A6XX_DBGBUS_HLSQ = 4, + A6XX_DBGBUS_UCHE = 5, + A6XX_DBGBUS_DPM = 6, + A6XX_DBGBUS_TESS = 7, + A6XX_DBGBUS_PC = 8, + A6XX_DBGBUS_VFDP = 9, + A6XX_DBGBUS_VPC = 10, + A6XX_DBGBUS_TSE = 11, + A6XX_DBGBUS_RAS = 12, + A6XX_DBGBUS_VSC = 13, + A6XX_DBGBUS_COM = 14, + A6XX_DBGBUS_LRZ = 16, + A6XX_DBGBUS_A2D = 17, + A6XX_DBGBUS_CCUFCHE = 18, + A6XX_DBGBUS_GMU_CX = 19, + A6XX_DBGBUS_RBP = 20, + A6XX_DBGBUS_DCS = 21, + A6XX_DBGBUS_DBGC = 22, + A6XX_DBGBUS_CX = 23, + A6XX_DBGBUS_GMU_GX = 24, + A6XX_DBGBUS_TPFCHE = 25, + A6XX_DBGBUS_GBIF_GX = 26, + A6XX_DBGBUS_GPC = 29, + A6XX_DBGBUS_LARC = 30, + A6XX_DBGBUS_HLSQ_SPTP = 31, + A6XX_DBGBUS_RB_0 = 32, + A6XX_DBGBUS_RB_1 = 33, + A6XX_DBGBUS_UCHE_WRAPPER = 36, + A6XX_DBGBUS_CCU_0 = 40, + A6XX_DBGBUS_CCU_1 = 41, + A6XX_DBGBUS_VFD_0 = 56, + A6XX_DBGBUS_VFD_1 = 57, + A6XX_DBGBUS_VFD_2 = 58, + A6XX_DBGBUS_VFD_3 = 59, + A6XX_DBGBUS_SP_0 = 64, + A6XX_DBGBUS_SP_1 = 65, + A6XX_DBGBUS_TPL1_0 = 72, + A6XX_DBGBUS_TPL1_1 = 73, + A6XX_DBGBUS_TPL1_2 = 74, + A6XX_DBGBUS_TPL1_3 = 75, +}; + enum a6xx_tex_filter { A6XX_TEX_NEAREST = 0, A6XX_TEX_LINEAR = 1, @@ -1765,12 +1857,39 @@ static inline uint32_t A6XX_UCHE_CLIENT_PF_PERFSEL(uint32_t val) #define REG_A6XX_VBIF_VERSION 0x00003000 +#define REG_A6XX_VBIF_CLKON 0x00003001 +#define A6XX_VBIF_CLKON_FORCE_ON_TESTBUS 0x00000002 + #define REG_A6XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a #define REG_A6XX_VBIF_XIN_HALT_CTRL0 0x00003080 #define REG_A6XX_VBIF_XIN_HALT_CTRL1 0x00003081 +#define REG_A6XX_VBIF_TEST_BUS_OUT_CTRL 0x00003084 + +#define REG_A6XX_VBIF_TEST_BUS1_CTRL0 0x00003085 + +#define REG_A6XX_VBIF_TEST_BUS1_CTRL1 0x00003086 +#define A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK 0x0000000f +#define A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT 0 +static inline uint32_t A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL(uint32_t val) +{ + return ((val) << A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT) & A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK; +} + +#define REG_A6XX_VBIF_TEST_BUS2_CTRL0 0x00003087 + +#define REG_A6XX_VBIF_TEST_BUS2_CTRL1 0x00003088 +#define A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK 0x000001ff +#define A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT 0 +static inline uint32_t A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL(uint32_t val) +{ + return ((val) << A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT) & A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK; +} + +#define REG_A6XX_VBIF_TEST_BUS_OUT 0x0000308c + #define REG_A6XX_VBIF_PERF_CNT_SEL0 0x000030d0 #define REG_A6XX_VBIF_PERF_CNT_SEL1 0x000030d1 @@ -1813,228 +1932,6 @@ static inline uint32_t A6XX_UCHE_CLIENT_PF_PERFSEL(uint32_t val) #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH2 0x0000311a -#define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_A 0x00018400 - -#define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_B 0x00018401 - -#define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_C 0x00018402 - -#define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_D 0x00018403 -#define A6XX_CX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK 0x000000ff -#define A6XX_CX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT 0 -static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX(uint32_t val) -{ - return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK; -} -#define A6XX_CX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK 0x0000ff00 -#define A6XX_CX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT 8 -static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL(uint32_t val) -{ - return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK; -} - -#define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLT 0x00018404 -#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK 0x0000003f -#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT 0 -static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val) -{ - return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK; -} -#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK 0x00007000 -#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT 12 -static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val) -{ - return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK; -} -#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK 0xf0000000 -#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT 28 -static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val) -{ - return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK; -} - -#define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLM 0x00018405 -#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK 0x0f000000 -#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT 24 -static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val) -{ - return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK; -} - -#define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_0 0x00018408 - -#define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_1 0x00018409 - -#define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_2 0x0001840a - -#define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_3 0x0001840b - -#define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_0 0x0001840c - -#define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_1 0x0001840d - -#define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_2 0x0001840e - -#define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_3 0x0001840f - -#define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0 0x00018410 -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK 0x0000000f -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT 0 -static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val) -{ - return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK; -} -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK 0x000000f0 -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT 4 -static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val) -{ - return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK; -} -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK 0x00000f00 -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT 8 -static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val) -{ - return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK; -} -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK 0x0000f000 -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT 12 -static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val) -{ - return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK; -} -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK 0x000f0000 -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT 16 -static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val) -{ - return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK; -} -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK 0x00f00000 -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT 20 -static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val) -{ - return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK; -} -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK 0x0f000000 -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT 24 -static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val) -{ - return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK; -} -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK 0xf0000000 -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT 28 -static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val) -{ - return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK; -} - -#define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1 0x00018411 -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK 0x0000000f -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT 0 -static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val) -{ - return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK; -} -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK 0x000000f0 -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT 4 -static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val) -{ - return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK; -} -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK 0x00000f00 -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT 8 -static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val) -{ - return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK; -} -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK 0x0000f000 -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT 12 -static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val) -{ - return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK; -} -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK 0x000f0000 -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT 16 -static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val) -{ - return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK; -} -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK 0x00f00000 -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT 20 -static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val) -{ - return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK; -} -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK 0x0f000000 -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT 24 -static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val) -{ - return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK; -} -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK 0xf0000000 -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT 28 -static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val) -{ - return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK; -} - -#define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF1 0x0001842f - -#define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF2 0x00018430 - -#define REG_A6XX_PDC_GPU_ENABLE_PDC 0x00021140 - -#define REG_A6XX_PDC_GPU_SEQ_START_ADDR 0x00021148 - -#define REG_A6XX_PDC_GPU_TCS0_CONTROL 0x00021540 - -#define REG_A6XX_PDC_GPU_TCS0_CMD_ENABLE_BANK 0x00021541 - -#define REG_A6XX_PDC_GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK 0x00021542 - -#define REG_A6XX_PDC_GPU_TCS0_CMD0_MSGID 0x00021543 - -#define REG_A6XX_PDC_GPU_TCS0_CMD0_ADDR 0x00021544 - -#define REG_A6XX_PDC_GPU_TCS0_CMD0_DATA 0x00021545 - -#define REG_A6XX_PDC_GPU_TCS1_CONTROL 0x00021572 - -#define REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK 0x00021573 - -#define REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK 0x00021574 - -#define REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID 0x00021575 - -#define REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR 0x00021576 - -#define REG_A6XX_PDC_GPU_TCS1_CMD0_DATA 0x00021577 - -#define REG_A6XX_PDC_GPU_TCS2_CONTROL 0x000215a4 - -#define REG_A6XX_PDC_GPU_TCS2_CMD_ENABLE_BANK 0x000215a5 - -#define REG_A6XX_PDC_GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK 0x000215a6 - -#define REG_A6XX_PDC_GPU_TCS2_CMD0_MSGID 0x000215a7 - -#define REG_A6XX_PDC_GPU_TCS2_CMD0_ADDR 0x000215a8 - -#define REG_A6XX_PDC_GPU_TCS2_CMD0_DATA 0x000215a9 - -#define REG_A6XX_PDC_GPU_TCS3_CONTROL 0x000215d6 - -#define REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK 0x000215d7 - -#define REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK 0x000215d8 - -#define REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID 0x000215d9 - -#define REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR 0x000215da - -#define REG_A6XX_PDC_GPU_TCS3_CMD0_DATA 0x000215db - -#define REG_A6XX_PDC_GPU_SEQ_MEM_0 0x000a0000 - #define REG_A6XX_X1_WINDOW_OFFSET 0x000088d4 #define A6XX_X1_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000 #define A6XX_X1_WINDOW_OFFSET_X__MASK 0x00007fff @@ -2200,6 +2097,8 @@ static inline uint32_t REG_A6XX_VSC_SIZE_REG(uint32_t i0) { return 0x00000c78 + #define REG_A6XX_UCHE_UNKNOWN_0E12 0x00000e12 +#define REG_A6XX_GRAS_UNKNOWN_8000 0x00008000 + #define REG_A6XX_GRAS_UNKNOWN_8001 0x00008001 #define REG_A6XX_GRAS_UNKNOWN_8004 0x00008004 @@ -2344,6 +2243,8 @@ static inline uint32_t A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_dep #define REG_A6XX_GRAS_UNKNOWN_809B 0x0000809b +#define REG_A6XX_GRAS_UNKNOWN_80A0 0x000080a0 + #define REG_A6XX_GRAS_RAS_MSAA_CNTL 0x000080a2 #define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003 #define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT 0 @@ -2464,6 +2365,8 @@ static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) #define A6XX_GRAS_LRZ_CNTL_LRZ_WRITE 0x00000002 #define A6XX_GRAS_LRZ_CNTL_GREATER 0x00000004 +#define REG_A6XX_GRAS_UNKNOWN_8101 0x00008101 + #define REG_A6XX_GRAS_2D_BLIT_INFO 0x00008102 #define A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__MASK 0x000000ff #define A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__SHIFT 0 @@ -2494,6 +2397,10 @@ static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) #define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI 0x00008107 +#define REG_A6XX_GRAS_UNKNOWN_8109 0x00008109 + +#define REG_A6XX_GRAS_UNKNOWN_8110 0x00008110 + #define REG_A6XX_GRAS_2D_BLIT_CNTL 0x00008400 #define REG_A6XX_GRAS_2D_SRC_TL_X 0x00008401 @@ -2747,6 +2654,10 @@ static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7(enum adreno_rb_dithe #define A6XX_RB_SRGB_CNTL_SRGB_MRT6 0x00000040 #define A6XX_RB_SRGB_CNTL_SRGB_MRT7 0x00000080 +#define REG_A6XX_RB_UNKNOWN_8810 0x00008810 + +#define REG_A6XX_RB_UNKNOWN_8811 0x00008811 + #define REG_A6XX_RB_UNKNOWN_8818 0x00008818 #define REG_A6XX_RB_UNKNOWN_8819 0x00008819 @@ -3177,14 +3088,14 @@ static inline uint32_t A6XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val) #define REG_A6XX_RB_BLIT_INFO 0x000088e3 #define A6XX_RB_BLIT_INFO_UNK0 0x00000001 -#define A6XX_RB_BLIT_INFO_FAST_CLEAR 0x00000002 +#define A6XX_RB_BLIT_INFO_GMEM 0x00000002 #define A6XX_RB_BLIT_INFO_INTEGER 0x00000004 -#define A6XX_RB_BLIT_INFO_UNK3 0x00000008 -#define A6XX_RB_BLIT_INFO_MASK__MASK 0x000000f0 -#define A6XX_RB_BLIT_INFO_MASK__SHIFT 4 -static inline uint32_t A6XX_RB_BLIT_INFO_MASK(uint32_t val) +#define A6XX_RB_BLIT_INFO_DEPTH 0x00000008 +#define A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK 0x000000f0 +#define A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT 4 +static inline uint32_t A6XX_RB_BLIT_INFO_CLEAR_MASK(uint32_t val) { - return ((val) << A6XX_RB_BLIT_INFO_MASK__SHIFT) & A6XX_RB_BLIT_INFO_MASK__MASK; + return ((val) << A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT) & A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK; } #define REG_A6XX_RB_UNKNOWN_88F0 0x000088f0 @@ -3274,12 +3185,16 @@ static inline uint32_t A6XX_RB_2D_DST_SIZE_PITCH(uint32_t val) #define REG_A6XX_RB_UNKNOWN_8E01 0x00008e01 +#define REG_A6XX_RB_UNKNOWN_8E04 0x00008e04 + #define REG_A6XX_RB_CCU_CNTL 0x00008e07 #define REG_A6XX_VPC_UNKNOWN_9101 0x00009101 #define REG_A6XX_VPC_GS_SIV_CNTL 0x00009104 +#define REG_A6XX_VPC_UNKNOWN_9107 0x00009107 + #define REG_A6XX_VPC_UNKNOWN_9108 0x00009108 static inline uint32_t REG_A6XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00009200 + 0x1*i0; } @@ -3385,6 +3300,8 @@ static inline uint32_t A6XX_VPC_CNTL_0_NUMNONPOSVAR(uint32_t val) #define A6XX_VPC_SO_BUF_CNTL_BUF3 0x00000200 #define A6XX_VPC_SO_BUF_CNTL_ENABLE 0x00008000 +#define REG_A6XX_VPC_UNKNOWN_9306 0x00009306 + #define REG_A6XX_VPC_UNKNOWN_9600 0x00009600 #define REG_A6XX_VPC_UNKNOWN_9602 0x00009602 @@ -3397,8 +3314,14 @@ static inline uint32_t A6XX_VPC_CNTL_0_NUMNONPOSVAR(uint32_t val) #define REG_A6XX_PC_UNKNOWN_9805 0x00009805 +#define REG_A6XX_PC_UNKNOWN_9806 0x00009806 + +#define REG_A6XX_PC_UNKNOWN_9980 0x00009980 + #define REG_A6XX_PC_UNKNOWN_9981 0x00009981 +#define REG_A6XX_PC_UNKNOWN_9990 0x00009990 + #define REG_A6XX_PC_PRIMITIVE_CNTL_0 0x00009b00 #define A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART 0x00000001 #define A6XX_PC_PRIMITIVE_CNTL_0_PROVOKING_VTX_LAST 0x00000002 @@ -3410,6 +3333,7 @@ static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(uint32_t val) { return ((val) << A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC__MASK; } +#define A6XX_PC_PRIMITIVE_CNTL_1_PSIZE 0x00000100 #define REG_A6XX_PC_UNKNOWN_9B06 0x00009b06 @@ -3488,6 +3412,8 @@ static inline uint32_t A6XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val) #define REG_A6XX_VFD_UNKNOWN_A008 0x0000a008 +#define REG_A6XX_VFD_UNKNOWN_A009 0x0000a009 + #define REG_A6XX_VFD_INDEX_OFFSET 0x0000a00e #define REG_A6XX_VFD_INSTANCE_START_OFFSET 0x0000a00f @@ -3640,6 +3566,8 @@ static inline uint32_t A6XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) #define A6XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x04000000 #define A6XX_SP_VS_CTRL_REG0_MERGEDREGS 0x80000000 +#define REG_A6XX_SP_UNKNOWN_A81B 0x0000a81b + #define REG_A6XX_SP_VS_OBJ_START_LO 0x0000a81c #define REG_A6XX_SP_VS_OBJ_START_HI 0x0000a81d @@ -3884,6 +3812,8 @@ static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) #define A6XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x04000000 #define A6XX_SP_FS_CTRL_REG0_MERGEDREGS 0x80000000 +#define REG_A6XX_SP_UNKNOWN_A982 0x0000a982 + #define REG_A6XX_SP_FS_OBJ_START_LO 0x0000a983 #define REG_A6XX_SP_FS_OBJ_START_HI 0x0000a984 @@ -3981,6 +3911,8 @@ static inline uint32_t A6XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a6xx_color_fmt val) #define A6XX_SP_FS_MRT_REG_COLOR_UINT 0x00000200 #define A6XX_SP_FS_MRT_REG_COLOR_SRGB 0x00000400 +#define REG_A6XX_SP_UNKNOWN_A99E 0x0000a99e + #define REG_A6XX_SP_FS_TEX_COUNT 0x0000a9a7 #define REG_A6XX_SP_UNKNOWN_A9A8 0x0000a9a8 @@ -4066,14 +3998,20 @@ static inline uint32_t A6XX_SP_FS_CONFIG_NSAMP(uint32_t val) #define REG_A6XX_SP_FS_INSTRLEN 0x0000ab05 +#define REG_A6XX_SP_UNKNOWN_AB20 0x0000ab20 + #define REG_A6XX_SP_UNKNOWN_AE00 0x0000ae00 +#define REG_A6XX_SP_UNKNOWN_AE03 0x0000ae03 + #define REG_A6XX_SP_UNKNOWN_AE04 0x0000ae04 #define REG_A6XX_SP_UNKNOWN_AE0F 0x0000ae0f #define REG_A6XX_SP_UNKNOWN_B182 0x0000b182 +#define REG_A6XX_SP_UNKNOWN_B183 0x0000b183 + #define REG_A6XX_SP_TP_RAS_MSAA_CNTL 0x0000b300 #define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003 #define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT 0 @@ -4097,6 +4035,8 @@ static inline uint32_t A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples #define REG_A6XX_SP_TP_UNKNOWN_B304 0x0000b304 +#define REG_A6XX_SP_TP_UNKNOWN_B309 0x0000b309 + #define REG_A6XX_SP_PS_2D_SRC_INFO 0x0000b4c0 #define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff #define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0 @@ -4162,6 +4102,8 @@ static inline uint32_t A6XX_HLSQ_GS_CNTL_CONSTLEN(uint32_t val) return ((val >> 2) << A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK; } +#define REG_A6XX_HLSQ_UNKNOWN_B980 0x0000b980 + #define REG_A6XX_HLSQ_CONTROL_1_REG 0x0000b982 #define REG_A6XX_HLSQ_CONTROL_2_REG 0x0000b983 @@ -4558,5 +4500,227 @@ static inline uint32_t A6XX_TEX_CONST_8_BASE_HI(uint32_t val) #define REG_A6XX_TEX_CONST_15 0x0000000f +#define REG_A6XX_PDC_GPU_ENABLE_PDC 0x00001140 + +#define REG_A6XX_PDC_GPU_SEQ_START_ADDR 0x00001148 + +#define REG_A6XX_PDC_GPU_TCS0_CONTROL 0x00001540 + +#define REG_A6XX_PDC_GPU_TCS0_CMD_ENABLE_BANK 0x00001541 + +#define REG_A6XX_PDC_GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK 0x00001542 + +#define REG_A6XX_PDC_GPU_TCS0_CMD0_MSGID 0x00001543 + +#define REG_A6XX_PDC_GPU_TCS0_CMD0_ADDR 0x00001544 + +#define REG_A6XX_PDC_GPU_TCS0_CMD0_DATA 0x00001545 + +#define REG_A6XX_PDC_GPU_TCS1_CONTROL 0x00001572 + +#define REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK 0x00001573 + +#define REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK 0x00001574 + +#define REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID 0x00001575 + +#define REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR 0x00001576 + +#define REG_A6XX_PDC_GPU_TCS1_CMD0_DATA 0x00001577 + +#define REG_A6XX_PDC_GPU_TCS2_CONTROL 0x000015a4 + +#define REG_A6XX_PDC_GPU_TCS2_CMD_ENABLE_BANK 0x000015a5 + +#define REG_A6XX_PDC_GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK 0x000015a6 + +#define REG_A6XX_PDC_GPU_TCS2_CMD0_MSGID 0x000015a7 + +#define REG_A6XX_PDC_GPU_TCS2_CMD0_ADDR 0x000015a8 + +#define REG_A6XX_PDC_GPU_TCS2_CMD0_DATA 0x000015a9 + +#define REG_A6XX_PDC_GPU_TCS3_CONTROL 0x000015d6 + +#define REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK 0x000015d7 + +#define REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK 0x000015d8 + +#define REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID 0x000015d9 + +#define REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR 0x000015da + +#define REG_A6XX_PDC_GPU_TCS3_CMD0_DATA 0x000015db + +#define REG_A6XX_PDC_GPU_SEQ_MEM_0 0x00000000 + +#define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_A 0x00000000 +#define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK 0x000000ff +#define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT 0 +static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX(uint32_t val) +{ + return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK; +} +#define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK 0x0000ff00 +#define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT 8 +static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL(uint32_t val) +{ + return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK; +} + +#define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_B 0x00000001 + +#define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_C 0x00000002 + +#define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_D 0x00000003 + +#define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLT 0x00000004 +#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK 0x0000003f +#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT 0 +static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val) +{ + return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK; +} +#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK 0x00007000 +#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT 12 +static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val) +{ + return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK; +} +#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK 0xf0000000 +#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT 28 +static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val) +{ + return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK; +} + +#define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLM 0x00000005 +#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK 0x0f000000 +#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT 24 +static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val) +{ + return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK; +} + +#define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_0 0x00000008 + +#define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_1 0x00000009 + +#define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_2 0x0000000a + +#define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_3 0x0000000b + +#define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_0 0x0000000c + +#define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_1 0x0000000d + +#define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_2 0x0000000e + +#define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_3 0x0000000f + +#define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0 0x00000010 +#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK 0x0000000f +#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT 0 +static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val) +{ + return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK; +} +#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK 0x000000f0 +#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT 4 +static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val) +{ + return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK; +} +#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK 0x00000f00 +#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT 8 +static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val) +{ + return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK; +} +#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK 0x0000f000 +#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT 12 +static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val) +{ + return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK; +} +#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK 0x000f0000 +#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT 16 +static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val) +{ + return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK; +} +#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK 0x00f00000 +#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT 20 +static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val) +{ + return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK; +} +#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK 0x0f000000 +#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT 24 +static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val) +{ + return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK; +} +#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK 0xf0000000 +#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT 28 +static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val) +{ + return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK; +} + +#define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1 0x00000011 +#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK 0x0000000f +#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT 0 +static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val) +{ + return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK; +} +#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK 0x000000f0 +#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT 4 +static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val) +{ + return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK; +} +#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK 0x00000f00 +#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT 8 +static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val) +{ + return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK; +} +#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK 0x0000f000 +#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT 12 +static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val) +{ + return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK; +} +#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK 0x000f0000 +#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT 16 +static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val) +{ + return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK; +} +#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK 0x00f00000 +#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT 20 +static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val) +{ + return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK; +} +#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK 0x0f000000 +#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT 24 +static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val) +{ + return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK; +} +#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK 0xf0000000 +#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT 28 +static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val) +{ + return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK; +} + +#define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF1 0x0000002f + +#define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF2 0x00000030 + #endif /* A6XX_XML */ diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h b/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h index ef68098d2adc..83ffccef2506 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h @@ -8,17 +8,17 @@ This file was generated by the rules-ng-ng headergen tool in this git repository git clone https://github.com/freedreno/envytools.git The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13) -- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13) -- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 36805 bytes, from 2018-07-03 19:37:13) -- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 13634 bytes, from 2018-07-03 19:37:13) -- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 42393 bytes, from 2018-08-06 18:45:45) -- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13) -- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13) -- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-08-06 18:45:45) -- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 101627 bytes, from 2018-08-06 18:45:45) -- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-07-03 19:37:13) -- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13) +- ./adreno.xml ( 501 bytes, from 2018-05-23 16:51:57) +- ./freedreno_copyright.xml ( 1572 bytes, from 2016-10-24 21:12:27) +- ./adreno/a2xx.xml ( 36805 bytes, from 2018-05-23 16:51:57) +- ./adreno/adreno_common.xml ( 13634 bytes, from 2018-05-23 16:51:57) +- ./adreno/adreno_pm4.xml ( 42393 bytes, from 2018-08-16 16:56:14) +- ./adreno/a3xx.xml ( 83840 bytes, from 2017-12-05 18:20:27) +- ./adreno/a4xx.xml ( 112086 bytes, from 2018-05-23 16:51:57) +- ./adreno/a5xx.xml ( 147240 bytes, from 2018-08-16 16:56:14) +- ./adreno/a6xx.xml ( 107570 bytes, from 2018-08-16 17:32:18) +- ./adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-08-16 17:35:55) +- ./adreno/ocmem.xml ( 1773 bytes, from 2016-10-24 21:12:27) Copyright (C) 2013-2018 by the following authors: - Rob Clark (robclark) @@ -167,8 +167,8 @@ static inline uint32_t A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_MIN_PASS_LENGTH(uint32_ #define REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS 0x000050d0 #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWERING_OFF 0x00000001 #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWERING_ON 0x00000002 -#define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_ON 0x00000004 -#define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_OFF 0x00000008 +#define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_OFF 0x00000004 +#define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_ON 0x00000008 #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SP_CLOCK_OFF 0x00000010 #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GMU_UP_POWER_STATE 0x00000020 #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_GDSC_POWER_OFF 0x00000040 -- 2.18.0