From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Michael S. Tsirkin" Subject: Re: [PATCH V4 4/4] target-i386: add i440fx 0xcf8 port ascoalesced_pio Date: Mon, 27 Aug 2018 15:36:29 +0300 Message-ID: <20180827153604-mutt-send-email-mst@kernel.org> References: <201808271625000266021@zte.com.cn> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Cc: zhong.weidong@zte.com.cn, ehabkost@redhat.com, kvm@vger.kernel.org, rkrcmar@redhat.com, qemu-devel@nongnu.org, liran.alon@oracle.com, pbonzini@redhat.com To: peng.hao2@zte.com.cn Return-path: Content-Disposition: inline In-Reply-To: <201808271625000266021@zte.com.cn> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+gceq-qemu-devel2=m.gmane.org@nongnu.org Sender: "Qemu-devel" List-Id: kvm.vger.kernel.org On Mon, Aug 27, 2018 at 04:25:00PM +0800, peng.hao2@zte.com.cn wrote: > >> On 25 Aug 2018, at 15:19, Peng Hao wrote: > >> > >> diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c > >> index 0e60834..da73743 100644 > >> --- a/hw/pci-host/piix.c > >> +++ b/hw/pci-host/piix.c > >> @@ -327,6 +327,10 @@ static void i440fx_pcihost_realize(DeviceState *dev, Error **errp) > >> > >> sysbus_add_io(sbd, 0xcfc, &s->data_mem); > >> sysbus_init_ioports(sbd, 0xcfc, 4); > >> + > >> + /* register i440fx 0xcf8 port as coalesced pio */ > >> + memory_region_set_flush_coalesced(&s->data_mem); > >> + memory_region_add_coalescing(&s->conf_mem, 0, 4); > >> } > >> > > >Is there a reason to not register this port as coalesced PIO also for Q35? > >In q35_host_realize()? > >If not, I would do that as an extra patch as part of this series. > Just as I mentioned in patch [0/4] , you can add pci-host config port as coalesecd pio. I think it works for q35 port 0xcf8. > >-Liran What's the performance improvement for q35? -- MST From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34662) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fuGl1-00028J-4A for qemu-devel@nongnu.org; Mon, 27 Aug 2018 08:36:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fuGkx-0004CB-UW for qemu-devel@nongnu.org; Mon, 27 Aug 2018 08:36:35 -0400 Received: from mx3-rdu2.redhat.com ([66.187.233.73]:33362 helo=mx1.redhat.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fuGkx-00048v-PU for qemu-devel@nongnu.org; Mon, 27 Aug 2018 08:36:31 -0400 Date: Mon, 27 Aug 2018 15:36:29 +0300 From: "Michael S. Tsirkin" Message-ID: <20180827153604-mutt-send-email-mst@kernel.org> References: <201808271625000266021@zte.com.cn> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <201808271625000266021@zte.com.cn> Subject: Re: [Qemu-devel] [PATCH V4 4/4] target-i386: add i440fx 0xcf8 port ascoalesced_pio List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: peng.hao2@zte.com.cn Cc: liran.alon@oracle.com, pbonzini@redhat.com, ehabkost@redhat.com, rkrcmar@redhat.com, kvm@vger.kernel.org, qemu-devel@nongnu.org, zhong.weidong@zte.com.cn On Mon, Aug 27, 2018 at 04:25:00PM +0800, peng.hao2@zte.com.cn wrote: > >> On 25 Aug 2018, at 15:19, Peng Hao wrote: > >> > >> diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c > >> index 0e60834..da73743 100644 > >> --- a/hw/pci-host/piix.c > >> +++ b/hw/pci-host/piix.c > >> @@ -327,6 +327,10 @@ static void i440fx_pcihost_realize(DeviceState *dev, Error **errp) > >> > >> sysbus_add_io(sbd, 0xcfc, &s->data_mem); > >> sysbus_init_ioports(sbd, 0xcfc, 4); > >> + > >> + /* register i440fx 0xcf8 port as coalesced pio */ > >> + memory_region_set_flush_coalesced(&s->data_mem); > >> + memory_region_add_coalescing(&s->conf_mem, 0, 4); > >> } > >> > > >Is there a reason to not register this port as coalesced PIO also for Q35? > >In q35_host_realize()? > >If not, I would do that as an extra patch as part of this series. > Just as I mentioned in patch [0/4] , you can add pci-host config port as coalesecd pio. I think it works for q35 port 0xcf8. > >-Liran What's the performance improvement for q35? -- MST