From: David Gibson <david@gibson.dropbear.id.au>
To: BALATON Zoltan <balaton@eik.bme.hu>
Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>,
hpoussin@reactos.org, qemu-devel@nongnu.org, qemu-ppc@nongnu.org
Subject: Re: [Qemu-devel] [Qemu-ppc] [PATCH] 40p: fix PCI interrupt routing
Date: Tue, 28 Aug 2018 11:02:53 +1000 [thread overview]
Message-ID: <20180828010253.GD2222@umbus.fritz.box> (raw)
In-Reply-To: <alpine.BSF.2.21.1808271903170.61025@zero.eik.bme.hu>
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On Mon, Aug 27, 2018 at 07:12:29PM +0200, BALATON Zoltan wrote:
> On Mon, 27 Aug 2018, Mark Cave-Ayland wrote:
> > According to the PReP specification section 6.1.6 "System Interrupt
> > Assignments", all PCI interrupts are routed via IRQ 15.
> >
> > With this patch applied it is now possible to boot the sandalfoot
> > zImage all the way through to a working userspace when using
> > OpenBIOS.
> >
> > Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> > ---
> > hw/ppc/prep.c | 9 +++++----
> > 1 file changed, 5 insertions(+), 4 deletions(-)
> >
> > diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c
> > index 162b27a3b8..e82c1355d9 100644
> > --- a/hw/ppc/prep.c
> > +++ b/hw/ppc/prep.c
> > @@ -668,10 +668,11 @@ static void ibm_40p_init(MachineState *machine)
> > dev = DEVICE(pci_create_simple(pci_bus, PCI_DEVFN(11, 0), "i82378"));
> > qdev_connect_gpio_out(dev, 0,
> > cpu->env.irq_inputs[PPC6xx_INPUT_INT]);
> > - sysbus_connect_irq(pcihost, 0, qdev_get_gpio_in(dev, 15));
> > - sysbus_connect_irq(pcihost, 1, qdev_get_gpio_in(dev, 13));
> > - sysbus_connect_irq(pcihost, 2, qdev_get_gpio_in(dev, 15));
> > - sysbus_connect_irq(pcihost, 3, qdev_get_gpio_in(dev, 13));
> > + /* According to PReP specification section 6.1.6 "System Interrupt
> > + * Assignments", all PCI interrupts are routed via IRQ 15 */
> > + for (i = 0; i < PCI_NUM_PINS; i++) {
> > + sysbus_connect_irq(pcihost, i, qdev_get_gpio_in(dev, 15));
> > + }
>
> I'm not sure but this looks similar to what we had with sam460ex:
>
> http://lists.nongnu.org/archive/html/qemu-ppc/2018-07/msg00359.html
>
> I think you may not connect multiple interrupts to the same host irq line
> this way but you either need an OR gate or handle it within the mapping in
> the PCI host model (which is what we ended up with for the sam460ex).
> Peter's suggestion was to do whichever matches real hardware the most if you
> can find out that (as noted here also with more explanation that could be
> useful):
>
> http://lists.nongnu.org/archive/html/qemu-ppc/2018-07/msg00360.html
>
> But I could be mistaken in this case, haven't checked it in detail.
Yeah.. I was thinking this looked very familiar. I believe you do
need to construct the OR explicitly, not just wire all the irqs to the
same line.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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next prev parent reply other threads:[~2018-08-28 1:26 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-08-27 11:05 [Qemu-devel] [PATCH] 40p: fix PCI interrupt routing Mark Cave-Ayland
2018-08-27 14:00 ` Mark Cave-Ayland
2018-08-27 17:12 ` [Qemu-devel] [Qemu-ppc] " BALATON Zoltan
2018-08-28 1:02 ` David Gibson [this message]
2018-09-08 8:47 ` Mark Cave-Ayland
2018-09-10 0:49 ` David Gibson
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