From mboxrd@z Thu Jan 1 00:00:00 1970 From: Vivek Gautam Subject: [PATCH v16 4/5] dt-bindings: arm-smmu: Add bindings for qcom, smmu-v2 Date: Thu, 30 Aug 2018 20:15:40 +0530 Message-ID: <20180830144541.17740-5-vivek.gautam@codeaurora.org> References: <20180830144541.17740-1-vivek.gautam@codeaurora.org> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <20180830144541.17740-1-vivek.gautam-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: freedreno-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "Freedreno" To: joro-zLv9SwRftAIdnm+yROfE0A@public.gmane.org, robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, robin.murphy-5wv7dgnIgG8@public.gmane.org, will.deacon-5wv7dgnIgG8@public.gmane.org, iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org Cc: mark.rutland-5wv7dgnIgG8@public.gmane.org, architt-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, jcrouse-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, linux-pm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, sboyd-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, sricharan-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, rjw-LthD3rsA81gm4RdzfppkhA@public.gmane.org, robdclark-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, tfiga-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org, alex.williamson-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org, Vivek Gautam , linux-arm-msm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org, m.szyprowski-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org List-Id: linux-arm-msm@vger.kernel.org QWRkIGJpbmRpbmdzIGRvYyBmb3IgUWNvbSdzIHNtbXUtdjIgaW1wbGVtZW50YXRpb24uCgpTaWdu ZWQtb2ZmLWJ5OiBWaXZlayBHYXV0YW0gPHZpdmVrLmdhdXRhbUBjb2RlYXVyb3JhLm9yZz4KUmV2 aWV3ZWQtYnk6IFRvbWFzeiBGaWdhIDx0ZmlnYUBjaHJvbWl1bS5vcmc+ClRlc3RlZC1ieTogU3Jp bml2YXMgS2FuZGFnYXRsYSA8c3Jpbml2YXMua2FuZGFnYXRsYUBsaW5hcm8ub3JnPgotLS0KIC4u Li9kZXZpY2V0cmVlL2JpbmRpbmdzL2lvbW11L2FybSxzbW11LnR4dCAgICAgICAgIHwgMzkgKysr KysrKysrKysrKysrKysrKysrKwogMSBmaWxlIGNoYW5nZWQsIDM5IGluc2VydGlvbnMoKykKCmRp ZmYgLS1naXQgYS9Eb2N1bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGluZ3MvaW9tbXUvYXJtLHNt bXUudHh0IGIvRG9jdW1lbnRhdGlvbi9kZXZpY2V0cmVlL2JpbmRpbmdzL2lvbW11L2FybSxzbW11 LnR4dAppbmRleCA4YTZmZmNlMTJhZjUuLmE2NTA0YjM3Y2MyMSAxMDA2NDQKLS0tIGEvRG9jdW1l bnRhdGlvbi9kZXZpY2V0cmVlL2JpbmRpbmdzL2lvbW11L2FybSxzbW11LnR4dAorKysgYi9Eb2N1 bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGluZ3MvaW9tbXUvYXJtLHNtbXUudHh0CkBAIC0xNywx MCArMTcsMTYgQEAgY29uZGl0aW9ucy4KICAgICAgICAgICAgICAgICAgICAgICAgICJhcm0sbW11 LTQwMSIKICAgICAgICAgICAgICAgICAgICAgICAgICJhcm0sbW11LTUwMCIKICAgICAgICAgICAg ICAgICAgICAgICAgICJjYXZpdW0sc21tdS12MiIKKyAgICAgICAgICAgICAgICAgICAgICAgICJx Y29tLHNtbXUtdjIiCiAKICAgICAgICAgICAgICAgICAgIGRlcGVuZGluZyBvbiB0aGUgcGFydGlj dWxhciBpbXBsZW1lbnRhdGlvbiBhbmQvb3IgdGhlCiAgICAgICAgICAgICAgICAgICB2ZXJzaW9u IG9mIHRoZSBhcmNoaXRlY3R1cmUgaW1wbGVtZW50ZWQuCiAKKyAgICAgICAgICAgICAgICAgIFFj b20gU29DcyBtdXN0IGNvbnRhaW4sIGFzIGJlbG93LCBTb0Mtc3BlY2lmaWMgY29tcGF0aWJsZXMK KyAgICAgICAgICAgICAgICAgIGFsb25nIHdpdGggInFjb20sc21tdS12MiI6CisgICAgICAgICAg ICAgICAgICAicWNvbSxtc204OTk2LXNtbXUtdjIiLCAicWNvbSxzbW11LXYyIiwKKyAgICAgICAg ICAgICAgICAgICJxY29tLHNkbTg0NS1zbW11LXYyIiwgInFjb20sc21tdS12MiIuCisKIC0gcmVn ICAgICAgICAgICA6IEJhc2UgYWRkcmVzcyBhbmQgc2l6ZSBvZiB0aGUgU01NVS4KIAogLSAjZ2xv YmFsLWludGVycnVwdHMgOiBUaGUgbnVtYmVyIG9mIGdsb2JhbCBpbnRlcnJ1cHRzIGV4cG9zZWQg YnkgdGhlCkBAIC03MSw2ICs3NywyMiBAQCBjb25kaXRpb25zLgogICAgICAgICAgICAgICAgICAg b3IgdXNpbmcgc3RyZWFtIG1hdGNoaW5nIHdpdGggI2lvbW11LWNlbGxzID0gPDI+LCBhbmQKICAg ICAgICAgICAgICAgICAgIG1heSBiZSBpZ25vcmVkIGlmIHByZXNlbnQgaW4gc3VjaCBjYXNlcy4K IAorLSBjbG9jay1uYW1lczogICAgTGlzdCBvZiB0aGUgbmFtZXMgb2YgY2xvY2tzIGlucHV0IHRv IHRoZSBkZXZpY2UuIFRoZQorICAgICAgICAgICAgICAgICAgcmVxdWlyZWQgbGlzdCBkZXBlbmRz IG9uIHBhcnRpY3VsYXIgaW1wbGVtZW50YXRpb24gYW5kCisgICAgICAgICAgICAgICAgICBpcyBh cyBmb2xsb3dzOgorICAgICAgICAgICAgICAgICAgLSBmb3IgInFjb20sc21tdS12MiI6CisgICAg ICAgICAgICAgICAgICAgIC0gImJ1cyI6IGNsb2NrIHJlcXVpcmVkIGZvciBkb3duc3RyZWFtIGJ1 cyBhY2Nlc3MgYW5kCisgICAgICAgICAgICAgICAgICAgICAgICAgICAgIGZvciB0aGUgc21tdSBw dHcsCisgICAgICAgICAgICAgICAgICAgIC0gImlmYWNlIjogY2xvY2sgcmVxdWlyZWQgdG8gYWNj ZXNzIHNtbXUncyByZWdpc3RlcnMKKyAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICB0aHJv dWdoIHRoZSBUQ1UncyBwcm9ncmFtbWluZyBpbnRlcmZhY2UuCisgICAgICAgICAgICAgICAgICAt IHVuc3BlY2lmaWVkIGZvciBvdGhlciBpbXBsZW1lbnRhdGlvbnMuCisKKy0gY2xvY2tzOiAgICAg ICAgIFNwZWNpZmllcnMgZm9yIGFsbCBjbG9ja3MgbGlzdGVkIGluIHRoZSBjbG9jay1uYW1lcyBw cm9wZXJ0eSwKKyAgICAgICAgICAgICAgICAgIGFzIHBlciBnZW5lcmljIGNsb2NrIGJpbmRpbmdz LgorCistIHBvd2VyLWRvbWFpbnM6ICBTcGVjaWZpZXJzIGZvciBwb3dlciBkb21haW5zIHJlcXVp cmVkIHRvIGJlIHBvd2VyZWQgb24gZm9yCisgICAgICAgICAgICAgICAgICB0aGUgU01NVSB0byBv cGVyYXRlLCBhcyBwZXIgZ2VuZXJpYyBwb3dlciBkb21haW4gYmluZGluZ3MuCisKICoqIERlcHJl Y2F0ZWQgcHJvcGVydGllczoKIAogLSBtbXUtbWFzdGVycyAoZGVwcmVjYXRlZCBpbiBmYXZvdXIg b2YgdGhlIGdlbmVyaWMgImlvbW11cyIgYmluZGluZykgOgpAQCAtMTM3LDMgKzE1OSwyMCBAQCBj b25kaXRpb25zLgogICAgICAgICAgICAgICAgIGlvbW11LW1hcCA9IDwwICZzbW11MyAwIDB4NDAw PjsKICAgICAgICAgICAgICAgICAuLi4KICAgICAgICAgfTsKKworCS8qIFFjb20ncyBhcm0sc21t dS12MiBpbXBsZW1lbnRhdGlvbiAqLworCXNtbXU0OiBpb21tdUBkMDAwMDAgeworCQljb21wYXRp YmxlID0gInFjb20sbXNtODk5Ni1zbW11LXYyIiwgInFjb20sc21tdS12MiI7CisJCXJlZyA9IDww eGQwMDAwMCAweDEwMDAwPjsKKworCQkjZ2xvYmFsLWludGVycnVwdHMgPSA8MT47CisJCWludGVy cnVwdHMgPSA8R0lDX1NQSSA3MyBJUlFfVFlQRV9MRVZFTF9ISUdIPiwKKwkJCSAgICAgPEdJQ19T UEkgMzIwIElSUV9UWVBFX0xFVkVMX0hJR0g+LAorCQkJICAgICA8R0lDX1NQSSAzMjEgSVJRX1RZ UEVfTEVWRUxfSElHSD47CisJCSNpb21tdS1jZWxscyA9IDwxPjsKKwkJcG93ZXItZG9tYWlucyA9 IDwmbW1jYyBNRFNTX0dEU0M+OworCisJCWNsb2NrcyA9IDwmbW1jYyBTTU1VX01EUF9BWElfQ0xL PiwKKwkJCSA8Jm1tY2MgU01NVV9NRFBfQUhCX0NMSz47CisJCWNsb2NrLW5hbWVzID0gImJ1cyIs ICJpZmFjZSI7CisJfTsKLS0gClFVQUxDT01NIElORElBLCBvbiBiZWhhbGYgb2YgUXVhbGNvbW0g SW5ub3ZhdGlvbiBDZW50ZXIsIEluYy4gaXMgYSBtZW1iZXIKb2YgQ29kZSBBdXJvcmEgRm9ydW0s IGhvc3RlZCBieSBUaGUgTGludXggRm91bmRhdGlvbgoKX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX18KRnJlZWRyZW5vIG1haWxpbmcgbGlzdApGcmVlZHJlbm9A bGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxt YW4vbGlzdGluZm8vZnJlZWRyZW5vCg== From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.6 required=3.0 tests=DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_PASS,T_DKIM_INVALID, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0029AC433F5 for ; Thu, 30 Aug 2018 14:46:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9BB3320836 for ; Thu, 30 Aug 2018 14:46:42 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="klJ+Y7TZ"; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="hLJ/ZPdp" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9BB3320836 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729990AbeH3StJ (ORCPT ); Thu, 30 Aug 2018 14:49:09 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:57608 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729404AbeH3StI (ORCPT ); Thu, 30 Aug 2018 14:49:08 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id A79F9606FC; Thu, 30 Aug 2018 14:46:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1535640397; bh=QmXc5jDxFAXBdJV7M3zVXEzN/XtYSAEl7NIy+dukw9Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=klJ+Y7TZ/ycn9s8D4lFDtpQaJ8UQE/K1+895W4lO3lP0TMIF0O76r6K/0oHJjYK3Q 3Mpku26SmsLgkWWFIy7aawZ12sFdndAxdP9UkDGQyoHCg9UGjwW8UC/jgk4h25JTbW N+40LpUU1fSw22O7O2xsdRp7UnMIuIAiIKKrYJks= Received: from blr-ubuntu-41.ap.qualcomm.com (blr-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.18.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: vivek.gautam@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 06C5A607DC; Thu, 30 Aug 2018 14:46:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1535640392; bh=QmXc5jDxFAXBdJV7M3zVXEzN/XtYSAEl7NIy+dukw9Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hLJ/ZPdpcZ1JbPtuhBcT7YNCbGHum1kHCwsog+H7MJqal5VTYkw4tqb8HzBHazYau 0Rq1e5f45j+GgXmGf9oPRJ5fYgdkUwN2mPoOCz3TUsXNLNNvZxy31LCAma7dyoZ9sP hz3+Of0O6wWvsQOuzQGyfSFq1opAKm4ehK5Ojvzo= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 06C5A607DC Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=vivek.gautam@codeaurora.org From: Vivek Gautam To: joro@8bytes.org, robh+dt@kernel.org, robin.murphy@arm.com, will.deacon@arm.com, iommu@lists.linux-foundation.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: alex.williamson@redhat.com, mark.rutland@arm.com, rjw@rjwysocki.net, robdclark@gmail.com, linux-pm@vger.kernel.org, freedreno@lists.freedesktop.org, sboyd@kernel.org, tfiga@chromium.org, jcrouse@codeaurora.org, sricharan@codeaurora.org, m.szyprowski@samsung.com, architt@codeaurora.org, linux-arm-msm@vger.kernel.org, Vivek Gautam Subject: [PATCH v16 4/5] dt-bindings: arm-smmu: Add bindings for qcom,smmu-v2 Date: Thu, 30 Aug 2018 20:15:40 +0530 Message-Id: <20180830144541.17740-5-vivek.gautam@codeaurora.org> X-Mailer: git-send-email 2.16.1.72.g5be1f00a9a70 In-Reply-To: <20180830144541.17740-1-vivek.gautam@codeaurora.org> References: <20180830144541.17740-1-vivek.gautam@codeaurora.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add bindings doc for Qcom's smmu-v2 implementation. Signed-off-by: Vivek Gautam Reviewed-by: Tomasz Figa Tested-by: Srinivas Kandagatla --- .../devicetree/bindings/iommu/arm,smmu.txt | 39 ++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt b/Documentation/devicetree/bindings/iommu/arm,smmu.txt index 8a6ffce12af5..a6504b37cc21 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.txt +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.txt @@ -17,10 +17,16 @@ conditions. "arm,mmu-401" "arm,mmu-500" "cavium,smmu-v2" + "qcom,smmu-v2" depending on the particular implementation and/or the version of the architecture implemented. + Qcom SoCs must contain, as below, SoC-specific compatibles + along with "qcom,smmu-v2": + "qcom,msm8996-smmu-v2", "qcom,smmu-v2", + "qcom,sdm845-smmu-v2", "qcom,smmu-v2". + - reg : Base address and size of the SMMU. - #global-interrupts : The number of global interrupts exposed by the @@ -71,6 +77,22 @@ conditions. or using stream matching with #iommu-cells = <2>, and may be ignored if present in such cases. +- clock-names: List of the names of clocks input to the device. The + required list depends on particular implementation and + is as follows: + - for "qcom,smmu-v2": + - "bus": clock required for downstream bus access and + for the smmu ptw, + - "iface": clock required to access smmu's registers + through the TCU's programming interface. + - unspecified for other implementations. + +- clocks: Specifiers for all clocks listed in the clock-names property, + as per generic clock bindings. + +- power-domains: Specifiers for power domains required to be powered on for + the SMMU to operate, as per generic power domain bindings. + ** Deprecated properties: - mmu-masters (deprecated in favour of the generic "iommus" binding) : @@ -137,3 +159,20 @@ conditions. iommu-map = <0 &smmu3 0 0x400>; ... }; + + /* Qcom's arm,smmu-v2 implementation */ + smmu4: iommu@d00000 { + compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; + reg = <0xd00000 0x10000>; + + #global-interrupts = <1>; + interrupts = , + , + ; + #iommu-cells = <1>; + power-domains = <&mmcc MDSS_GDSC>; + + clocks = <&mmcc SMMU_MDP_AXI_CLK>, + <&mmcc SMMU_MDP_AHB_CLK>; + clock-names = "bus", "iface"; + }; -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation