From: Mika Westerberg <mika.westerberg@linux.intel.com>
To: Daniel Drake <drake@endlessm.com>
Cc: Bjorn Helgaas <helgaas@kernel.org>,
Bjorn Helgaas <bhelgaas@google.com>,
linux-pci@vger.kernel.org,
Linux Upstreaming Team <linux@endlessm.com>,
nouveau@lists.freedesktop.org,
Linux PM <linux-pm@vger.kernel.org>,
Peter Wu <peter@lekensteyn.nl>,
kherbst@redhat.com,
Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
"Rafael J. Wysocki" <rafael.j.wysocki@intel.com>,
Keith Busch <keith.busch@intel.com>,
Jon Derrick <jonathan.derrick@intel.com>
Subject: Re: [PATCH] PCI: add prefetch quirk to work around Asus/Nvidia suspend issues
Date: Mon, 3 Sep 2018 15:12:09 +0300 [thread overview]
Message-ID: <20180903121209.GC2283@lahna.fi.intel.com> (raw)
In-Reply-To: <CAD8Lp45CKCHxTg91zF9bWztqbAwLzgAUpNEHQ6ouKu2PkJT8SQ@mail.gmail.com>
On Mon, Sep 03, 2018 at 04:56:32PM +0800, Daniel Drake wrote:
> On Sat, Sep 1, 2018 at 3:12 AM, Bjorn Helgaas <helgaas@kernel.org> wrote:
> > If true, this sounds like some sort of erratum, so it would be good to
> > get some input from Intel, and I cc'd a few Intel folks.
>
> Yes, it would be great to get their input.
We have seen one similar issue with LPSS devices when BIOS assigns
device BARs above 4G (which is not the case here) and it turned out to
be misconfigured MTRR register or something like that. It may not be
related at all but it could be worth a try to dump out MTRR registers of
one of the affected systems and see if the memory areas are listed there
(and if the attributes are somehow wrong if found).
WARNING: multiple messages have this Message-ID (diff)
From: Mika Westerberg <mika.westerberg-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
To: Daniel Drake <drake-6IF/jdPJHihWk0Htik3J/w@public.gmane.org>
Cc: Linux PM <linux-pm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
"Rafael J. Wysocki"
<rafael.j.wysocki-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>,
Keith Busch <keith.busch-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>,
Bjorn Helgaas <helgaas-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org,
Bjorn Helgaas <bhelgaas-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>,
Andy Shevchenko
<andriy.shevchenko-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>,
Linux Upstreaming Team
<linux-6IF/jdPJHihWk0Htik3J/w@public.gmane.org>,
Jon Derrick
<jonathan.derrick-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
Subject: Re: [PATCH] PCI: add prefetch quirk to work around Asus/Nvidia suspend issues
Date: Mon, 3 Sep 2018 15:12:09 +0300 [thread overview]
Message-ID: <20180903121209.GC2283@lahna.fi.intel.com> (raw)
In-Reply-To: <CAD8Lp45CKCHxTg91zF9bWztqbAwLzgAUpNEHQ6ouKu2PkJT8SQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On Mon, Sep 03, 2018 at 04:56:32PM +0800, Daniel Drake wrote:
> On Sat, Sep 1, 2018 at 3:12 AM, Bjorn Helgaas <helgaas@kernel.org> wrote:
> > If true, this sounds like some sort of erratum, so it would be good to
> > get some input from Intel, and I cc'd a few Intel folks.
>
> Yes, it would be great to get their input.
We have seen one similar issue with LPSS devices when BIOS assigns
device BARs above 4G (which is not the case here) and it turned out to
be misconfigured MTRR register or something like that. It may not be
related at all but it could be worth a try to dump out MTRR registers of
one of the affected systems and see if the memory areas are listed there
(and if the attributes are somehow wrong if found).
_______________________________________________
Nouveau mailing list
Nouveau@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/nouveau
next prev parent reply other threads:[~2018-09-03 12:12 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-08-31 7:30 [PATCH] PCI: add prefetch quirk to work around Asus/Nvidia suspend issues Daniel Drake
2018-08-31 7:30 ` Daniel Drake
2018-08-31 19:12 ` Bjorn Helgaas
2018-08-31 19:12 ` Bjorn Helgaas
2018-09-03 8:56 ` Daniel Drake
2018-09-03 8:56 ` Daniel Drake
2018-09-03 12:12 ` Mika Westerberg [this message]
2018-09-03 12:12 ` Mika Westerberg
2018-09-04 1:52 ` Daniel Drake
2018-09-04 1:52 ` Daniel Drake
2018-09-04 6:43 ` Mika Westerberg
2018-09-04 6:43 ` Mika Westerberg
2018-09-04 7:07 ` Daniel Drake
2018-09-04 7:07 ` Daniel Drake
2018-09-04 9:36 ` Mika Westerberg
2018-09-04 9:36 ` Mika Westerberg
2018-09-06 9:02 ` Daniel Drake
2018-09-06 9:02 ` Daniel Drake
2018-08-31 21:47 ` kbuild test robot
2018-08-31 21:47 ` kbuild test robot
2018-09-04 15:31 ` kbuild test robot
2018-09-04 15:31 ` kbuild test robot
2018-09-06 13:35 ` [Nouveau] " Thomas Martitz
2018-09-06 13:35 ` Thomas Martitz
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