From: Wolfram Sang <wsa@the-dreams.de>
To: shubhrajyoti.datta@gmail.com
Cc: linux-i2c@vger.kernel.org, michal.simek@xilinx.com,
linux-kernel@vger.kernel.org,
Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Subject: Re: [PATCH] i2c: xiic: Make the start and the byte count write atomic
Date: Tue, 4 Sep 2018 18:11:14 +0200 [thread overview]
Message-ID: <20180904161114.GC5000@kunai> (raw)
In-Reply-To: <1535967671-7784-1-git-send-email-shubhrajyoti.datta@gmail.com>
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On Mon, Sep 03, 2018 at 03:11:11PM +0530, shubhrajyoti.datta@gmail.com wrote:
> From: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
>
> Disable interrupts while configuring the transfer and enable them back.
>
> We have below as the programming sequence
> 1. start and slave address
> 2. byte count and stop
>
> In some customer platform there was a lot of interrupts between 1 and 2
> and after slave address (around 7 clock cyles) if 2 is not executed
> then the transaction is nacked.
>
> To fix this case make the 2 writes atomic.
>
> Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
I assume simply changing the order of the register writes won't fix it?
I also assume this is stable material?
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next prev parent reply other threads:[~2018-09-04 16:11 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-09-03 9:41 [PATCH] i2c: xiic: Make the start and the byte count write atomic shubhrajyoti.datta
2018-09-03 9:41 ` shubhrajyoti.datta
2018-09-04 16:11 ` Wolfram Sang [this message]
2018-09-06 7:08 ` Shubhrajyoti Datta
2018-09-06 18:52 ` Wolfram Sang
2018-09-07 6:02 ` Michal Simek
2018-09-07 6:02 ` Michal Simek
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