From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [v5,4/4] arm64: zynqmp: Add DDRC node From: Borislav Petkov Message-Id: <20180905102053.GE2237@zn.tnic> Date: Wed, 5 Sep 2018 12:20:53 +0200 To: Manish Narani , robh+dt@kernel.org Cc: mark.rutland@arm.com, michal.simek@xilinx.com, mchehab@kernel.org, leoyang.li@nxp.com, amit.kucheria@linaro.org, olof@lixom.net, sgoud@xilinx.com, anirudh@xilinx.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org List-ID: T24gRnJpLCBBdWcgMzEsIDIwMTggYXQgMDY6NTc6NTBQTSArMDUzMCwgTWFuaXNoIE5hcmFuaSB3 cm90ZToKPiBBZGQgZGRyYyBtZW1vcnkgY29udHJvbGxlciBub2RlIGluIGR0cy4gVGhlIHNpemUg bWVudGlvbmVkIGluIGR0cyBpcwo+IDB4MzAwMDAsIGJlY2F1c2Ugd2UgbmVlZCB0byBhY2Nlc3Mg RERSX1FPUyBJTlRSIHJlZ2lzdGVycyBsb2NhdGVkIGF0Cj4gMHhGRDA5MDIwOCBmcm9tIHRoaXMg ZHJpdmVyLgo+IAo+IFNpZ25lZC1vZmYtYnk6IE1hbmlzaCBOYXJhbmkgPG1hbmlzaC5uYXJhbmlA eGlsaW54LmNvbT4KPiAtLS0KPiAgYXJjaC9hcm02NC9ib290L2R0cy94aWxpbngvenlucW1wLmR0 c2kgfCA3ICsrKysrKysKPiAgMSBmaWxlIGNoYW5nZWQsIDcgaW5zZXJ0aW9ucygrKQo+IAo+IGRp ZmYgLS1naXQgYS9hcmNoL2FybTY0L2Jvb3QvZHRzL3hpbGlueC96eW5xbXAuZHRzaSBiL2FyY2gv YXJtNjQvYm9vdC9kdHMveGlsaW54L3p5bnFtcC5kdHNpCj4gaW5kZXggMjljZTIzNC4uYTgxZDNi MTYgMTAwNjQ0Cj4gLS0tIGEvYXJjaC9hcm02NC9ib290L2R0cy94aWxpbngvenlucW1wLmR0c2kK PiArKysgYi9hcmNoL2FybTY0L2Jvb3QvZHRzL3hpbGlueC96eW5xbXAuZHRzaQo+IEBAIC0zNTUs NiArMzU1LDEzIEBACj4gIAkJCXhsbngsYnVzLXdpZHRoID0gPDY0PjsKPiAgCQl9Owo+ICAKPiAr CQltYzogbWVtb3J5LWNvbnRyb2xsZXJAZmQwNzAwMDAgewo+ICsJCQljb21wYXRpYmxlID0gInhs bngsenlucW1wLWRkcmMtMi40MGEiOwo+ICsJCQlyZWcgPSA8MHgwIDB4ZmQwNzAwMDAgMHgwIDB4 MzAwMDA+Owo+ICsJCQlpbnRlcnJ1cHQtcGFyZW50ID0gPCZnaWM+Owo+ICsJCQlpbnRlcnJ1cHRz ID0gPDAgMTEyIDQ+Owo+ICsJCX07Cj4gKwo+ICAJCWdlbTA6IGV0aGVybmV0QGZmMGIwMDAwIHsK PiAgCQkJY29tcGF0aWJsZSA9ICJjZG5zLHp5bnFtcC1nZW0iLCAiY2RucyxnZW0iOwo+ICAJCQlz dGF0dXMgPSAiZGlzYWJsZWQiOwo+IC0tIAoKVGhpcyBzdGlsbCBuZWVkcyBSb2IncyBBQ0suCg== From mboxrd@z Thu Jan 1 00:00:00 1970 From: bp@alien8.de (Borislav Petkov) Date: Wed, 5 Sep 2018 12:20:53 +0200 Subject: [PATCH v5 4/4] arm64: zynqmp: Add DDRC node In-Reply-To: <1535722070-10394-5-git-send-email-manish.narani@xilinx.com> References: <1535722070-10394-1-git-send-email-manish.narani@xilinx.com> <1535722070-10394-5-git-send-email-manish.narani@xilinx.com> Message-ID: <20180905102053.GE2237@zn.tnic> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Fri, Aug 31, 2018 at 06:57:50PM +0530, Manish Narani wrote: > Add ddrc memory controller node in dts. The size mentioned in dts is > 0x30000, because we need to access DDR_QOS INTR registers located at > 0xFD090208 from this driver. > > Signed-off-by: Manish Narani > --- > arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > index 29ce234..a81d3b16 100644 > --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > @@ -355,6 +355,13 @@ > xlnx,bus-width = <64>; > }; > > + mc: memory-controller at fd070000 { > + compatible = "xlnx,zynqmp-ddrc-2.40a"; > + reg = <0x0 0xfd070000 0x0 0x30000>; > + interrupt-parent = <&gic>; > + interrupts = <0 112 4>; > + }; > + > gem0: ethernet at ff0b0000 { > compatible = "cdns,zynqmp-gem", "cdns,gem"; > status = "disabled"; > -- This still needs Rob's ACK. -- Regards/Gruss, Boris. Good mailing practices for 400: avoid top-posting and trim the reply. From mboxrd@z Thu Jan 1 00:00:00 1970 From: Borislav Petkov Subject: Re: [PATCH v5 4/4] arm64: zynqmp: Add DDRC node Date: Wed, 5 Sep 2018 12:20:53 +0200 Message-ID: <20180905102053.GE2237@zn.tnic> References: <1535722070-10394-1-git-send-email-manish.narani@xilinx.com> <1535722070-10394-5-git-send-email-manish.narani@xilinx.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Return-path: Content-Disposition: inline In-Reply-To: <1535722070-10394-5-git-send-email-manish.narani@xilinx.com> Sender: linux-kernel-owner@vger.kernel.org To: Manish Narani , robh+dt@kernel.org Cc: mark.rutland@arm.com, michal.simek@xilinx.com, mchehab@kernel.org, leoyang.li@nxp.com, amit.kucheria@linaro.org, olof@lixom.net, sgoud@xilinx.com, anirudh@xilinx.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org List-Id: devicetree@vger.kernel.org On Fri, Aug 31, 2018 at 06:57:50PM +0530, Manish Narani wrote: > Add ddrc memory controller node in dts. The size mentioned in dts is > 0x30000, because we need to access DDR_QOS INTR registers located at > 0xFD090208 from this driver. > > Signed-off-by: Manish Narani > --- > arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > index 29ce234..a81d3b16 100644 > --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > @@ -355,6 +355,13 @@ > xlnx,bus-width = <64>; > }; > > + mc: memory-controller@fd070000 { > + compatible = "xlnx,zynqmp-ddrc-2.40a"; > + reg = <0x0 0xfd070000 0x0 0x30000>; > + interrupt-parent = <&gic>; > + interrupts = <0 112 4>; > + }; > + > gem0: ethernet@ff0b0000 { > compatible = "cdns,zynqmp-gem", "cdns,gem"; > status = "disabled"; > -- This still needs Rob's ACK. -- Regards/Gruss, Boris. Good mailing practices for 400: avoid top-posting and trim the reply.