From mboxrd@z Thu Jan 1 00:00:00 1970 From: Borislav Petkov Subject: Re: [PATCH v5 15/16] driver/edac: enable Hygon support to AMD64 EDAC driver Date: Wed, 5 Sep 2018 12:44:05 +0200 Message-ID: <20180905104405.GG2237@zn.tnic> References: <47e08d8bab1cef667be3955941e7eedc23187ae1.1535459013.git.puwen@hygon.cn> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Return-path: Content-Disposition: inline In-Reply-To: <47e08d8bab1cef667be3955941e7eedc23187ae1.1535459013.git.puwen@hygon.cn> Sender: linux-kernel-owner@vger.kernel.org To: Pu Wen Cc: tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com, x86@kernel.org, thomas.lendacky@amd.com, pbonzini@redhat.com, mchehab@kernel.org, mikhail.jin@gmail.com, linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, linux-edac@vger.kernel.org List-Id: linux-arch.vger.kernel.org Subject should be: EDAC, amd64: Add Hygon Dhyana support On Wed, Aug 29, 2018 at 08:45:45PM +0800, Pu Wen wrote: > To make AMD64 EDAC and MCE drivers working on Hygon platforms, add > support for Hygon by using the code path of AMD family 0x17. > > As Hygon will negotiate with AMD to make sure that only Hygon will > use family 0x18, under this consideration try to minimize code > modifications and share most codes with AMD. > > Also Hygon PCI Device ID DF_F0/DF_F6(0x1460/0x1466) of Host bridges > is needed for edac driver. > > Signed-off-by: Pu Wen > --- > drivers/edac/amd64_edac.c | 20 +++++++++++++++++++- > drivers/edac/amd64_edac.h | 4 ++++ > drivers/edac/mce_amd.c | 4 +++- > 3 files changed, 26 insertions(+), 2 deletions(-) > > diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c > index 18aeabb..d8b4b0e 100644 > --- a/drivers/edac/amd64_edac.c > +++ b/drivers/edac/amd64_edac.c > @@ -211,7 +211,7 @@ static int __set_scrub_rate(struct amd64_pvt *pvt, u32 new_bw, u32 min_rate) > > scrubval = scrubrates[i].scrubval; > > - if (pvt->fam == 0x17) { > + if (pvt->fam == 0x17 || pvt->fam == 0x18) { > __f17h_set_scrubval(pvt, scrubval); > } else if (pvt->fam == 0x15 && pvt->model == 0x60) { > f15h_select_dct(pvt, 0); > @@ -264,6 +264,7 @@ static int get_scrub_rate(struct mem_ctl_info *mci) > break; > > case 0x17: > + case 0x18: > amd64_read_pci_cfg(pvt->F6, F17H_SCR_BASE_ADDR, &scrubval); > if (scrubval & BIT(0)) { > amd64_read_pci_cfg(pvt->F6, F17H_SCR_LIMIT_ADDR, &scrubval); > @@ -1044,6 +1045,7 @@ static void determine_memory_type(struct amd64_pvt *pvt) > goto ddr3; > > case 0x17: > + case 0x18: > if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(5)) > pvt->dram_type = MEM_LRDDR4; > else if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(4)) > @@ -2200,6 +2202,16 @@ static struct amd64_family_type family_types[] = { > .dbam_to_cs = f17_base_addr_to_cs_size, > } > }, > + [HYGON_F18_CPUS] = { > + /* Hygon F18h uses the same AMD F17h support */ > + .ctl_name = "Hygon_F18h", > + .f0_id = PCI_DEVICE_ID_HYGON_18H_DF_F0, > + .f6_id = PCI_DEVICE_ID_HYGON_18H_DF_F6, > + .ops = { > + .early_channel_count = f17_early_channel_count, > + .dbam_to_cs = f17_base_addr_to_cs_size, > + } > + }, > }; > > /* > @@ -3192,6 +3204,11 @@ static struct amd64_family_type *per_family_init(struct amd64_pvt *pvt) > pvt->ops = &family_types[F17_CPUS].ops; > break; > > + case 0x18: > + fam_type = &family_types[HYGON_F18_CPUS]; > + pvt->ops = &family_types[HYGON_F18_CPUS].ops; > + break; > + You can use the F17_CPUS array element here and overwrite the ->ctl_name string only. No need to define [HYGON_F18_CPUS] above... yet. > default: > amd64_err("Unsupported family!\n"); > return NULL; > @@ -3428,6 +3445,7 @@ static const struct x86_cpu_id amd64_cpuids[] = { > { X86_VENDOR_AMD, 0x15, X86_MODEL_ANY, X86_FEATURE_ANY, 0 }, > { X86_VENDOR_AMD, 0x16, X86_MODEL_ANY, X86_FEATURE_ANY, 0 }, > { X86_VENDOR_AMD, 0x17, X86_MODEL_ANY, X86_FEATURE_ANY, 0 }, > + { X86_VENDOR_HYGON, 0x18, X86_MODEL_ANY, X86_FEATURE_ANY, 0 }, > { } > }; > MODULE_DEVICE_TABLE(x86cpu, amd64_cpuids); > diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h > index 1d4b74e..6e5f609 100644 > --- a/drivers/edac/amd64_edac.h > +++ b/drivers/edac/amd64_edac.h > @@ -116,6 +116,9 @@ > #define PCI_DEVICE_ID_AMD_17H_DF_F0 0x1460 > #define PCI_DEVICE_ID_AMD_17H_DF_F6 0x1466 > > +#define PCI_DEVICE_ID_HYGON_18H_DF_F0 0x1460 > +#define PCI_DEVICE_ID_HYGON_18H_DF_F6 0x1466 As in the previous patch - use the AMD defines. -- Regards/Gruss, Boris. Good mailing practices for 400: avoid top-posting and trim the reply. From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [v5,15/16] driver/edac: enable Hygon support to AMD64 EDAC driver From: Borislav Petkov Message-Id: <20180905104405.GG2237@zn.tnic> Date: Wed, 5 Sep 2018 12:44:05 +0200 To: Pu Wen Cc: tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com, x86@kernel.org, thomas.lendacky@amd.com, pbonzini@redhat.com, mchehab@kernel.org, mikhail.jin@gmail.com, linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, linux-edac@vger.kernel.org List-ID: U3ViamVjdCBzaG91bGQgYmU6CgpFREFDLCBhbWQ2NDogQWRkIEh5Z29uIERoeWFuYSBzdXBwb3J0 CgpPbiBXZWQsIEF1ZyAyOSwgMjAxOCBhdCAwODo0NTo0NVBNICswODAwLCBQdSBXZW4gd3JvdGU6 Cj4gVG8gbWFrZSBBTUQ2NCBFREFDIGFuZCBNQ0UgZHJpdmVycyB3b3JraW5nIG9uIEh5Z29uIHBs YXRmb3JtcywgYWRkCj4gc3VwcG9ydCBmb3IgSHlnb24gYnkgdXNpbmcgdGhlIGNvZGUgcGF0aCBv ZiBBTUQgZmFtaWx5IDB4MTcuCj4gCj4gQXMgSHlnb24gd2lsbCBuZWdvdGlhdGUgd2l0aCBBTUQg dG8gbWFrZSBzdXJlIHRoYXQgb25seSBIeWdvbiB3aWxsCj4gdXNlIGZhbWlseSAweDE4LCB1bmRl ciB0aGlzIGNvbnNpZGVyYXRpb24gdHJ5IHRvIG1pbmltaXplIGNvZGUKPiBtb2RpZmljYXRpb25z IGFuZCBzaGFyZSBtb3N0IGNvZGVzIHdpdGggQU1ELgo+IAo+IEFsc28gSHlnb24gUENJIERldmlj ZSBJRCBERl9GMC9ERl9GNigweDE0NjAvMHgxNDY2KSBvZiBIb3N0IGJyaWRnZXMKPiBpcyBuZWVk ZWQgZm9yIGVkYWMgZHJpdmVyLgo+IAo+IFNpZ25lZC1vZmYtYnk6IFB1IFdlbiA8cHV3ZW5AaHln b24uY24+Cj4gLS0tCj4gIGRyaXZlcnMvZWRhYy9hbWQ2NF9lZGFjLmMgfCAyMCArKysrKysrKysr KysrKysrKysrLQo+ICBkcml2ZXJzL2VkYWMvYW1kNjRfZWRhYy5oIHwgIDQgKysrKwo+ICBkcml2 ZXJzL2VkYWMvbWNlX2FtZC5jICAgIHwgIDQgKysrLQo+ICAzIGZpbGVzIGNoYW5nZWQsIDI2IGlu c2VydGlvbnMoKyksIDIgZGVsZXRpb25zKC0pCj4gCj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvZWRh Yy9hbWQ2NF9lZGFjLmMgYi9kcml2ZXJzL2VkYWMvYW1kNjRfZWRhYy5jCj4gaW5kZXggMThhZWFi Yi4uZDhiNGIwZSAxMDA2NDQKPiAtLS0gYS9kcml2ZXJzL2VkYWMvYW1kNjRfZWRhYy5jCj4gKysr IGIvZHJpdmVycy9lZGFjL2FtZDY0X2VkYWMuYwo+IEBAIC0yMTEsNyArMjExLDcgQEAgc3RhdGlj IGludCBfX3NldF9zY3J1Yl9yYXRlKHN0cnVjdCBhbWQ2NF9wdnQgKnB2dCwgdTMyIG5ld19idywg dTMyIG1pbl9yYXRlKQo+ICAKPiAgCXNjcnVidmFsID0gc2NydWJyYXRlc1tpXS5zY3J1YnZhbDsK PiAgCj4gLQlpZiAocHZ0LT5mYW0gPT0gMHgxNykgewo+ICsJaWYgKHB2dC0+ZmFtID09IDB4MTcg fHwgcHZ0LT5mYW0gPT0gMHgxOCkgewo+ICAJCV9fZjE3aF9zZXRfc2NydWJ2YWwocHZ0LCBzY3J1 YnZhbCk7Cj4gIAl9IGVsc2UgaWYgKHB2dC0+ZmFtID09IDB4MTUgJiYgcHZ0LT5tb2RlbCA9PSAw eDYwKSB7Cj4gIAkJZjE1aF9zZWxlY3RfZGN0KHB2dCwgMCk7Cj4gQEAgLTI2NCw2ICsyNjQsNyBA QCBzdGF0aWMgaW50IGdldF9zY3J1Yl9yYXRlKHN0cnVjdCBtZW1fY3RsX2luZm8gKm1jaSkKPiAg CQlicmVhazsKPiAgCj4gIAljYXNlIDB4MTc6Cj4gKwljYXNlIDB4MTg6Cj4gIAkJYW1kNjRfcmVh ZF9wY2lfY2ZnKHB2dC0+RjYsIEYxN0hfU0NSX0JBU0VfQUREUiwgJnNjcnVidmFsKTsKPiAgCQlp ZiAoc2NydWJ2YWwgJiBCSVQoMCkpIHsKPiAgCQkJYW1kNjRfcmVhZF9wY2lfY2ZnKHB2dC0+RjYs IEYxN0hfU0NSX0xJTUlUX0FERFIsICZzY3J1YnZhbCk7Cj4gQEAgLTEwNDQsNiArMTA0NSw3IEBA IHN0YXRpYyB2b2lkIGRldGVybWluZV9tZW1vcnlfdHlwZShzdHJ1Y3QgYW1kNjRfcHZ0ICpwdnQp Cj4gIAkJZ290byBkZHIzOwo+ICAKPiAgCWNhc2UgMHgxNzoKPiArCWNhc2UgMHgxODoKPiAgCQlp ZiAoKHB2dC0+dW1jWzBdLmRpbW1fY2ZnIHwgcHZ0LT51bWNbMV0uZGltbV9jZmcpICYgQklUKDUp KQo+ICAJCQlwdnQtPmRyYW1fdHlwZSA9IE1FTV9MUkREUjQ7Cj4gIAkJZWxzZSBpZiAoKHB2dC0+ dW1jWzBdLmRpbW1fY2ZnIHwgcHZ0LT51bWNbMV0uZGltbV9jZmcpICYgQklUKDQpKQo+IEBAIC0y MjAwLDYgKzIyMDIsMTYgQEAgc3RhdGljIHN0cnVjdCBhbWQ2NF9mYW1pbHlfdHlwZSBmYW1pbHlf dHlwZXNbXSA9IHsKPiAgCQkJLmRiYW1fdG9fY3MJCT0gZjE3X2Jhc2VfYWRkcl90b19jc19zaXpl LAo+ICAJCX0KPiAgCX0sCj4gKwlbSFlHT05fRjE4X0NQVVNdID0gewo+ICsJCS8qIEh5Z29uIEYx OGggdXNlcyB0aGUgc2FtZSBBTUQgRjE3aCBzdXBwb3J0ICovCj4gKwkJLmN0bF9uYW1lID0gIkh5 Z29uX0YxOGgiLAo+ICsJCS5mMF9pZCA9IFBDSV9ERVZJQ0VfSURfSFlHT05fMThIX0RGX0YwLAo+ ICsJCS5mNl9pZCA9IFBDSV9ERVZJQ0VfSURfSFlHT05fMThIX0RGX0Y2LAo+ICsJCS5vcHMgPSB7 Cj4gKwkJCS5lYXJseV9jaGFubmVsX2NvdW50CT0gZjE3X2Vhcmx5X2NoYW5uZWxfY291bnQsCj4g KwkJCS5kYmFtX3RvX2NzCQk9IGYxN19iYXNlX2FkZHJfdG9fY3Nfc2l6ZSwKPiArCQl9Cj4gKwl9 LAo+ICB9Owo+ICAKPiAgLyoKPiBAQCAtMzE5Miw2ICszMjA0LDExIEBAIHN0YXRpYyBzdHJ1Y3Qg YW1kNjRfZmFtaWx5X3R5cGUgKnBlcl9mYW1pbHlfaW5pdChzdHJ1Y3QgYW1kNjRfcHZ0ICpwdnQp Cj4gIAkJcHZ0LT5vcHMJPSAmZmFtaWx5X3R5cGVzW0YxN19DUFVTXS5vcHM7Cj4gIAkJYnJlYWs7 Cj4gIAo+ICsJY2FzZSAweDE4Ogo+ICsJCWZhbV90eXBlCT0gJmZhbWlseV90eXBlc1tIWUdPTl9G MThfQ1BVU107Cj4gKwkJcHZ0LT5vcHMJPSAmZmFtaWx5X3R5cGVzW0hZR09OX0YxOF9DUFVTXS5v cHM7Cj4gKwkJYnJlYWs7Cj4gKwoKWW91IGNhbiB1c2UgdGhlIEYxN19DUFVTIGFycmF5IGVsZW1l bnQgaGVyZSBhbmQgb3ZlcndyaXRlIHRoZSAtPmN0bF9uYW1lCnN0cmluZyBvbmx5LiBObyBuZWVk IHRvIGRlZmluZSBbSFlHT05fRjE4X0NQVVNdIGFib3ZlLi4uIHlldC4KCj4gIAlkZWZhdWx0Ogo+ ICAJCWFtZDY0X2VycigiVW5zdXBwb3J0ZWQgZmFtaWx5IVxuIik7Cj4gIAkJcmV0dXJuIE5VTEw7 Cj4gQEAgLTM0MjgsNiArMzQ0NSw3IEBAIHN0YXRpYyBjb25zdCBzdHJ1Y3QgeDg2X2NwdV9pZCBh bWQ2NF9jcHVpZHNbXSA9IHsKPiAgCXsgWDg2X1ZFTkRPUl9BTUQsIDB4MTUsIFg4Nl9NT0RFTF9B TlksCVg4Nl9GRUFUVVJFX0FOWSwgMCB9LAo+ICAJeyBYODZfVkVORE9SX0FNRCwgMHgxNiwgWDg2 X01PREVMX0FOWSwJWDg2X0ZFQVRVUkVfQU5ZLCAwIH0sCj4gIAl7IFg4Nl9WRU5ET1JfQU1ELCAw eDE3LCBYODZfTU9ERUxfQU5ZLAlYODZfRkVBVFVSRV9BTlksIDAgfSwKPiArCXsgWDg2X1ZFTkRP Ul9IWUdPTiwgMHgxOCwgWDg2X01PREVMX0FOWSwgWDg2X0ZFQVRVUkVfQU5ZLCAwIH0sCj4gIAl7 IH0KPiAgfTsKPiAgTU9EVUxFX0RFVklDRV9UQUJMRSh4ODZjcHUsIGFtZDY0X2NwdWlkcyk7Cj4g ZGlmZiAtLWdpdCBhL2RyaXZlcnMvZWRhYy9hbWQ2NF9lZGFjLmggYi9kcml2ZXJzL2VkYWMvYW1k NjRfZWRhYy5oCj4gaW5kZXggMWQ0Yjc0ZS4uNmU1ZjYwOSAxMDA2NDQKPiAtLS0gYS9kcml2ZXJz L2VkYWMvYW1kNjRfZWRhYy5oCj4gKysrIGIvZHJpdmVycy9lZGFjL2FtZDY0X2VkYWMuaAo+IEBA IC0xMTYsNiArMTE2LDkgQEAKPiAgI2RlZmluZSBQQ0lfREVWSUNFX0lEX0FNRF8xN0hfREZfRjAJ MHgxNDYwCj4gICNkZWZpbmUgUENJX0RFVklDRV9JRF9BTURfMTdIX0RGX0Y2CTB4MTQ2Ngo+ICAK PiArI2RlZmluZSBQQ0lfREVWSUNFX0lEX0hZR09OXzE4SF9ERl9GMAkweDE0NjAKPiArI2RlZmlu ZSBQQ0lfREVWSUNFX0lEX0hZR09OXzE4SF9ERl9GNgkweDE0NjYKCkFzIGluIHRoZSBwcmV2aW91 cyBwYXRjaCAtIHVzZSB0aGUgQU1EIGRlZmluZXMuCg==