From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jacob Pan Subject: Re: [PATCH v2 03/40] iommu/sva: Manage process address spaces Date: Wed, 5 Sep 2018 11:18:35 -0700 Message-ID: <20180905111835.7f3ae40e@jacob-builder> References: <20180511190641.23008-1-jean-philippe.brucker@arm.com> <20180511190641.23008-4-jean-philippe.brucker@arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org Errors-To: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org To: Auger Eric Cc: xieyisheng1-hv44wF8Li93QT0dZR+AlfA@public.gmane.org, ilias.apalodimas-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org, kvm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, xuzaibo-hv44wF8Li93QT0dZR+AlfA@public.gmane.org, will.deacon-5wv7dgnIgG8@public.gmane.org, okaya-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, linux-mm-Bw31MaZKKs3YtjvyW6yDsg@public.gmane.org, ashok.raj-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org, Jean-Philippe Brucker , linux-acpi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, rfranz-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, kevin.tian-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org, rgummal-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, dwmw2-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org, liubo95-hv44wF8Li93QT0dZR+AlfA@public.gmane.org, alex.williamson-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org, iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org, robin.murphy-5wv7dgnIgG8@public.gmane.org, christian.koenig-5C7GfCeVMHo@public.gmane.org List-Id: linux-acpi@vger.kernel.org On Wed, 5 Sep 2018 14:14:12 +0200 Auger Eric wrote: > > + * > > + * On Arm and AMD IOMMUs, entry 0 of the PASID table can be used > > to hold > > + * non-PASID translations. In this case PASID 0 is reserved and > > entry 0 points > > + * to the io_pgtable base. On Intel IOMMU, the io_pgtable base > > would be held in > > + * the device table and PASID 0 would be available to the > > allocator. > > + */ > very nice explanation With the new Vt-d 3.0 spec., 2nd level IO page table base is no longer held in the device context table. Instead it is held in the PASID table entry pointed by the RID_PASID field in the device context entry. If RID_PASID = 0, then it is the same as ARM and AMD IOMMUs. You can refer to ch3.4.3 of the VT-d spec. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Date: Wed, 5 Sep 2018 11:18:35 -0700 From: Jacob Pan To: Auger Eric Cc: Jean-Philippe Brucker , linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, linux-acpi@vger.kernel.org, devicetree@vger.kernel.org, iommu@lists.linux-foundation.org, kvm@vger.kernel.org, linux-mm@kvack.org, xieyisheng1@huawei.com, liubo95@huawei.com, xuzaibo@huawei.com, thunder.leizhen@huawei.com, will.deacon@arm.com, okaya@codeaurora.org, yi.l.liu@intel.com, ashok.raj@intel.com, tn@semihalf.com, joro@8bytes.org, bharatku@xilinx.com, liudongdong3@huawei.com, rfranz@cavium.com, kevin.tian@intel.com, jcrouse@codeaurora.org, rgummal@xilinx.com, jonathan.cameron@huawei.com, shunyong.yang@hxt-semitech.com, robin.murphy@arm.com, ilias.apalodimas@linaro.org, alex.williamson@redhat.com, robdclark@gmail.com, dwmw2@infradead.org, christian.koenig@amd.com, nwatters@codeaurora.org, baolu.lu@linux.intel.com, jacob.jun.pan@linux.intel.com Subject: Re: [PATCH v2 03/40] iommu/sva: Manage process address spaces Message-ID: <20180905111835.7f3ae40e@jacob-builder> In-Reply-To: References: <20180511190641.23008-1-jean-philippe.brucker@arm.com> <20180511190641.23008-4-jean-philippe.brucker@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Sender: linux-acpi-owner@vger.kernel.org List-ID: On Wed, 5 Sep 2018 14:14:12 +0200 Auger Eric wrote: > > + * > > + * On Arm and AMD IOMMUs, entry 0 of the PASID table can be used > > to hold > > + * non-PASID translations. In this case PASID 0 is reserved and > > entry 0 points > > + * to the io_pgtable base. On Intel IOMMU, the io_pgtable base > > would be held in > > + * the device table and PASID 0 would be available to the > > allocator. > > + */ > very nice explanation With the new Vt-d 3.0 spec., 2nd level IO page table base is no longer held in the device context table. Instead it is held in the PASID table entry pointed by the RID_PASID field in the device context entry. If RID_PASID = 0, then it is the same as ARM and AMD IOMMUs. You can refer to ch3.4.3 of the VT-d spec. From mboxrd@z Thu Jan 1 00:00:00 1970 From: jacob.jun.pan@linux.intel.com (Jacob Pan) Date: Wed, 5 Sep 2018 11:18:35 -0700 Subject: [PATCH v2 03/40] iommu/sva: Manage process address spaces In-Reply-To: References: <20180511190641.23008-1-jean-philippe.brucker@arm.com> <20180511190641.23008-4-jean-philippe.brucker@arm.com> Message-ID: <20180905111835.7f3ae40e@jacob-builder> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Wed, 5 Sep 2018 14:14:12 +0200 Auger Eric wrote: > > + * > > + * On Arm and AMD IOMMUs, entry 0 of the PASID table can be used > > to hold > > + * non-PASID translations. In this case PASID 0 is reserved and > > entry 0 points > > + * to the io_pgtable base. On Intel IOMMU, the io_pgtable base > > would be held in > > + * the device table and PASID 0 would be available to the > > allocator. > > + */ > very nice explanation With the new Vt-d 3.0 spec., 2nd level IO page table base is no longer held in the device context table. Instead it is held in the PASID table entry pointed by the RID_PASID field in the device context entry. If RID_PASID = 0, then it is the same as ARM and AMD IOMMUs. You can refer to ch3.4.3 of the VT-d spec.