From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [v5,2/7] dmaengine: xilinx_dma: in axidma slave_sg and dma_cyclic mode align split descriptors From: Andrea Merello Message-Id: <20180907062502.8241-2-andrea.merello@gmail.com> Date: Fri, 7 Sep 2018 08:24:57 +0200 To: vkoul@kernel.org, dan.j.williams@intel.com, michal.simek@xilinx.com, appana.durga.rao@xilinx.com, dmaengine@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, radhey.shyam.pandey@xilinx.com, Andrea Merello List-ID: V2hlbmV2ZXIgYSBzaW5nbGUgb3IgY3ljbGljIHRyYW5zYWN0aW9uIGlzIHByZXBhcmVkLCB0aGUg ZHJpdmVyCmNvdWxkIGV2ZW50dWFsbHkgc3BsaXQgaXQgb3ZlciBzZXZlcmFsIFNHIGRlc2NyaXB0 b3JzIGluIG9yZGVyCnRvIGRlYWwgd2l0aCB0aGUgSFcgbWF4aW11bSB0cmFuc2ZlciBsZW5ndGgu CgpUaGlzIGNvdWxkIGVuZCB1cCBpbiBETUEgb3BlcmF0aW9ucyBzdGFydGluZyBmcm9tIGEgbWlz YWxpZ25lZAphZGRyZXNzLiBUaGlzIHNlZW1zIGZhdGFsIGZvciB0aGUgSFcgaWYgRFJFIChEYXRh IFJlYWxpZ25tZW50IEVuZ2luZSkKaXMgbm90IGVuYWJsZWQuCgpUaGlzIHBhdGNoIGV2ZW50dWFs bHkgYWRqdXN0cyB0aGUgdHJhbnNmZXIgc2l6ZSBpbiBvcmRlciB0byBtYWtlIHN1cmUKYWxsIG9w ZXJhdGlvbnMgc3RhcnQgZnJvbSBhbiBhbGlnbmVkIGFkZHJlc3MuCgpDYzogUmFkaGV5IFNoeWFt IFBhbmRleSA8cmFkaGV5LnNoeWFtLnBhbmRleUB4aWxpbnguY29tPgpTaWduZWQtb2ZmLWJ5OiBB bmRyZWEgTWVyZWxsbyA8YW5kcmVhLm1lcmVsbG9AZ21haWwuY29tPgpSZXZpZXdlZC1ieTogUmFk aGV5IFNoeWFtIFBhbmRleSA8cmFkaGV5LnNoeWFtLnBhbmRleUB4aWxpbnguY29tPgotLS0KQ2hh bmdlcyBpbiB2MjoKICAgICAgICAtIGRvbid0IGludHJvZHVjZSBjb3B5X21hc2sgZmllbGQsIHJh dGhlciByZWx5IG9uIGFscmVhZHktZXNpc3RlbnQKICAgICAgICAgIGNvcHlfYWxpZ24gZmllbGQu IFN1Z2dlc3RlZCBieSBSYWRoZXkgU2h5YW0gUGFuZGV5CiAgICAgICAgLSByZXdvcmQgdGl0bGUK Q2hhbmdlcyBpbiB2MzoKCS0gZml4IGJ1ZyBpbnRyb2R1Y2VkIGluIHYyOiB3cm9uZyBjb3B5IHNp emUgd2hlbiBEUkUgaXMgZW5hYmxlZAoJLSB1c2UgaW1wbGVtZW50YXRpb24gc3VnZ2VzdGVkIGJ5 IFJhZGhleSBTaHlhbSBQYW5kZXkKQ2hhbmdlcyBpbiB2NDoKCS0gcmV3b3JrIG9uIHRoZSB0b3Ag b2YgMS82CkNoYW5nZXMgaW4gdjU6CgktIGZpeCB0eXBvIGluIGNvbW1pdCB0aXRsZQoJLSBhZGQg aGludCBhYm91dCAiRFJFIiBtZWFuaW5nIGluIGNvbW1pdCBtZXNzYWdlCi0tLQogZHJpdmVycy9k bWEveGlsaW54L3hpbGlueF9kbWEuYyB8IDIyICsrKysrKysrKysrKysrKysrKy0tLS0KIDEgZmls ZSBjaGFuZ2VkLCAxOCBpbnNlcnRpb25zKCspLCA0IGRlbGV0aW9ucygtKQoKZGlmZiAtLWdpdCBh L2RyaXZlcnMvZG1hL3hpbGlueC94aWxpbnhfZG1hLmMgYi9kcml2ZXJzL2RtYS94aWxpbngveGls aW54X2RtYS5jCmluZGV4IGEzYWFhMGUzNGNjNy4uYWFhNmRlOGE3MGU0IDEwMDY0NAotLS0gYS9k cml2ZXJzL2RtYS94aWxpbngveGlsaW54X2RtYS5jCisrKyBiL2RyaXZlcnMvZG1hL3hpbGlueC94 aWxpbnhfZG1hLmMKQEAgLTk1NCwxNSArOTU0LDI4IEBAIHN0YXRpYyBpbnQgeGlsaW54X2RtYV9h bGxvY19jaGFuX3Jlc291cmNlcyhzdHJ1Y3QgZG1hX2NoYW4gKmRjaGFuKQogCiAvKioKICAqIHhp bGlueF9kbWFfY2FsY19jb3B5c2l6ZSAtIENhbGN1bGF0ZSB0aGUgYW1vdW50IG9mIGRhdGEgdG8g Y29weQorICogQGNoYW46IERyaXZlciBzcGVjaWZpYyBETUEgY2hhbm5lbAogICogQHNpemU6IFRv dGFsIGRhdGEgdGhhdCBuZWVkcyB0byBiZSBjb3BpZWQKICAqIEBkb25lOiBBbW91bnQgb2YgZGF0 YSB0aGF0IGhhcyBiZWVuIGFscmVhZHkgY29waWVkCiAgKgogICogUmV0dXJuOiBBbW91bnQgb2Yg ZGF0YSB0aGF0IGhhcyB0byBiZSBjb3BpZWQKICAqLwotc3RhdGljIGludCB4aWxpbnhfZG1hX2Nh bGNfY29weXNpemUoaW50IHNpemUsIGludCBkb25lKQorc3RhdGljIGludCB4aWxpbnhfZG1hX2Nh bGNfY29weXNpemUoc3RydWN0IHhpbGlueF9kbWFfY2hhbiAqY2hhbiwKKwkJCQkgICAgaW50IHNp emUsIGludCBkb25lKQogewotCXJldHVybiBtaW5fdChzaXplX3QsIHNpemUgLSBkb25lLAorCXNp emVfdCBjb3B5ID0gbWluX3Qoc2l6ZV90LCBzaXplIC0gZG9uZSwKIAkJICAgICBYSUxJTlhfRE1B X01BWF9UUkFOU19MRU4pOworCisJaWYgKChjb3B5ICsgZG9uZSA8IHNpemUpICYmCisJICAgIGNo YW4tPnhkZXYtPmNvbW1vbi5jb3B5X2FsaWduKSB7CisJCS8qCisJCSAqIElmIHRoaXMgaXMgbm90 IHRoZSBsYXN0IGRlc2NyaXB0b3IsIG1ha2Ugc3VyZQorCQkgKiB0aGUgbmV4dCBvbmUgd2lsbCBi ZSBwcm9wZXJseSBhbGlnbmVkCisJCSAqLworCQljb3B5ID0gcm91bmRkb3duKGNvcHksCisJCQkJ ICgxIDw8IGNoYW4tPnhkZXYtPmNvbW1vbi5jb3B5X2FsaWduKSk7CisJfQorCXJldHVybiBjb3B5 OwogfQogCiAvKioKQEAgLTE4MDQsNyArMTgxNyw3IEBAIHN0YXRpYyBzdHJ1Y3QgZG1hX2FzeW5j X3R4X2Rlc2NyaXB0b3IgKnhpbGlueF9kbWFfcHJlcF9zbGF2ZV9zZygKIAkJCSAqIENhbGN1bGF0 ZSB0aGUgbWF4aW11bSBudW1iZXIgb2YgYnl0ZXMgdG8gdHJhbnNmZXIsCiAJCQkgKiBtYWtpbmcg c3VyZSBpdCBpcyBsZXNzIHRoYW4gdGhlIGh3IGxpbWl0CiAJCQkgKi8KLQkJCWNvcHkgPSB4aWxp bnhfZG1hX2NhbGNfY29weXNpemUoc2dfZG1hX2xlbihzZyksCisJCQljb3B5ID0geGlsaW54X2Rt YV9jYWxjX2NvcHlzaXplKGNoYW4sIHNnX2RtYV9sZW4oc2cpLAogCQkJCQkJCXNnX3VzZWQpOwog CQkJaHcgPSAmc2VnbWVudC0+aHc7CiAKQEAgLTE5MDksNyArMTkyMiw4IEBAIHN0YXRpYyBzdHJ1 Y3QgZG1hX2FzeW5jX3R4X2Rlc2NyaXB0b3IgKnhpbGlueF9kbWFfcHJlcF9kbWFfY3ljbGljKAog CQkJICogQ2FsY3VsYXRlIHRoZSBtYXhpbXVtIG51bWJlciBvZiBieXRlcyB0byB0cmFuc2ZlciwK IAkJCSAqIG1ha2luZyBzdXJlIGl0IGlzIGxlc3MgdGhhbiB0aGUgaHcgbGltaXQKIAkJCSAqLwot CQkJY29weSA9IHhpbGlueF9kbWFfY2FsY19jb3B5c2l6ZShwZXJpb2RfbGVuLCBzZ191c2VkKTsK KwkJCWNvcHkgPSB4aWxpbnhfZG1hX2NhbGNfY29weXNpemUoY2hhbiwKKwkJCQkJCQlwZXJpb2Rf bGVuLCBzZ191c2VkKTsKIAkJCWh3ID0gJnNlZ21lbnQtPmh3OwogCQkJeGlsaW54X2F4aWRtYV9i dWYoY2hhbiwgaHcsIGJ1Zl9hZGRyLCBzZ191c2VkLAogCQkJCQkgIHBlcmlvZF9sZW4gKiBpKTsK From mboxrd@z Thu Jan 1 00:00:00 1970 From: andrea.merello@gmail.com (Andrea Merello) Date: Fri, 7 Sep 2018 08:24:57 +0200 Subject: [PATCH v5 2/7] dmaengine: xilinx_dma: in axidma slave_sg and dma_cyclic mode align split descriptors In-Reply-To: <20180907062502.8241-1-andrea.merello@gmail.com> References: <20180907062502.8241-1-andrea.merello@gmail.com> Message-ID: <20180907062502.8241-2-andrea.merello@gmail.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Whenever a single or cyclic transaction is prepared, the driver could eventually split it over several SG descriptors in order to deal with the HW maximum transfer length. This could end up in DMA operations starting from a misaligned address. This seems fatal for the HW if DRE (Data Realignment Engine) is not enabled. This patch eventually adjusts the transfer size in order to make sure all operations start from an aligned address. Cc: Radhey Shyam Pandey Signed-off-by: Andrea Merello Reviewed-by: Radhey Shyam Pandey --- Changes in v2: - don't introduce copy_mask field, rather rely on already-esistent copy_align field. Suggested by Radhey Shyam Pandey - reword title Changes in v3: - fix bug introduced in v2: wrong copy size when DRE is enabled - use implementation suggested by Radhey Shyam Pandey Changes in v4: - rework on the top of 1/6 Changes in v5: - fix typo in commit title - add hint about "DRE" meaning in commit message --- drivers/dma/xilinx/xilinx_dma.c | 22 ++++++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c index a3aaa0e34cc7..aaa6de8a70e4 100644 --- a/drivers/dma/xilinx/xilinx_dma.c +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -954,15 +954,28 @@ static int xilinx_dma_alloc_chan_resources(struct dma_chan *dchan) /** * xilinx_dma_calc_copysize - Calculate the amount of data to copy + * @chan: Driver specific DMA channel * @size: Total data that needs to be copied * @done: Amount of data that has been already copied * * Return: Amount of data that has to be copied */ -static int xilinx_dma_calc_copysize(int size, int done) +static int xilinx_dma_calc_copysize(struct xilinx_dma_chan *chan, + int size, int done) { - return min_t(size_t, size - done, + size_t copy = min_t(size_t, size - done, XILINX_DMA_MAX_TRANS_LEN); + + if ((copy + done < size) && + chan->xdev->common.copy_align) { + /* + * If this is not the last descriptor, make sure + * the next one will be properly aligned + */ + copy = rounddown(copy, + (1 << chan->xdev->common.copy_align)); + } + return copy; } /** @@ -1804,7 +1817,7 @@ static struct dma_async_tx_descriptor *xilinx_dma_prep_slave_sg( * Calculate the maximum number of bytes to transfer, * making sure it is less than the hw limit */ - copy = xilinx_dma_calc_copysize(sg_dma_len(sg), + copy = xilinx_dma_calc_copysize(chan, sg_dma_len(sg), sg_used); hw = &segment->hw; @@ -1909,7 +1922,8 @@ static struct dma_async_tx_descriptor *xilinx_dma_prep_dma_cyclic( * Calculate the maximum number of bytes to transfer, * making sure it is less than the hw limit */ - copy = xilinx_dma_calc_copysize(period_len, sg_used); + copy = xilinx_dma_calc_copysize(chan, + period_len, sg_used); hw = &segment->hw; xilinx_axidma_buf(chan, hw, buf_addr, sg_used, period_len * i); -- 2.17.1 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andrea Merello Subject: [PATCH v5 2/7] dmaengine: xilinx_dma: in axidma slave_sg and dma_cyclic mode align split descriptors Date: Fri, 7 Sep 2018 08:24:57 +0200 Message-ID: <20180907062502.8241-2-andrea.merello@gmail.com> References: <20180907062502.8241-1-andrea.merello@gmail.com> Return-path: In-Reply-To: <20180907062502.8241-1-andrea.merello@gmail.com> Sender: linux-kernel-owner@vger.kernel.org To: vkoul@kernel.org, dan.j.williams@intel.com, michal.simek@xilinx.com, appana.durga.rao@xilinx.com, dmaengine@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, radhey.shyam.pandey@xilinx.com, Andrea Merello List-Id: devicetree@vger.kernel.org Whenever a single or cyclic transaction is prepared, the driver could eventually split it over several SG descriptors in order to deal with the HW maximum transfer length. This could end up in DMA operations starting from a misaligned address. This seems fatal for the HW if DRE (Data Realignment Engine) is not enabled. This patch eventually adjusts the transfer size in order to make sure all operations start from an aligned address. Cc: Radhey Shyam Pandey Signed-off-by: Andrea Merello Reviewed-by: Radhey Shyam Pandey --- Changes in v2: - don't introduce copy_mask field, rather rely on already-esistent copy_align field. Suggested by Radhey Shyam Pandey - reword title Changes in v3: - fix bug introduced in v2: wrong copy size when DRE is enabled - use implementation suggested by Radhey Shyam Pandey Changes in v4: - rework on the top of 1/6 Changes in v5: - fix typo in commit title - add hint about "DRE" meaning in commit message --- drivers/dma/xilinx/xilinx_dma.c | 22 ++++++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c index a3aaa0e34cc7..aaa6de8a70e4 100644 --- a/drivers/dma/xilinx/xilinx_dma.c +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -954,15 +954,28 @@ static int xilinx_dma_alloc_chan_resources(struct dma_chan *dchan) /** * xilinx_dma_calc_copysize - Calculate the amount of data to copy + * @chan: Driver specific DMA channel * @size: Total data that needs to be copied * @done: Amount of data that has been already copied * * Return: Amount of data that has to be copied */ -static int xilinx_dma_calc_copysize(int size, int done) +static int xilinx_dma_calc_copysize(struct xilinx_dma_chan *chan, + int size, int done) { - return min_t(size_t, size - done, + size_t copy = min_t(size_t, size - done, XILINX_DMA_MAX_TRANS_LEN); + + if ((copy + done < size) && + chan->xdev->common.copy_align) { + /* + * If this is not the last descriptor, make sure + * the next one will be properly aligned + */ + copy = rounddown(copy, + (1 << chan->xdev->common.copy_align)); + } + return copy; } /** @@ -1804,7 +1817,7 @@ static struct dma_async_tx_descriptor *xilinx_dma_prep_slave_sg( * Calculate the maximum number of bytes to transfer, * making sure it is less than the hw limit */ - copy = xilinx_dma_calc_copysize(sg_dma_len(sg), + copy = xilinx_dma_calc_copysize(chan, sg_dma_len(sg), sg_used); hw = &segment->hw; @@ -1909,7 +1922,8 @@ static struct dma_async_tx_descriptor *xilinx_dma_prep_dma_cyclic( * Calculate the maximum number of bytes to transfer, * making sure it is less than the hw limit */ - copy = xilinx_dma_calc_copysize(period_len, sg_used); + copy = xilinx_dma_calc_copysize(chan, + period_len, sg_used); hw = &segment->hw; xilinx_axidma_buf(chan, hw, buf_addr, sg_used, period_len * i); -- 2.17.1