From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [v5,3/7] dt-bindings: dmaengine: xilinx_dma: add optional xlnx,sg-length-width property From: Andrea Merello Message-Id: <20180907062502.8241-3-andrea.merello@gmail.com> Date: Fri, 7 Sep 2018 08:24:58 +0200 To: vkoul@kernel.org, dan.j.williams@intel.com, michal.simek@xilinx.com, appana.durga.rao@xilinx.com, dmaengine@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, radhey.shyam.pandey@xilinx.com, Andrea Merello List-ID: VGhlIHdpZHRoIG9mIHRoZSAibGVuZ3RoIHJlZ2lzdGVyIiBjYW5ub3QgYmUgYXV0b2RldGVjdGVk LCBhbmQgaXQgaXMgbm93CnNwZWNpZmllZCB3aXRoIGEgRFQgcHJvcGVydHkuIEFkZCBkb2N1bWVu dGF0aW9uIGZvciBpdC4KCkNjOiBSb2IgSGVycmluZyA8cm9iaCtkdEBrZXJuZWwub3JnPgpDYzog TWFyayBSdXRsYW5kIDxtYXJrLnJ1dGxhbmRAYXJtLmNvbT4KQ2M6IGRldmljZXRyZWVAdmdlci5r ZXJuZWwub3JnCkNjOiBSYWRoZXkgU2h5YW0gUGFuZGV5IDxyYWRoZXkuc2h5YW0ucGFuZGV5QHhp bGlueC5jb20+ClNpZ25lZC1vZmYtYnk6IEFuZHJlYSBNZXJlbGxvIDxhbmRyZWEubWVyZWxsb0Bn bWFpbC5jb20+ClJldmlld2VkLWJ5OiBSYWRoZXkgU2h5YW0gUGFuZGV5IDxyYWRoZXkuc2h5YW0u cGFuZGV5QHhpbGlueC5jb20+Ci0tLQpDaGFuZ2VzIGluIHYyOgoJLSBjaGFuZ2UgcHJvcGVydHkg bmFtZQoJLSBwcm9wZXJ0eSBpcyBub3cgb3B0aW9uYWwKCS0gY2MgRFQgbWFpbnRhaW5lcgpDaGFu Z2VzIGluIHYzOgoJLSByZXdvcmQKCS0gY2MgRFQgbWFpbnRhaW5lclMgYW5kIE1MCkNoYW5nZXMg aW4gdjQ6CgktIHNwZWNpZnkgdGhlIHVuaXQsIHRoZSB2YWxpZCByYW5nZSBhbmQgdGhlIGRlZmF1 bHQgdmFsdWUKQ2hhbmdlcyBpbiB2NToKCS0gY29tbWl0IG1lc3NhZ2UgdHJpdmlhbCBmaXgKCS0g Zml4IHNwYWNlcyBiZWZvcmUgdGFiCi0tLQogRG9jdW1lbnRhdGlvbi9kZXZpY2V0cmVlL2JpbmRp bmdzL2RtYS94aWxpbngveGlsaW54X2RtYS50eHQgfCA0ICsrKysKIDEgZmlsZSBjaGFuZ2VkLCA0 IGluc2VydGlvbnMoKykKCmRpZmYgLS1naXQgYS9Eb2N1bWVudGF0aW9uL2RldmljZXRyZWUvYmlu ZGluZ3MvZG1hL3hpbGlueC94aWxpbnhfZG1hLnR4dCBiL0RvY3VtZW50YXRpb24vZGV2aWNldHJl ZS9iaW5kaW5ncy9kbWEveGlsaW54L3hpbGlueF9kbWEudHh0CmluZGV4IGEyYjhiZmFlYzQzYy4u NWRmNGVhYzczMDBjIDEwMDY0NAotLS0gYS9Eb2N1bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGlu Z3MvZG1hL3hpbGlueC94aWxpbnhfZG1hLnR4dAorKysgYi9Eb2N1bWVudGF0aW9uL2RldmljZXRy ZWUvYmluZGluZ3MvZG1hL3hpbGlueC94aWxpbnhfZG1hLnR4dApAQCAtNDEsNiArNDEsMTAgQEAg T3B0aW9uYWwgcHJvcGVydGllczoKIC0geGxueCxpbmNsdWRlLXNnOiBUZWxscyBjb25maWd1cmVk IGZvciBTY2F0dGVyLW1vZGUgaW4KIAl0aGUgaGFyZHdhcmUuCiBPcHRpb25hbCBwcm9wZXJ0aWVz IGZvciBBWEkgRE1BOgorLSB4bG54LHNnLWxlbmd0aC13aWR0aDogU2hvdWxkIGJlIHNldCB0byB0 aGUgd2lkdGggaW4gYml0cyBvZiB0aGUgbGVuZ3RoCisJcmVnaXN0ZXIgYXMgY29uZmlndXJlZCBp biBoL3cuIFRha2VzIHZhbHVlcyB7OC4uLjI2fS4gSWYgdGhlIHByb3BlcnR5CisJaXMgbWlzc2lu ZyBvciBpbnZhbGlkIHRoZW4gdGhlIGRlZmF1bHQgdmFsdWUgMjMgaXMgdXNlZC4gVGhpcyBpcyB0 aGUKKwltYXhpbXVtIHZhbHVlIHRoYXQgaXMgc3VwcG9ydGVkIGJ5IGFsbCBJUCB2ZXJzaW9ucy4K IC0geGxueCxtY2RtYTogVGVsbHMgd2hldGhlciBjb25maWd1cmVkIGZvciBtdWx0aS1jaGFubmVs IG1vZGUgaW4gdGhlIGhhcmR3YXJlLgogT3B0aW9uYWwgcHJvcGVydGllcyBmb3IgVkRNQToKIC0g eGxueCxmbHVzaC1mc3luYzogVGVsbHMgd2hpY2ggY2hhbm5lbCB0byBGbHVzaCBvbiBGcmFtZSBz eW5jLgo= From mboxrd@z Thu Jan 1 00:00:00 1970 From: andrea.merello@gmail.com (Andrea Merello) Date: Fri, 7 Sep 2018 08:24:58 +0200 Subject: [PATCH v5 3/7] dt-bindings: dmaengine: xilinx_dma: add optional xlnx, sg-length-width property In-Reply-To: <20180907062502.8241-1-andrea.merello@gmail.com> References: <20180907062502.8241-1-andrea.merello@gmail.com> Message-ID: <20180907062502.8241-3-andrea.merello@gmail.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org The width of the "length register" cannot be autodetected, and it is now specified with a DT property. Add documentation for it. Cc: Rob Herring Cc: Mark Rutland Cc: devicetree at vger.kernel.org Cc: Radhey Shyam Pandey Signed-off-by: Andrea Merello Reviewed-by: Radhey Shyam Pandey --- Changes in v2: - change property name - property is now optional - cc DT maintainer Changes in v3: - reword - cc DT maintainerS and ML Changes in v4: - specify the unit, the valid range and the default value Changes in v5: - commit message trivial fix - fix spaces before tab --- Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt index a2b8bfaec43c..5df4eac7300c 100644 --- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt +++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt @@ -41,6 +41,10 @@ Optional properties: - xlnx,include-sg: Tells configured for Scatter-mode in the hardware. Optional properties for AXI DMA: +- xlnx,sg-length-width: Should be set to the width in bits of the length + register as configured in h/w. Takes values {8...26}. If the property + is missing or invalid then the default value 23 is used. This is the + maximum value that is supported by all IP versions. - xlnx,mcdma: Tells whether configured for multi-channel mode in the hardware. Optional properties for VDMA: - xlnx,flush-fsync: Tells which channel to Flush on Frame sync. -- 2.17.1 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andrea Merello Subject: [PATCH v5 3/7] dt-bindings: dmaengine: xilinx_dma: add optional xlnx,sg-length-width property Date: Fri, 7 Sep 2018 08:24:58 +0200 Message-ID: <20180907062502.8241-3-andrea.merello@gmail.com> References: <20180907062502.8241-1-andrea.merello@gmail.com> Return-path: In-Reply-To: <20180907062502.8241-1-andrea.merello@gmail.com> Sender: linux-kernel-owner@vger.kernel.org To: vkoul@kernel.org, dan.j.williams@intel.com, michal.simek@xilinx.com, appana.durga.rao@xilinx.com, dmaengine@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, radhey.shyam.pandey@xilinx.com, Andrea Merello List-Id: devicetree@vger.kernel.org The width of the "length register" cannot be autodetected, and it is now specified with a DT property. Add documentation for it. Cc: Rob Herring Cc: Mark Rutland Cc: devicetree@vger.kernel.org Cc: Radhey Shyam Pandey Signed-off-by: Andrea Merello Reviewed-by: Radhey Shyam Pandey --- Changes in v2: - change property name - property is now optional - cc DT maintainer Changes in v3: - reword - cc DT maintainerS and ML Changes in v4: - specify the unit, the valid range and the default value Changes in v5: - commit message trivial fix - fix spaces before tab --- Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt index a2b8bfaec43c..5df4eac7300c 100644 --- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt +++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt @@ -41,6 +41,10 @@ Optional properties: - xlnx,include-sg: Tells configured for Scatter-mode in the hardware. Optional properties for AXI DMA: +- xlnx,sg-length-width: Should be set to the width in bits of the length + register as configured in h/w. Takes values {8...26}. If the property + is missing or invalid then the default value 23 is used. This is the + maximum value that is supported by all IP versions. - xlnx,mcdma: Tells whether configured for multi-channel mode in the hardware. Optional properties for VDMA: - xlnx,flush-fsync: Tells which channel to Flush on Frame sync. -- 2.17.1