From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [v5,7/7] dmaengine: xilinx_dma: Drop SG support for VDMA IP From: Andrea Merello Message-Id: <20180907062502.8241-7-andrea.merello@gmail.com> Date: Fri, 7 Sep 2018 08:25:02 +0200 To: vkoul@kernel.org, dan.j.williams@intel.com, michal.simek@xilinx.com, appana.durga.rao@xilinx.com, dmaengine@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, radhey.shyam.pandey@xilinx.com, Andrea Merello List-ID: eGlsaW54X3ZkbWFfc3RhcnRfdHJhbnNmZXIoKSBpcyB1c2VkIG9ubHkgZm9yIFZETUEgSVAsIHN0 aWxsIGl0IGNvbnRhaW5zCmNvbmRpdGlvbmFsIGNvZGUgb24gaGFzX3NnIHZhcmlhYmxlLiBoYXNf c2cgaXMgc2V0IG9ubHkgd2hlbmV2ZXIgdGhlIEhXCmRvZXMgc3VwcG9ydCBTRyBtb2RlLCB0aGF0 IGlzIG5ldmVyIHRydWUgZm9yIFZETUEgSVAuCgpUaGlzIHBhdGNoIGRyb3BzIHRoZSBuZXZlci10 YWtlbiBicmFuY2hlcy4KClNpZ25lZC1vZmYtYnk6IEFuZHJlYSBNZXJlbGxvIDxhbmRyZWEubWVy ZWxsb0BnbWFpbC5jb20+Ci0tLQpDaGFuZ2VzIGluIFY0OiBpbnRyb2R1Y2VkIHRoaXMgcGF0Y2gg aW4gc2VyaWVzCkNoYW5nZXMgaW4gdjU6CglOb25lCi0tLQogZHJpdmVycy9kbWEveGlsaW54L3hp bGlueF9kbWEuYyB8IDg0ICsrKysrKysrKysrKystLS0tLS0tLS0tLS0tLS0tLS0tLQogMSBmaWxl IGNoYW5nZWQsIDMyIGluc2VydGlvbnMoKyksIDUyIGRlbGV0aW9ucygtKQoKZGlmZiAtLWdpdCBh L2RyaXZlcnMvZG1hL3hpbGlueC94aWxpbnhfZG1hLmMgYi9kcml2ZXJzL2RtYS94aWxpbngveGls aW54X2RtYS5jCmluZGV4IDc4ZDBmMmY4MjI1ZS4uMDdjZWFkZWYwYTAwIDEwMDY0NAotLS0gYS9k cml2ZXJzL2RtYS94aWxpbngveGlsaW54X2RtYS5jCisrKyBiL2RyaXZlcnMvZG1hL3hpbGlueC94 aWxpbnhfZG1hLmMKQEAgLTEwOTMsNiArMTA5Myw4IEBAIHN0YXRpYyB2b2lkIHhpbGlueF92ZG1h X3N0YXJ0X3RyYW5zZmVyKHN0cnVjdCB4aWxpbnhfZG1hX2NoYW4gKmNoYW4pCiAJc3RydWN0IHhp bGlueF9kbWFfdHhfZGVzY3JpcHRvciAqZGVzYywgKnRhaWxfZGVzYzsKIAl1MzIgcmVnLCBqOwog CXN0cnVjdCB4aWxpbnhfdmRtYV90eF9zZWdtZW50ICp0YWlsX3NlZ21lbnQ7CisJc3RydWN0IHhp bGlueF92ZG1hX3R4X3NlZ21lbnQgKnNlZ21lbnQsICpsYXN0ID0gTlVMTDsKKwlpbnQgaSA9IDA7 CiAKIAkvKiBUaGlzIGZ1bmN0aW9uIHdhcyBpbnZva2VkIHdpdGggbG9jayBoZWxkICovCiAJaWYg KGNoYW4tPmVycikKQEAgLTExMTIsMTQgKzExMTQsNiBAQCBzdGF0aWMgdm9pZCB4aWxpbnhfdmRt YV9zdGFydF90cmFuc2ZlcihzdHJ1Y3QgeGlsaW54X2RtYV9jaGFuICpjaGFuKQogCXRhaWxfc2Vn bWVudCA9IGxpc3RfbGFzdF9lbnRyeSgmdGFpbF9kZXNjLT5zZWdtZW50cywKIAkJCQkgICAgICAg c3RydWN0IHhpbGlueF92ZG1hX3R4X3NlZ21lbnQsIG5vZGUpOwogCi0JLyoKLQkgKiBJZiBoYXJk d2FyZSBpcyBpZGxlLCB0aGVuIGFsbCBkZXNjcmlwdG9ycyBvbiB0aGUgcnVubmluZyBsaXN0cyBh cmUKLQkgKiBkb25lLCBzdGFydCBuZXcgdHJhbnNmZXJzCi0JICovCi0JaWYgKGNoYW4tPmhhc19z ZykKLQkJZG1hX2N0cmxfd3JpdGUoY2hhbiwgWElMSU5YX0RNQV9SRUdfQ1VSREVTQywKLQkJCQlk ZXNjLT5hc3luY190eC5waHlzKTsKLQogCS8qIENvbmZpZ3VyZSB0aGUgaGFyZHdhcmUgdXNpbmcg aW5mbyBpbiB0aGUgY29uZmlnIHN0cnVjdHVyZSAqLwogCXJlZyA9IGRtYV9jdHJsX3JlYWQoY2hh biwgWElMSU5YX0RNQV9SRUdfRE1BQ1IpOwogCkBAIC0xMTI4LDE1ICsxMTIyLDExIEBAIHN0YXRp YyB2b2lkIHhpbGlueF92ZG1hX3N0YXJ0X3RyYW5zZmVyKHN0cnVjdCB4aWxpbnhfZG1hX2NoYW4g KmNoYW4pCiAJZWxzZQogCQlyZWcgJj0gflhJTElOWF9ETUFfRE1BQ1JfRlJBTUVDTlRfRU47CiAK LQkvKgotCSAqIFdpdGggU0csIHN0YXJ0IHdpdGggY2lyY3VsYXIgbW9kZSwgc28gdGhhdCBCRHMg Y2FuIGJlIGZldGNoZWQuCi0JICogSW4gZGlyZWN0IHJlZ2lzdGVyIG1vZGUsIGlmIG5vdCBwYXJr aW5nLCBlbmFibGUgY2lyY3VsYXIgbW9kZQotCSAqLwotCWlmIChjaGFuLT5oYXNfc2cgfHwgIWNv bmZpZy0+cGFyaykKLQkJcmVnIHw9IFhJTElOWF9ETUFfRE1BQ1JfQ0lSQ19FTjsKLQorCS8qIElm IG5vdCBwYXJraW5nLCBlbmFibGUgY2lyY3VsYXIgbW9kZSAqLwogCWlmIChjb25maWctPnBhcmsp CiAJCXJlZyAmPSB+WElMSU5YX0RNQV9ETUFDUl9DSVJDX0VOOworCWVsc2UKKwkJcmVnIHw9IFhJ TElOWF9ETUFfRE1BQ1JfQ0lSQ19FTjsKIAogCWRtYV9jdHJsX3dyaXRlKGNoYW4sIFhJTElOWF9E TUFfUkVHX0RNQUNSLCByZWcpOwogCkBAIC0xMTU4LDQ4ICsxMTQ4LDM4IEBAIHN0YXRpYyB2b2lk IHhpbGlueF92ZG1hX3N0YXJ0X3RyYW5zZmVyKHN0cnVjdCB4aWxpbnhfZG1hX2NoYW4gKmNoYW4p CiAJCXJldHVybjsKIAogCS8qIFN0YXJ0IHRoZSB0cmFuc2ZlciAqLwotCWlmIChjaGFuLT5oYXNf c2cpIHsKLQkJZG1hX2N0cmxfd3JpdGUoY2hhbiwgWElMSU5YX0RNQV9SRUdfVEFJTERFU0MsCi0J CQkJdGFpbF9zZWdtZW50LT5waHlzKTsKLQkJbGlzdF9zcGxpY2VfdGFpbF9pbml0KCZjaGFuLT5w ZW5kaW5nX2xpc3QsICZjaGFuLT5hY3RpdmVfbGlzdCk7Ci0JCWNoYW4tPmRlc2NfcGVuZGluZ2Nv dW50ID0gMDsKLQl9IGVsc2UgewotCQlzdHJ1Y3QgeGlsaW54X3ZkbWFfdHhfc2VnbWVudCAqc2Vn bWVudCwgKmxhc3QgPSBOVUxMOwotCQlpbnQgaSA9IDA7Ci0KLQkJaWYgKGNoYW4tPmRlc2Nfc3Vi bWl0Y291bnQgPCBjaGFuLT5udW1fZnJtcykKLQkJCWkgPSBjaGFuLT5kZXNjX3N1Ym1pdGNvdW50 OwotCi0JCWxpc3RfZm9yX2VhY2hfZW50cnkoc2VnbWVudCwgJmRlc2MtPnNlZ21lbnRzLCBub2Rl KSB7Ci0JCQlpZiAoY2hhbi0+ZXh0X2FkZHIpCi0JCQkJdmRtYV9kZXNjX3dyaXRlXzY0KGNoYW4s Ci0JCQkJCVhJTElOWF9WRE1BX1JFR19TVEFSVF9BRERSRVNTXzY0KGkrKyksCi0JCQkJCXNlZ21l bnQtPmh3LmJ1Zl9hZGRyLAotCQkJCQlzZWdtZW50LT5ody5idWZfYWRkcl9tc2IpOwotCQkJZWxz ZQotCQkJCXZkbWFfZGVzY193cml0ZShjaGFuLAorCWlmIChjaGFuLT5kZXNjX3N1Ym1pdGNvdW50 IDwgY2hhbi0+bnVtX2ZybXMpCisJCWkgPSBjaGFuLT5kZXNjX3N1Ym1pdGNvdW50OworCisJbGlz dF9mb3JfZWFjaF9lbnRyeShzZWdtZW50LCAmZGVzYy0+c2VnbWVudHMsIG5vZGUpIHsKKwkJaWYg KGNoYW4tPmV4dF9hZGRyKQorCQkJdmRtYV9kZXNjX3dyaXRlXzY0KGNoYW4sCisJCQkJICAgWElM SU5YX1ZETUFfUkVHX1NUQVJUX0FERFJFU1NfNjQoaSsrKSwKKwkJCQkgICBzZWdtZW50LT5ody5i dWZfYWRkciwKKwkJCQkgICBzZWdtZW50LT5ody5idWZfYWRkcl9tc2IpOworCQllbHNlCisJCQl2 ZG1hX2Rlc2Nfd3JpdGUoY2hhbiwKIAkJCQkJWElMSU5YX1ZETUFfUkVHX1NUQVJUX0FERFJFU1Mo aSsrKSwKIAkJCQkJc2VnbWVudC0+aHcuYnVmX2FkZHIpOwogCi0JCQlsYXN0ID0gc2VnbWVudDsK LQkJfQotCi0JCWlmICghbGFzdCkKLQkJCXJldHVybjsKKwkJbGFzdCA9IHNlZ21lbnQ7CisJfQog Ci0JCS8qIEhXIGV4cGVjdHMgdGhlc2UgcGFyYW1ldGVycyB0byBiZSBzYW1lIGZvciBvbmUgdHJh bnNhY3Rpb24gKi8KLQkJdmRtYV9kZXNjX3dyaXRlKGNoYW4sIFhJTElOWF9ETUFfUkVHX0hTSVpF LCBsYXN0LT5ody5oc2l6ZSk7Ci0JCXZkbWFfZGVzY193cml0ZShjaGFuLCBYSUxJTlhfRE1BX1JF R19GUk1ETFlfU1RSSURFLAotCQkJCWxhc3QtPmh3LnN0cmlkZSk7Ci0JCXZkbWFfZGVzY193cml0 ZShjaGFuLCBYSUxJTlhfRE1BX1JFR19WU0laRSwgbGFzdC0+aHcudnNpemUpOworCWlmICghbGFz dCkKKwkJcmV0dXJuOwogCi0JCWNoYW4tPmRlc2Nfc3VibWl0Y291bnQrKzsKLQkJY2hhbi0+ZGVz Y19wZW5kaW5nY291bnQtLTsKLQkJbGlzdF9kZWwoJmRlc2MtPm5vZGUpOwotCQlsaXN0X2FkZF90 YWlsKCZkZXNjLT5ub2RlLCAmY2hhbi0+YWN0aXZlX2xpc3QpOwotCQlpZiAoY2hhbi0+ZGVzY19z dWJtaXRjb3VudCA9PSBjaGFuLT5udW1fZnJtcykKLQkJCWNoYW4tPmRlc2Nfc3VibWl0Y291bnQg PSAwOwotCX0KKwkvKiBIVyBleHBlY3RzIHRoZXNlIHBhcmFtZXRlcnMgdG8gYmUgc2FtZSBmb3Ig b25lIHRyYW5zYWN0aW9uICovCisJdmRtYV9kZXNjX3dyaXRlKGNoYW4sIFhJTElOWF9ETUFfUkVH X0hTSVpFLCBsYXN0LT5ody5oc2l6ZSk7CisJdmRtYV9kZXNjX3dyaXRlKGNoYW4sIFhJTElOWF9E TUFfUkVHX0ZSTURMWV9TVFJJREUsCisJCQlsYXN0LT5ody5zdHJpZGUpOworCXZkbWFfZGVzY193 cml0ZShjaGFuLCBYSUxJTlhfRE1BX1JFR19WU0laRSwgbGFzdC0+aHcudnNpemUpOworCisJY2hh bi0+ZGVzY19zdWJtaXRjb3VudCsrOworCWNoYW4tPmRlc2NfcGVuZGluZ2NvdW50LS07CisJbGlz dF9kZWwoJmRlc2MtPm5vZGUpOworCWxpc3RfYWRkX3RhaWwoJmRlc2MtPm5vZGUsICZjaGFuLT5h Y3RpdmVfbGlzdCk7CisJaWYgKGNoYW4tPmRlc2Nfc3VibWl0Y291bnQgPT0gY2hhbi0+bnVtX2Zy bXMpCisJCWNoYW4tPmRlc2Nfc3VibWl0Y291bnQgPSAwOwogCiAJY2hhbi0+aWRsZSA9IGZhbHNl OwogfQo= From mboxrd@z Thu Jan 1 00:00:00 1970 From: andrea.merello@gmail.com (Andrea Merello) Date: Fri, 7 Sep 2018 08:25:02 +0200 Subject: [PATCH v5 7/7] dmaengine: xilinx_dma: Drop SG support for VDMA IP In-Reply-To: <20180907062502.8241-1-andrea.merello@gmail.com> References: <20180907062502.8241-1-andrea.merello@gmail.com> Message-ID: <20180907062502.8241-7-andrea.merello@gmail.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org xilinx_vdma_start_transfer() is used only for VDMA IP, still it contains conditional code on has_sg variable. has_sg is set only whenever the HW does support SG mode, that is never true for VDMA IP. This patch drops the never-taken branches. Signed-off-by: Andrea Merello --- Changes in V4: introduced this patch in series Changes in v5: None --- drivers/dma/xilinx/xilinx_dma.c | 84 +++++++++++++-------------------- 1 file changed, 32 insertions(+), 52 deletions(-) diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c index 78d0f2f8225e..07ceadef0a00 100644 --- a/drivers/dma/xilinx/xilinx_dma.c +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -1093,6 +1093,8 @@ static void xilinx_vdma_start_transfer(struct xilinx_dma_chan *chan) struct xilinx_dma_tx_descriptor *desc, *tail_desc; u32 reg, j; struct xilinx_vdma_tx_segment *tail_segment; + struct xilinx_vdma_tx_segment *segment, *last = NULL; + int i = 0; /* This function was invoked with lock held */ if (chan->err) @@ -1112,14 +1114,6 @@ static void xilinx_vdma_start_transfer(struct xilinx_dma_chan *chan) tail_segment = list_last_entry(&tail_desc->segments, struct xilinx_vdma_tx_segment, node); - /* - * If hardware is idle, then all descriptors on the running lists are - * done, start new transfers - */ - if (chan->has_sg) - dma_ctrl_write(chan, XILINX_DMA_REG_CURDESC, - desc->async_tx.phys); - /* Configure the hardware using info in the config structure */ reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); @@ -1128,15 +1122,11 @@ static void xilinx_vdma_start_transfer(struct xilinx_dma_chan *chan) else reg &= ~XILINX_DMA_DMACR_FRAMECNT_EN; - /* - * With SG, start with circular mode, so that BDs can be fetched. - * In direct register mode, if not parking, enable circular mode - */ - if (chan->has_sg || !config->park) - reg |= XILINX_DMA_DMACR_CIRC_EN; - + /* If not parking, enable circular mode */ if (config->park) reg &= ~XILINX_DMA_DMACR_CIRC_EN; + else + reg |= XILINX_DMA_DMACR_CIRC_EN; dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); @@ -1158,48 +1148,38 @@ static void xilinx_vdma_start_transfer(struct xilinx_dma_chan *chan) return; /* Start the transfer */ - if (chan->has_sg) { - dma_ctrl_write(chan, XILINX_DMA_REG_TAILDESC, - tail_segment->phys); - list_splice_tail_init(&chan->pending_list, &chan->active_list); - chan->desc_pendingcount = 0; - } else { - struct xilinx_vdma_tx_segment *segment, *last = NULL; - int i = 0; - - if (chan->desc_submitcount < chan->num_frms) - i = chan->desc_submitcount; - - list_for_each_entry(segment, &desc->segments, node) { - if (chan->ext_addr) - vdma_desc_write_64(chan, - XILINX_VDMA_REG_START_ADDRESS_64(i++), - segment->hw.buf_addr, - segment->hw.buf_addr_msb); - else - vdma_desc_write(chan, + if (chan->desc_submitcount < chan->num_frms) + i = chan->desc_submitcount; + + list_for_each_entry(segment, &desc->segments, node) { + if (chan->ext_addr) + vdma_desc_write_64(chan, + XILINX_VDMA_REG_START_ADDRESS_64(i++), + segment->hw.buf_addr, + segment->hw.buf_addr_msb); + else + vdma_desc_write(chan, XILINX_VDMA_REG_START_ADDRESS(i++), segment->hw.buf_addr); - last = segment; - } - - if (!last) - return; + last = segment; + } - /* HW expects these parameters to be same for one transaction */ - vdma_desc_write(chan, XILINX_DMA_REG_HSIZE, last->hw.hsize); - vdma_desc_write(chan, XILINX_DMA_REG_FRMDLY_STRIDE, - last->hw.stride); - vdma_desc_write(chan, XILINX_DMA_REG_VSIZE, last->hw.vsize); + if (!last) + return; - chan->desc_submitcount++; - chan->desc_pendingcount--; - list_del(&desc->node); - list_add_tail(&desc->node, &chan->active_list); - if (chan->desc_submitcount == chan->num_frms) - chan->desc_submitcount = 0; - } + /* HW expects these parameters to be same for one transaction */ + vdma_desc_write(chan, XILINX_DMA_REG_HSIZE, last->hw.hsize); + vdma_desc_write(chan, XILINX_DMA_REG_FRMDLY_STRIDE, + last->hw.stride); + vdma_desc_write(chan, XILINX_DMA_REG_VSIZE, last->hw.vsize); + + chan->desc_submitcount++; + chan->desc_pendingcount--; + list_del(&desc->node); + list_add_tail(&desc->node, &chan->active_list); + if (chan->desc_submitcount == chan->num_frms) + chan->desc_submitcount = 0; chan->idle = false; } -- 2.17.1 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andrea Merello Subject: [PATCH v5 7/7] dmaengine: xilinx_dma: Drop SG support for VDMA IP Date: Fri, 7 Sep 2018 08:25:02 +0200 Message-ID: <20180907062502.8241-7-andrea.merello@gmail.com> References: <20180907062502.8241-1-andrea.merello@gmail.com> Return-path: In-Reply-To: <20180907062502.8241-1-andrea.merello@gmail.com> Sender: linux-kernel-owner@vger.kernel.org To: vkoul@kernel.org, dan.j.williams@intel.com, michal.simek@xilinx.com, appana.durga.rao@xilinx.com, dmaengine@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, radhey.shyam.pandey@xilinx.com, Andrea Merello List-Id: devicetree@vger.kernel.org xilinx_vdma_start_transfer() is used only for VDMA IP, still it contains conditional code on has_sg variable. has_sg is set only whenever the HW does support SG mode, that is never true for VDMA IP. This patch drops the never-taken branches. Signed-off-by: Andrea Merello --- Changes in V4: introduced this patch in series Changes in v5: None --- drivers/dma/xilinx/xilinx_dma.c | 84 +++++++++++++-------------------- 1 file changed, 32 insertions(+), 52 deletions(-) diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c index 78d0f2f8225e..07ceadef0a00 100644 --- a/drivers/dma/xilinx/xilinx_dma.c +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -1093,6 +1093,8 @@ static void xilinx_vdma_start_transfer(struct xilinx_dma_chan *chan) struct xilinx_dma_tx_descriptor *desc, *tail_desc; u32 reg, j; struct xilinx_vdma_tx_segment *tail_segment; + struct xilinx_vdma_tx_segment *segment, *last = NULL; + int i = 0; /* This function was invoked with lock held */ if (chan->err) @@ -1112,14 +1114,6 @@ static void xilinx_vdma_start_transfer(struct xilinx_dma_chan *chan) tail_segment = list_last_entry(&tail_desc->segments, struct xilinx_vdma_tx_segment, node); - /* - * If hardware is idle, then all descriptors on the running lists are - * done, start new transfers - */ - if (chan->has_sg) - dma_ctrl_write(chan, XILINX_DMA_REG_CURDESC, - desc->async_tx.phys); - /* Configure the hardware using info in the config structure */ reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); @@ -1128,15 +1122,11 @@ static void xilinx_vdma_start_transfer(struct xilinx_dma_chan *chan) else reg &= ~XILINX_DMA_DMACR_FRAMECNT_EN; - /* - * With SG, start with circular mode, so that BDs can be fetched. - * In direct register mode, if not parking, enable circular mode - */ - if (chan->has_sg || !config->park) - reg |= XILINX_DMA_DMACR_CIRC_EN; - + /* If not parking, enable circular mode */ if (config->park) reg &= ~XILINX_DMA_DMACR_CIRC_EN; + else + reg |= XILINX_DMA_DMACR_CIRC_EN; dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); @@ -1158,48 +1148,38 @@ static void xilinx_vdma_start_transfer(struct xilinx_dma_chan *chan) return; /* Start the transfer */ - if (chan->has_sg) { - dma_ctrl_write(chan, XILINX_DMA_REG_TAILDESC, - tail_segment->phys); - list_splice_tail_init(&chan->pending_list, &chan->active_list); - chan->desc_pendingcount = 0; - } else { - struct xilinx_vdma_tx_segment *segment, *last = NULL; - int i = 0; - - if (chan->desc_submitcount < chan->num_frms) - i = chan->desc_submitcount; - - list_for_each_entry(segment, &desc->segments, node) { - if (chan->ext_addr) - vdma_desc_write_64(chan, - XILINX_VDMA_REG_START_ADDRESS_64(i++), - segment->hw.buf_addr, - segment->hw.buf_addr_msb); - else - vdma_desc_write(chan, + if (chan->desc_submitcount < chan->num_frms) + i = chan->desc_submitcount; + + list_for_each_entry(segment, &desc->segments, node) { + if (chan->ext_addr) + vdma_desc_write_64(chan, + XILINX_VDMA_REG_START_ADDRESS_64(i++), + segment->hw.buf_addr, + segment->hw.buf_addr_msb); + else + vdma_desc_write(chan, XILINX_VDMA_REG_START_ADDRESS(i++), segment->hw.buf_addr); - last = segment; - } - - if (!last) - return; + last = segment; + } - /* HW expects these parameters to be same for one transaction */ - vdma_desc_write(chan, XILINX_DMA_REG_HSIZE, last->hw.hsize); - vdma_desc_write(chan, XILINX_DMA_REG_FRMDLY_STRIDE, - last->hw.stride); - vdma_desc_write(chan, XILINX_DMA_REG_VSIZE, last->hw.vsize); + if (!last) + return; - chan->desc_submitcount++; - chan->desc_pendingcount--; - list_del(&desc->node); - list_add_tail(&desc->node, &chan->active_list); - if (chan->desc_submitcount == chan->num_frms) - chan->desc_submitcount = 0; - } + /* HW expects these parameters to be same for one transaction */ + vdma_desc_write(chan, XILINX_DMA_REG_HSIZE, last->hw.hsize); + vdma_desc_write(chan, XILINX_DMA_REG_FRMDLY_STRIDE, + last->hw.stride); + vdma_desc_write(chan, XILINX_DMA_REG_VSIZE, last->hw.vsize); + + chan->desc_submitcount++; + chan->desc_pendingcount--; + list_del(&desc->node); + list_add_tail(&desc->node, &chan->active_list); + if (chan->desc_submitcount == chan->num_frms) + chan->desc_submitcount = 0; chan->idle = false; } -- 2.17.1