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diff for duplicates of <20180907142504.5034351e@jacob-builder>

diff --git a/a/1.txt b/N1/1.txt
index 897ab0e..e8f5097 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -1,151 +1,114 @@
-On Fri, 7 Sep 2018 20:02:54 +0200
-Christian König <christian.koenig@amd.com> wrote:
-
-> Am 07.09.2018 um 17:45 schrieb Jean-Philippe Brucker:
-> > On 07/09/2018 09:55, Christian König wrote:  
-> >> I will take this as an opportunity to summarize some of the
-> >> requirements we have for PASID management from the amdgpu driver
-> >> point of view:  
-> > That's incredibly useful, thanks :)
-> >  
-> >> 1. We need to be able to allocate PASID between 1 and some
-> >> maximum. Zero is reserved as far as I know, but we don't necessary
-> >> need a minimum.  
->  [...]  
-> >> 2. We need to be able to allocate PASIDs without a process address
-> >> space backing it. E.g. our hardware uses PASIDs even without
-> >> Shared Virtual Addressing enabled to distinct clients from each
-> >> other. Would be a pity if we need to still have a separate PASID
-> >> handling because the system wide is only available when IOMMU is
-> >> turned on.  
->  [...]  
-> 
-> I agree on that.
-> 
-> > iommu-sva expects everywhere that the device has an iommu_domain,
-> > it's the first thing we check on entry. Bypassing all of this would
-> > call idr_alloc() directly, and wouldn't have any code in common
-> > with the current iommu-sva. So it seems like you need a layer on
-> > top of iommu-sva calling idr_alloc() when an IOMMU isn't present,
-> > but I don't think it should be in drivers/iommu/  
-> 
-> In this case I question if the PASID handling should be under 
-> drivers/iommu at all.
-> 
-> See I can have a mix of VM context which are bound to processes (some 
-> few) and VM contexts which are standalone and doesn't care for a
-> process address space. But for each VM context I need a distinct
-> PASID for the hardware to work.
-> 
-> I can live if we say if IOMMU is completely disabled we use a simple
-> ida to allocate them, but when IOMMU is enabled I certainly need a
-> way to reserve a PASID without an associated process.
-> 
-VT-d would also have such requirement. There is a virtual command
-register for allocate and free PASID for VM use. When that PASID
-allocation request gets propagated to the host IOMMU driver, we need to
-allocate PASID w/o mm.
-
-If the PASID allocation is done via VFIO, can we have FD to track PASID
-life cycle instead of mm_exit()? i.e. all FDs get closed before
-mm_exit, I assume?
-
-> >> 3. Even after destruction of a process address space we need some
-> >> grace period before a PASID is reused because it can be that the
-> >> specific PASID is still in some hardware queues etc...
-> >>           At bare minimum all device drivers using process binding
-> >> need to explicitly note to the core when they are done with a
-> >> PASID.  
-> > Right, much of the horribleness in iommu-sva deals with this:
-> >
-> > The process dies, iommu-sva is notified and calls the mm_exit()
-> > function passed by the device driver to iommu_sva_device_init(). In
-> > mm_exit() the device driver needs to clear any reference to the
-> > PASID in hardware and in its own structures. When the device driver
-> > returns from mm_exit(), it effectively tells the core that it has
-> > finished using the PASID, and iommu-sva can reuse the PASID for
-> > another process. mm_exit() is allowed to block, so the device
-> > driver has time to clean up and flush the queues.
-> >
-> > If the device driver finishes using the PASID before the process
-> > exits, it just calls unbind().  
-> 
-> Exactly that's what Michal Hocko is probably going to not like at all.
-> 
-> Can we have a different approach where each driver is informed by the 
-> mm_exit(), but needs to explicitly call unbind() before a PASID is
-> reused?
-> 
-> During that teardown transition it would be ideal if that PASID only 
-> points to a dummy root page directory with only invalid entries.
-> 
-I guess this can be vendor specific, In VT-d I plan to mark PASID
-entry not present and disable fault reporting while draining remaining
-activities.
-
-> >  
-> >> 4. It would be nice to have to be able to set a "void *" for each
-> >> PASID/device combination while binding to a process which then can
-> >> be queried later on based on the PASID.
-> >>           E.g. when you have a per PASID/device structure around
-> >> anyway, just add an extra field.  
-> > iommu_sva_bind_device() takes a "drvdata" pointer that is stored
-> > internally for the PASID/device combination (iommu_bond). It is
-> > passed to mm_exit(), but I haven't added anything for the device
-> > driver to query it back.  
-> 
-> Nice! Looks like all we need additionally is a function to retrieve
-> that based on the PASID.
-> 
-> >> 5. It would be nice to have to allocate multiple PASIDs for the
-> >> same process address space.
-> >>           E.g. some teams at AMD want to use a separate GPU
-> >> address space for their userspace client library. I'm still trying
-> >> to avoid that, but it is perfectly possible that we are going to
-> >> need that.  
-> > Two PASIDs pointing to the same process pgd? At first glance it
-> > seems feasible, maybe with a flag passed to bind() and a few
-> > changes to internal structures. It will duplicate ATC invalidation
-> > commands for each process address space change (munmap etc) so you
-> > might take a performance hit.
-> >
-> > Intel's SVM code has the SVM_FLAG_PRIVATE_PASID which seems similar
-> > to what you describe, but I don't plan to support it in this series
-> > (the io_mm model is already pretty complicated). I think it can be
-> > added without too much effort in a future series, though with a
-> > different flag name since we'd like to use "private PASID" for
-> > something else
-> > (https://www.spinics.net/lists/dri-devel/msg177007.html).  
-> 
-> To be honest I hoped that you would say: No never! So that I have a
-> good argument to pushback on such requirements :)
-> 
-> But if it's doable it would be at least nice to have for debugging.
-> 
-> Thanks a lot for working on that,
-> Christian.
-> 
-> >
-> > Thanks,
-> > Jean
-> >  
-> >>           Additional to that it is sometimes quite useful for
-> >> debugging to isolate where exactly an incorrect access (segfault)
-> >> is coming from.
-> >>
-> >> Let me know if there are some problems with that, especially I
-> >> want to know if there is pushback on #5 so that I can forward
-> >> that :)
-> >>
-> >> Thanks,
-> >> Christian.
-> >>  
-> >>> Thanks,
-> >>> Jean  
-> 
-
-[Jacob Pan]
-_______________________________________________
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-iommu@lists.linux-foundation.org
-https://lists.linuxfoundation.org/mailman/listinfo/iommu
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diff --git a/a/content_digest b/N1/content_digest
index 482babd..3ac1deb 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -7,181 +7,161 @@
  "ref\02fd4a0a1-1a35-bf82-df84-b995cce011d9@amd.com\0"
  "ref\065e7accd-4446-19f5-c667-c6407e89cfa6@arm.com\0"
  "ref\05bbc0332-b94b-75cc-ca42-a9b196811daf@amd.com\0"
- "ref\05bbc0332-b94b-75cc-ca42-a9b196811daf-5C7GfCeVMHo@public.gmane.org\0"
- "From\0Jacob Pan <jacob.jun.pan-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>\0"
+ "From\0Jacob Pan <jacob.jun.pan@linux.intel.com>\0"
  "Subject\0Re: [PATCH v2 01/40] iommu: Introduce Shared Virtual Addressing API\0"
  "Date\0Fri, 7 Sep 2018 14:25:04 -0700\0"
- "To\0Christian K\303\266nig <christian.koenig-5C7GfCeVMHo@public.gmane.org>\0"
- "Cc\0xieyisheng1-hv44wF8Li93QT0dZR+AlfA@public.gmane.org <xieyisheng1-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>"
-  ilias.apalodimas-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org <ilias.apalodimas-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
-  kvm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org <kvm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>
-  linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org <linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>
-  Will Deacon <Will.Deacon-5wv7dgnIgG8@public.gmane.org>
-  Michal Hocko <mhocko-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
-  okaya-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org <okaya-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
-  linux-mm-Bw31MaZKKs3YtjvyW6yDsg@public.gmane.org <linux-mm-Bw31MaZKKs3YtjvyW6yDsg@public.gmane.org>
-  ashok.raj-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org <ashok.raj-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
-  Jean-Philippe Brucker <jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org>
-  linux-acpi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org <linux-acpi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>
-  rfranz-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org <rfranz-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org>
-  devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org <devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>
-  kevin.tian-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org <kevin.tian-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
-  rgummal-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org <rgummal-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
-  linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org <linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>
-  dwmw2-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org <dwmw2-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org>
- " liubo95-hv44wF8Li93QT0dZR+AlfA@public.gmane.org <liubo95@hua>\0"
+ "To\0Christian K\303\266nig <christian.koenig@amd.com>\0"
+ "Cc\0xieyisheng1@huawei.com <xieyisheng1@huawei.com>"
+  ilias.apalodimas@linaro.org <ilias.apalodimas@linaro.org>
+  kvm@vger.kernel.org <kvm@vger.kernel.org>
+  linux-pci@vger.kernel.org <linux-pci@vger.kernel.org>
+  xuzaibo@huawei.com <xuzaibo@huawei.com>
+  jonathan.cameron@huawei.com <jonathan.cameron@huawei.com>
+  Will Deacon <Will.Deacon@arm.com>
+  Michal Hocko <mhocko@kernel.org>
+  okaya@codeaurora.org <okaya@codeaurora.org>
+  linux-mm@kvack.org <linux-mm@kvack.org>
+  yi.l.liu@intel.com <yi.l.liu@intel.com>
+  ashok.raj@intel.com <ashok.raj@intel.com>
+  Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
+  tn@semihalf.com <tn@semihalf.com>
+  joro@8bytes.org <joro@8bytes.org>
+  robdclark@gmail.com <robdclark@gmail.com>
+  bharatku@xilinx.com <bharatku@xilinx.com>
+  linux-acpi@vger.kernel.org <linux-acpi@vger.kernel.org>
+  liudongdong3@huawei.com <liudongdong3@huawei.com>
+  rfranz@cavium.com <rfranz@cavium.com>
+  devicetree@vger.kernel.org <devicetree@vger.kernel.org>
+  kevin.tian@intel.com <kevin.tian@intel.com>
+  jacob.jun.pan@linux.intel.com
+  Auger Eric <eric.auger@redhat.com>
+  jcrouse@codeaurora.org <jcrouse@codeaurora.org>
+  rgummal@xilinx.com <rgummal@xilinx.com>
+  thunder.leizhen@huawei.com <thunder.leizhen@huawei.com>
+  linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org>
+  shunyong.yang@hxt-semitech.com <shunyong.yang@hxt-semitech.com>
+  dwmw2@infradead.org <dwmw2@infradead.org>
+  liubo95@huawei.com <liubo95@huawei.com>
+  alex.williamson@redhat.com <alex.williamson@redhat.com>
+  iommu@lists.linux-foundation.org <iommu@lists.linux-foundation.org>
+  Robin Murphy <Robin.Murphy@arm.com>
+  nwatters@codeaurora.org <nwatters@codeaurora.org>
+ " baolu.lu@linux.intel.com <baolu.lu@linux.intel.com>\0"
  "\00:1\0"
  "b\0"
- "On Fri, 7 Sep 2018 20:02:54 +0200\n"
- "Christian K\303\266nig <christian.koenig@amd.com> wrote:\n"
- "\n"
- "> Am 07.09.2018 um 17:45 schrieb Jean-Philippe Brucker:\n"
- "> > On 07/09/2018 09:55, Christian K\303\266nig wrote:  \n"
- "> >> I will take this as an opportunity to summarize some of the\n"
- "> >> requirements we have for PASID management from the amdgpu driver\n"
- "> >> point of view:  \n"
- "> > That's incredibly useful, thanks :)\n"
- "> >  \n"
- "> >> 1. We need to be able to allocate PASID between 1 and some\n"
- "> >> maximum. Zero is reserved as far as I know, but we don't necessary\n"
- "> >> need a minimum.  \n"
- ">  [...]  \n"
- "> >> 2. We need to be able to allocate PASIDs without a process address\n"
- "> >> space backing it. E.g. our hardware uses PASIDs even without\n"
- "> >> Shared Virtual Addressing enabled to distinct clients from each\n"
- "> >> other. Would be a pity if we need to still have a separate PASID\n"
- "> >> handling because the system wide is only available when IOMMU is\n"
- "> >> turned on.  \n"
- ">  [...]  \n"
- "> \n"
- "> I agree on that.\n"
- "> \n"
- "> > iommu-sva expects everywhere that the device has an iommu_domain,\n"
- "> > it's the first thing we check on entry. Bypassing all of this would\n"
- "> > call idr_alloc() directly, and wouldn't have any code in common\n"
- "> > with the current iommu-sva. So it seems like you need a layer on\n"
- "> > top of iommu-sva calling idr_alloc() when an IOMMU isn't present,\n"
- "> > but I don't think it should be in drivers/iommu/  \n"
- "> \n"
- "> In this case I question if the PASID handling should be under \n"
- "> drivers/iommu at all.\n"
- "> \n"
- "> See I can have a mix of VM context which are bound to processes (some \n"
- "> few) and VM contexts which are standalone and doesn't care for a\n"
- "> process address space. But for each VM context I need a distinct\n"
- "> PASID for the hardware to work.\n"
- "> \n"
- "> I can live if we say if IOMMU is completely disabled we use a simple\n"
- "> ida to allocate them, but when IOMMU is enabled I certainly need a\n"
- "> way to reserve a PASID without an associated process.\n"
- "> \n"
- "VT-d would also have such requirement. There is a virtual command\n"
- "register for allocate and free PASID for VM use. When that PASID\n"
- "allocation request gets propagated to the host IOMMU driver, we need to\n"
- "allocate PASID w/o mm.\n"
- "\n"
- "If the PASID allocation is done via VFIO, can we have FD to track PASID\n"
- "life cycle instead of mm_exit()? i.e. all FDs get closed before\n"
- "mm_exit, I assume?\n"
- "\n"
- "> >> 3. Even after destruction of a process address space we need some\n"
- "> >> grace period before a PASID is reused because it can be that the\n"
- "> >> specific PASID is still in some hardware queues etc...\n"
- "> >>   \302\240\302\240\302\240 \302\240\302\240\302\240 At bare minimum all device drivers using process binding\n"
- "> >> need to explicitly note to the core when they are done with a\n"
- "> >> PASID.  \n"
- "> > Right, much of the horribleness in iommu-sva deals with this:\n"
- "> >\n"
- "> > The process dies, iommu-sva is notified and calls the mm_exit()\n"
- "> > function passed by the device driver to iommu_sva_device_init(). In\n"
- "> > mm_exit() the device driver needs to clear any reference to the\n"
- "> > PASID in hardware and in its own structures. When the device driver\n"
- "> > returns from mm_exit(), it effectively tells the core that it has\n"
- "> > finished using the PASID, and iommu-sva can reuse the PASID for\n"
- "> > another process. mm_exit() is allowed to block, so the device\n"
- "> > driver has time to clean up and flush the queues.\n"
- "> >\n"
- "> > If the device driver finishes using the PASID before the process\n"
- "> > exits, it just calls unbind().  \n"
- "> \n"
- "> Exactly that's what Michal Hocko is probably going to not like at all.\n"
- "> \n"
- "> Can we have a different approach where each driver is informed by the \n"
- "> mm_exit(), but needs to explicitly call unbind() before a PASID is\n"
- "> reused?\n"
- "> \n"
- "> During that teardown transition it would be ideal if that PASID only \n"
- "> points to a dummy root page directory with only invalid entries.\n"
- "> \n"
- "I guess this can be vendor specific, In VT-d I plan to mark PASID\n"
- "entry not present and disable fault reporting while draining remaining\n"
- "activities.\n"
- "\n"
- "> >  \n"
- "> >> 4. It would be nice to have to be able to set a \"void *\" for each\n"
- "> >> PASID/device combination while binding to a process which then can\n"
- "> >> be queried later on based on the PASID.\n"
- "> >>   \302\240\302\240\302\240 \302\240\302\240\302\240 E.g. when you have a per PASID/device structure around\n"
- "> >> anyway, just add an extra field.  \n"
- "> > iommu_sva_bind_device() takes a \"drvdata\" pointer that is stored\n"
- "> > internally for the PASID/device combination (iommu_bond). It is\n"
- "> > passed to mm_exit(), but I haven't added anything for the device\n"
- "> > driver to query it back.  \n"
- "> \n"
- "> Nice! Looks like all we need additionally is a function to retrieve\n"
- "> that based on the PASID.\n"
- "> \n"
- "> >> 5. It would be nice to have to allocate multiple PASIDs for the\n"
- "> >> same process address space.\n"
- "> >>   \302\240\302\240\302\240 \302\240\302\240\302\240 E.g. some teams at AMD want to use a separate GPU\n"
- "> >> address space for their userspace client library. I'm still trying\n"
- "> >> to avoid that, but it is perfectly possible that we are going to\n"
- "> >> need that.  \n"
- "> > Two PASIDs pointing to the same process pgd? At first glance it\n"
- "> > seems feasible, maybe with a flag passed to bind() and a few\n"
- "> > changes to internal structures. It will duplicate ATC invalidation\n"
- "> > commands for each process address space change (munmap etc) so you\n"
- "> > might take a performance hit.\n"
- "> >\n"
- "> > Intel's SVM code has the SVM_FLAG_PRIVATE_PASID which seems similar\n"
- "> > to what you describe, but I don't plan to support it in this series\n"
- "> > (the io_mm model is already pretty complicated). I think it can be\n"
- "> > added without too much effort in a future series, though with a\n"
- "> > different flag name since we'd like to use \"private PASID\" for\n"
- "> > something else\n"
- "> > (https://www.spinics.net/lists/dri-devel/msg177007.html).  \n"
- "> \n"
- "> To be honest I hoped that you would say: No never! So that I have a\n"
- "> good argument to pushback on such requirements :)\n"
- "> \n"
- "> But if it's doable it would be at least nice to have for debugging.\n"
- "> \n"
- "> Thanks a lot for working on that,\n"
- "> Christian.\n"
- "> \n"
- "> >\n"
- "> > Thanks,\n"
- "> > Jean\n"
- "> >  \n"
- "> >>   \302\240\302\240\302\240 \302\240\302\240\302\240 Additional to that it is sometimes quite useful for\n"
- "> >> debugging to isolate where exactly an incorrect access (segfault)\n"
- "> >> is coming from.\n"
- "> >>\n"
- "> >> Let me know if there are some problems with that, especially I\n"
- "> >> want to know if there is pushback on #5 so that I can forward\n"
- "> >> that :)\n"
- "> >>\n"
- "> >> Thanks,\n"
- "> >> Christian.\n"
- "> >>  \n"
- "> >>> Thanks,\n"
- "> >>> Jean  \n"
- "> \n"
- "\n"
- "[Jacob Pan]\n"
- "_______________________________________________\n"
- "iommu mailing list\n"
- "iommu@lists.linux-foundation.org\n"
- https://lists.linuxfoundation.org/mailman/listinfo/iommu
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diff --git a/a/1.txt b/N2/1.txt
index 897ab0e..41a7d4a 100644
--- a/a/1.txt
+++ b/N2/1.txt
@@ -1,8 +1,8 @@
 On Fri, 7 Sep 2018 20:02:54 +0200
-Christian König <christian.koenig@amd.com> wrote:
+Christian K?nig <christian.koenig@amd.com> wrote:
 
 > Am 07.09.2018 um 17:45 schrieb Jean-Philippe Brucker:
-> > On 07/09/2018 09:55, Christian König wrote:  
+> > On 07/09/2018 09:55, Christian K?nig wrote:  
 > >> I will take this as an opportunity to summarize some of the
 > >> requirements we have for PASID management from the amdgpu driver
 > >> point of view:  
@@ -53,7 +53,7 @@ mm_exit, I assume?
 > >> 3. Even after destruction of a process address space we need some
 > >> grace period before a PASID is reused because it can be that the
 > >> specific PASID is still in some hardware queues etc...
-> >>           At bare minimum all device drivers using process binding
+> >>   ??? ??? At bare minimum all device drivers using process binding
 > >> need to explicitly note to the core when they are done with a
 > >> PASID.  
 > > Right, much of the horribleness in iommu-sva deals with this:
@@ -87,7 +87,7 @@ activities.
 > >> 4. It would be nice to have to be able to set a "void *" for each
 > >> PASID/device combination while binding to a process which then can
 > >> be queried later on based on the PASID.
-> >>           E.g. when you have a per PASID/device structure around
+> >>   ??? ??? E.g. when you have a per PASID/device structure around
 > >> anyway, just add an extra field.  
 > > iommu_sva_bind_device() takes a "drvdata" pointer that is stored
 > > internally for the PASID/device combination (iommu_bond). It is
@@ -99,7 +99,7 @@ activities.
 > 
 > >> 5. It would be nice to have to allocate multiple PASIDs for the
 > >> same process address space.
-> >>           E.g. some teams at AMD want to use a separate GPU
+> >>   ??? ??? E.g. some teams at AMD want to use a separate GPU
 > >> address space for their userspace client library. I'm still trying
 > >> to avoid that, but it is perfectly possible that we are going to
 > >> need that.  
@@ -129,7 +129,7 @@ activities.
 > > Thanks,
 > > Jean
 > >  
-> >>           Additional to that it is sometimes quite useful for
+> >>   ??? ??? Additional to that it is sometimes quite useful for
 > >> debugging to isolate where exactly an incorrect access (segfault)
 > >> is coming from.
 > >>
@@ -145,7 +145,3 @@ activities.
 > 
 
 [Jacob Pan]
-_______________________________________________
-iommu mailing list
-iommu@lists.linux-foundation.org
-https://lists.linuxfoundation.org/mailman/listinfo/iommu
diff --git a/a/content_digest b/N2/content_digest
index 482babd..aa2e0ce 100644
--- a/a/content_digest
+++ b/N2/content_digest
@@ -7,36 +7,17 @@
  "ref\02fd4a0a1-1a35-bf82-df84-b995cce011d9@amd.com\0"
  "ref\065e7accd-4446-19f5-c667-c6407e89cfa6@arm.com\0"
  "ref\05bbc0332-b94b-75cc-ca42-a9b196811daf@amd.com\0"
- "ref\05bbc0332-b94b-75cc-ca42-a9b196811daf-5C7GfCeVMHo@public.gmane.org\0"
- "From\0Jacob Pan <jacob.jun.pan-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>\0"
- "Subject\0Re: [PATCH v2 01/40] iommu: Introduce Shared Virtual Addressing API\0"
+ "From\0jacob.jun.pan@linux.intel.com (Jacob Pan)\0"
+ "Subject\0[PATCH v2 01/40] iommu: Introduce Shared Virtual Addressing API\0"
  "Date\0Fri, 7 Sep 2018 14:25:04 -0700\0"
- "To\0Christian K\303\266nig <christian.koenig-5C7GfCeVMHo@public.gmane.org>\0"
- "Cc\0xieyisheng1-hv44wF8Li93QT0dZR+AlfA@public.gmane.org <xieyisheng1-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>"
-  ilias.apalodimas-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org <ilias.apalodimas-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
-  kvm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org <kvm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>
-  linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org <linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>
-  Will Deacon <Will.Deacon-5wv7dgnIgG8@public.gmane.org>
-  Michal Hocko <mhocko-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
-  okaya-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org <okaya-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
-  linux-mm-Bw31MaZKKs3YtjvyW6yDsg@public.gmane.org <linux-mm-Bw31MaZKKs3YtjvyW6yDsg@public.gmane.org>
-  ashok.raj-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org <ashok.raj-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
-  Jean-Philippe Brucker <jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org>
-  linux-acpi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org <linux-acpi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>
-  rfranz-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org <rfranz-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org>
-  devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org <devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>
-  kevin.tian-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org <kevin.tian-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
-  rgummal-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org <rgummal-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
-  linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org <linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>
-  dwmw2-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org <dwmw2-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org>
- " liubo95-hv44wF8Li93QT0dZR+AlfA@public.gmane.org <liubo95@hua>\0"
+ "To\0linux-arm-kernel@lists.infradead.org\0"
  "\00:1\0"
  "b\0"
  "On Fri, 7 Sep 2018 20:02:54 +0200\n"
- "Christian K\303\266nig <christian.koenig@amd.com> wrote:\n"
+ "Christian K?nig <christian.koenig@amd.com> wrote:\n"
  "\n"
  "> Am 07.09.2018 um 17:45 schrieb Jean-Philippe Brucker:\n"
- "> > On 07/09/2018 09:55, Christian K\303\266nig wrote:  \n"
+ "> > On 07/09/2018 09:55, Christian K?nig wrote:  \n"
  "> >> I will take this as an opportunity to summarize some of the\n"
  "> >> requirements we have for PASID management from the amdgpu driver\n"
  "> >> point of view:  \n"
@@ -87,7 +68,7 @@
  "> >> 3. Even after destruction of a process address space we need some\n"
  "> >> grace period before a PASID is reused because it can be that the\n"
  "> >> specific PASID is still in some hardware queues etc...\n"
- "> >>   \302\240\302\240\302\240 \302\240\302\240\302\240 At bare minimum all device drivers using process binding\n"
+ "> >>   ??? ??? At bare minimum all device drivers using process binding\n"
  "> >> need to explicitly note to the core when they are done with a\n"
  "> >> PASID.  \n"
  "> > Right, much of the horribleness in iommu-sva deals with this:\n"
@@ -121,7 +102,7 @@
  "> >> 4. It would be nice to have to be able to set a \"void *\" for each\n"
  "> >> PASID/device combination while binding to a process which then can\n"
  "> >> be queried later on based on the PASID.\n"
- "> >>   \302\240\302\240\302\240 \302\240\302\240\302\240 E.g. when you have a per PASID/device structure around\n"
+ "> >>   ??? ??? E.g. when you have a per PASID/device structure around\n"
  "> >> anyway, just add an extra field.  \n"
  "> > iommu_sva_bind_device() takes a \"drvdata\" pointer that is stored\n"
  "> > internally for the PASID/device combination (iommu_bond). It is\n"
@@ -133,7 +114,7 @@
  "> \n"
  "> >> 5. It would be nice to have to allocate multiple PASIDs for the\n"
  "> >> same process address space.\n"
- "> >>   \302\240\302\240\302\240 \302\240\302\240\302\240 E.g. some teams at AMD want to use a separate GPU\n"
+ "> >>   ??? ??? E.g. some teams at AMD want to use a separate GPU\n"
  "> >> address space for their userspace client library. I'm still trying\n"
  "> >> to avoid that, but it is perfectly possible that we are going to\n"
  "> >> need that.  \n"
@@ -163,7 +144,7 @@
  "> > Thanks,\n"
  "> > Jean\n"
  "> >  \n"
- "> >>   \302\240\302\240\302\240 \302\240\302\240\302\240 Additional to that it is sometimes quite useful for\n"
+ "> >>   ??? ??? Additional to that it is sometimes quite useful for\n"
  "> >> debugging to isolate where exactly an incorrect access (segfault)\n"
  "> >> is coming from.\n"
  "> >>\n"
@@ -178,10 +159,6 @@
  "> >>> Jean  \n"
  "> \n"
  "\n"
- "[Jacob Pan]\n"
- "_______________________________________________\n"
- "iommu mailing list\n"
- "iommu@lists.linux-foundation.org\n"
- https://lists.linuxfoundation.org/mailman/listinfo/iommu
+ [Jacob Pan]
 
-9c3476ba1dc0c94633a1de6723708f8bf166d6f78911508ed309ab479a95cf90
+b86a54ac60d4853c0f0968832ba9c4647049673915f5c59b19c102bfc3551ed0

diff --git a/a/content_digest b/N3/content_digest
index 482babd..cdc41dc 100644
--- a/a/content_digest
+++ b/N3/content_digest
@@ -29,7 +29,7 @@
   rgummal-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org <rgummal-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
   linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org <linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>
   dwmw2-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org <dwmw2-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org>
- " liubo95-hv44wF8Li93QT0dZR+AlfA@public.gmane.org <liubo95@hua>\0"
+ " liubo95-hv44wF8Li93QT0dZR+AlfA@public.gmane.org <liubo95@hua\0"
  "\00:1\0"
  "b\0"
  "On Fri, 7 Sep 2018 20:02:54 +0200\n"
@@ -184,4 +184,4 @@
  "iommu@lists.linux-foundation.org\n"
  https://lists.linuxfoundation.org/mailman/listinfo/iommu
 
-9c3476ba1dc0c94633a1de6723708f8bf166d6f78911508ed309ab479a95cf90
+b55d66731257d7d9e2729a0f9647738f10de0e5962edcbd276076ab564b08903

diff --git a/a/1.txt b/N4/1.txt
index 897ab0e..915a142 100644
--- a/a/1.txt
+++ b/N4/1.txt
@@ -145,7 +145,3 @@ activities.
 > 
 
 [Jacob Pan]
-_______________________________________________
-iommu mailing list
-iommu@lists.linux-foundation.org
-https://lists.linuxfoundation.org/mailman/listinfo/iommu
diff --git a/a/content_digest b/N4/content_digest
index 482babd..d7e6852 100644
--- a/a/content_digest
+++ b/N4/content_digest
@@ -7,29 +7,46 @@
  "ref\02fd4a0a1-1a35-bf82-df84-b995cce011d9@amd.com\0"
  "ref\065e7accd-4446-19f5-c667-c6407e89cfa6@arm.com\0"
  "ref\05bbc0332-b94b-75cc-ca42-a9b196811daf@amd.com\0"
- "ref\05bbc0332-b94b-75cc-ca42-a9b196811daf-5C7GfCeVMHo@public.gmane.org\0"
- "From\0Jacob Pan <jacob.jun.pan-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>\0"
+ "From\0Jacob Pan <jacob.jun.pan@linux.intel.com>\0"
  "Subject\0Re: [PATCH v2 01/40] iommu: Introduce Shared Virtual Addressing API\0"
  "Date\0Fri, 7 Sep 2018 14:25:04 -0700\0"
- "To\0Christian K\303\266nig <christian.koenig-5C7GfCeVMHo@public.gmane.org>\0"
- "Cc\0xieyisheng1-hv44wF8Li93QT0dZR+AlfA@public.gmane.org <xieyisheng1-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>"
-  ilias.apalodimas-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org <ilias.apalodimas-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
-  kvm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org <kvm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>
-  linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org <linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>
-  Will Deacon <Will.Deacon-5wv7dgnIgG8@public.gmane.org>
-  Michal Hocko <mhocko-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
-  okaya-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org <okaya-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
-  linux-mm-Bw31MaZKKs3YtjvyW6yDsg@public.gmane.org <linux-mm-Bw31MaZKKs3YtjvyW6yDsg@public.gmane.org>
-  ashok.raj-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org <ashok.raj-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
-  Jean-Philippe Brucker <jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org>
-  linux-acpi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org <linux-acpi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>
-  rfranz-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org <rfranz-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org>
-  devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org <devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>
-  kevin.tian-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org <kevin.tian-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
-  rgummal-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org <rgummal-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
-  linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org <linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>
-  dwmw2-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org <dwmw2-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org>
- " liubo95-hv44wF8Li93QT0dZR+AlfA@public.gmane.org <liubo95@hua>\0"
+ "To\0Christian K\303\266nig <christian.koenig@amd.com>\0"
+ "Cc\0Jean-Philippe Brucker <jean-philippe.brucker@arm.com>"
+  Auger Eric <eric.auger@redhat.com>
+  linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org>
+  linux-pci@vger.kernel.org <linux-pci@vger.kernel.org>
+  linux-acpi@vger.kernel.org <linux-acpi@vger.kernel.org>
+  devicetree@vger.kernel.org <devicetree@vger.kernel.org>
+  iommu@lists.linux-foundation.org <iommu@lists.linux-foundation.org>
+  kvm@vger.kernel.org <kvm@vger.kernel.org>
+  linux-mm@kvack.org <linux-mm@kvack.org>
+  xieyisheng1@huawei.com <xieyisheng1@huawei.com>
+  liubo95@huawei.com <liubo95@huawei.com>
+  xuzaibo@huawei.com <xuzaibo@huawei.com>
+  thunder.leizhen@huawei.com <thunder.leizhen@huawei.com>
+  Will Deacon <Will.Deacon@arm.com>
+  okaya@codeaurora.org <okaya@codeaurora.org>
+  yi.l.liu@intel.com <yi.l.liu@intel.com>
+  ashok.raj@intel.com <ashok.raj@intel.com>
+  tn@semihalf.com <tn@semihalf.com>
+  joro@8bytes.org <joro@8bytes.org>
+  bharatku@xilinx.com <bharatku@xilinx.com>
+  liudongdong3@huawei.com <liudongdong3@huawei.com>
+  rfranz@cavium.com <rfranz@cavium.com>
+  kevin.tian@intel.com <kevin.tian@intel.com>
+  jcrouse@codeaurora.org <jcrouse@codeaurora.org>
+  rgummal@xilinx.com <rgummal@xilinx.com>
+  jonathan.cameron@huawei.com <jonathan.cameron@huawei.com>
+  shunyong.yang@hxt-semitech.com <shunyong.yang@hxt-semitech.com>
+  Robin Murphy <Robin.Murphy@arm.com>
+  ilias.apalodimas@linaro.org <ilias.apalodimas@linaro.org>
+  alex.williamson@redhat.com <alex.williamson@redhat.com>
+  robdclark@gmail.com <robdclark@gmail.com>
+  dwmw2@infradead.org <dwmw2@infradead.org>
+  nwatters@codeaurora.org <nwatters@codeaurora.org>
+  baolu.lu@linux.intel.com <baolu.lu@linux.intel.com>
+  Michal Hocko <mhocko@kernel.org>
+ " jacob.jun.pan@linux.intel.com\0"
  "\00:1\0"
  "b\0"
  "On Fri, 7 Sep 2018 20:02:54 +0200\n"
@@ -178,10 +195,6 @@
  "> >>> Jean  \n"
  "> \n"
  "\n"
- "[Jacob Pan]\n"
- "_______________________________________________\n"
- "iommu mailing list\n"
- "iommu@lists.linux-foundation.org\n"
- https://lists.linuxfoundation.org/mailman/listinfo/iommu
+ [Jacob Pan]
 
-9c3476ba1dc0c94633a1de6723708f8bf166d6f78911508ed309ab479a95cf90
+bd34dcdfdbc01cb05e5874258efcf7151f5d25e5a8d5955704879600d05fdfa4

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