diff for duplicates of <20180916111242.73af71ed@archlinux> diff --git a/a/1.txt b/N1/1.txt index fc32e04..f832207 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -35,7 +35,7 @@ Jonathan > +What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_vccpsintlp > +Date: September 2018 > +KernelVersion: 4.19.0 -> +Contact: mnarani@xilinx.com +> +Contact: mnarani at xilinx.com > +Description: > + Voltage input for PS (Processing System) LPD (Low Power Domain) > + power supply. @@ -44,7 +44,7 @@ Jonathan > +What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_vccpsintfp > +Date: September 2018 > +KernelVersion: 4.19.0 -> +Contact: mnarani@xilinx.com +> +Contact: mnarani at xilinx.com > +Description: > + Voltage input for PS (Processing System) FPD (Full Power Domain) > + power supply. @@ -53,7 +53,7 @@ Jonathan > +What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_vccpsaux > +Date: September 2018 > +KernelVersion: 4.19.0 -> +Contact: mnarani@xilinx.com +> +Contact: mnarani at xilinx.com > +Description: > + Voltage input for PS (Processing System) Auxiliary power > + supply. @@ -62,7 +62,7 @@ Jonathan > +What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_vccpsddr > +Date: September 2018 > +KernelVersion: 4.19.0 -> +Contact: mnarani@xilinx.com +> +Contact: mnarani at xilinx.com > +Description: > + Voltage input for PS (Processing System) I/O bank 504 (DDR > + PHY) power supply. @@ -71,7 +71,7 @@ Jonathan > +What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_vccpsio3 > +Date: September 2018 > +KernelVersion: 4.19.0 -> +Contact: mnarani@xilinx.com +> +Contact: mnarani at xilinx.com > +Description: > + Voltage input for PS (Processing System) I/O bank 503 > + (boot, config, JTAG, SRST, POR) power supply. @@ -80,7 +80,7 @@ Jonathan > +What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_vccpsio0 > +Date: September 2018 > +KernelVersion: 4.19.0 -> +Contact: mnarani@xilinx.com +> +Contact: mnarani at xilinx.com > +Description: > + Voltage input for PS (Processing System) I/O bank 500 > + (MIO[0:25]) power supply. @@ -89,7 +89,7 @@ Jonathan > +What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_vccpsio1 > +Date: September 2018 > +KernelVersion: 4.19.0 -> +Contact: mnarani@xilinx.com +> +Contact: mnarani at xilinx.com > +Description: > + Voltage input for PS (Processing System) I/O bank 501 > + (MIO[26:51]) power supply. @@ -98,7 +98,7 @@ Jonathan > +What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_vccpsio2 > +Date: September 2018 > +KernelVersion: 4.19.0 -> +Contact: mnarani@xilinx.com +> +Contact: mnarani at xilinx.com > +Description: > + Voltage input for PS (Processing System) I/O bank 502 > + (MIO[52:77]) power supply. @@ -107,7 +107,7 @@ Jonathan > +What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_psmgtravcc > +Date: September 2018 > +KernelVersion: 4.19.0 -> +Contact: mnarani@xilinx.com +> +Contact: mnarani at xilinx.com > +Description: > + Voltage input for PS (Processing System) GTR SerDes I/O > + power supply. @@ -116,7 +116,7 @@ Jonathan > +What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_psmgtravtt > +Date: September 2018 > +KernelVersion: 4.19.0 -> +Contact: mnarani@xilinx.com +> +Contact: mnarani at xilinx.com > +Description: > + Voltage input for PS (Processing System) GTR SerDes > + terminators power supply. @@ -125,7 +125,7 @@ Jonathan > +What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_vccams > +Date: September 2018 > +KernelVersion: 4.19.0 -> +Contact: mnarani@xilinx.com +> +Contact: mnarani at xilinx.com > +Description: > + Voltage input for PS (Processing System) SYSMON ADC circuitry > + power supply. @@ -134,7 +134,7 @@ Jonathan > +What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_vccint > +Date: September 2018 > +KernelVersion: 4.19.0 -> +Contact: mnarani@xilinx.com +> +Contact: mnarani at xilinx.com > +Description: > + Voltage input for PL (Programmable Logic) internal power supply. > + @@ -142,7 +142,7 @@ Jonathan > +What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_vccvrefp > +Date: September 2018 > +KernelVersion: 4.19.0 -> +Contact: mnarani@xilinx.com +> +Contact: mnarani at xilinx.com > +Description: > + Voltage input for PL (Programmable Logic) ADC positive V > + reference power supply. @@ -151,7 +151,7 @@ Jonathan > +What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_vccvrefn > +Date: September 2018 > +KernelVersion: 4.19.0 -> +Contact: mnarani@xilinx.com +> +Contact: mnarani at xilinx.com > +Description: > + Voltage input for PL (Programmable Logic) ADC negative V > + reference power supply. @@ -160,7 +160,7 @@ Jonathan > +What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_vccplintlp > +Date: September 2018 > +KernelVersion: 4.19.0 -> +Contact: mnarani@xilinx.com +> +Contact: mnarani at xilinx.com > +Description: > + Voltage input for PL (Programmable Logic) LPD (Low Power Domain) > + power supply. @@ -169,7 +169,7 @@ Jonathan > +What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_vccplintfp > +Date: September 2018 > +KernelVersion: 4.19.0 -> +Contact: mnarani@xilinx.com +> +Contact: mnarani at xilinx.com > +Description: > + Voltage input for PL (Programmable Logic) FPD (Full Power > + Domain) power supply. @@ -178,7 +178,7 @@ Jonathan > +What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_vccplaux > +Date: September 2018 > +KernelVersion: 4.19.0 -> +Contact: mnarani@xilinx.com +> +Contact: mnarani at xilinx.com > +Description: > + Voltage input for PL (Programmable Logic) Auxiliary power > + supply. @@ -187,7 +187,7 @@ Jonathan > +What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_vccvpvn > +Date: September 2018 > +KernelVersion: 4.19.0 -> +Contact: mnarani@xilinx.com +> +Contact: mnarani at xilinx.com > +Description: > + Voltage input for PL (Programmable Logic) Analog Input Pins > + power supply. @@ -196,7 +196,7 @@ Jonathan > +What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_vuserZ > +Date: September 2018 > +KernelVersion: 4.19.0 -> +Contact: mnarani@xilinx.com +> +Contact: mnarani at xilinx.com > +Description: > + Voltage input for PL (Programmable Logic) Fabric Analog Wires > + power supply. Z is the number in range of 0 to 3. @@ -209,7 +209,7 @@ datasheet name fields. > +What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_vcc_pspll0 > +Date: September 2018 > +KernelVersion: 4.19.0 -> +Contact: mnarani@xilinx.com +> +Contact: mnarani at xilinx.com > +Description: > + Voltage input for AMS (Analog Monitoring System) Systems PLLs > + power supply. @@ -218,7 +218,7 @@ datasheet name fields. > +What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_vcc_psbatt > +Date: September 2018 > +KernelVersion: 4.19.0 -> +Contact: mnarani@xilinx.com +> +Contact: mnarani at xilinx.com > +Description: > + Voltage input for AMS (Analog Monitoring System) Battery power > + supply. @@ -231,7 +231,7 @@ doesn't? These need to be consistent. > +What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_vccbram > +Date: September 2018 > +KernelVersion: 4.19.0 -> +Contact: mnarani@xilinx.com +> +Contact: mnarani at xilinx.com > +Description: > + Voltage input for AMS (Analog Monitoring System) Block RAM power > + supply. @@ -240,7 +240,7 @@ doesn't? These need to be consistent. > +What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_vccaux > +Date: September 2018 > +KernelVersion: 4.19.0 -> +Contact: mnarani@xilinx.com +> +Contact: mnarani at xilinx.com > +Description: > + Voltage input for AMS (Analog Monitoring System) Auxiliary power > + supply. @@ -249,7 +249,7 @@ doesn't? These need to be consistent. > +What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_psddrpll > +Date: September 2018 > +KernelVersion: 4.19.0 -> +Contact: mnarani@xilinx.com +> +Contact: mnarani at xilinx.com > +Description: > + Voltage input for AMS (Analog Monitoring System) DDR I/O > + PLLs [0:5] power supply. @@ -264,7 +264,7 @@ head! > +Date: September 2018 > +KernelVersion: 4.19.0 -> +Contact: mnarani@xilinx.com +> +Contact: mnarani at xilinx.com > +Description: > + Voltage input for AMS (Analog Monitoring System) DDR controller > + power supply. @@ -274,7 +274,7 @@ head! > +What: /sys/bus/iio/devices/iio:deviceX/in_tempY_ps_temp > +Date: September 2018 > +KernelVersion: 4.19.0 -> +Contact: mnarani@xilinx.com +> +Contact: mnarani at xilinx.com > +Description: > + Temperature input for PS (Processing System) RPU MPCore. > + @@ -282,7 +282,7 @@ head! > +What: /sys/bus/iio/devices/iio:deviceX/in_tempY_remote_temp > +Date: September 2018 > +KernelVersion: 4.19.0 -> +Contact: mnarani@xilinx.com +> +Contact: mnarani at xilinx.com > +Description: > + Temperature input for PS (Processing System) APU MPCore. @@ -299,6 +299,6 @@ For all these temperatures, do you intend to expose them as hwmon? > +What: /sys/bus/iio/devices/iio:deviceX/in_tempY_pl_temp > +Date: September 2018 > +KernelVersion: 4.19.0 -> +Contact: mnarani@xilinx.com +> +Contact: mnarani at xilinx.com > +Description: > + Temperature input for PL (Programmable Logic) SYSMON. diff --git a/a/content_digest b/N1/content_digest index e1ee862..6da0188 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,35 +1,9 @@ "ref\01536909510-7166-1-git-send-email-manish.narani@xilinx.com\0" "ref\01536909510-7166-3-git-send-email-manish.narani@xilinx.com\0" - "From\0Jonathan Cameron <jic23@kernel.org>\0" - "Subject\0Re: [PATCH v2 2/4] iio: Documentation: Add Xilinx AMS sysfs documentation\0" + "From\0jic23@kernel.org (Jonathan Cameron)\0" + "Subject\0[PATCH v2 2/4] iio: Documentation: Add Xilinx AMS sysfs documentation\0" "Date\0Sun, 16 Sep 2018 11:12:42 +0100\0" - "To\0Manish Narani <manish.narani@xilinx.com>\0" - "Cc\0<knaack.h@gmx.de>" - <lars@metafoo.de> - <pmeerw@pmeerw.net> - <michal.simek@xilinx.com> - <robh+dt@kernel.org> - <mark.rutland@arm.com> - <sudeep.holla@arm.com> - <amit.kucheria@linaro.org> - <leoyang.li@nxp.com> - <broonie@kernel.org> - <arnaud.pouliquen@st.com> - <eugen.hristev@microchip.com> - <rdunlap@infradead.org> - <geert@linux-m68k.org> - <ak@it-klinger.de> - <freeman.liu@spreadtrum.com> - <lukas@wunner.de> - <vilhelm.gray@gmail.com> - <gregkh@linuxfoundation.org> - <kstewart@linuxfoundation.org> - <sgoud@xilinx.com> - <anirudh@xilinx.com> - <linux-iio@vger.kernel.org> - <linux-arm-kernel@lists.infradead.org> - <linux-kernel@vger.kernel.org> - " <devicetree@vger.kernel.org>\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "On Fri, 14 Sep 2018 12:48:28 +0530\n" @@ -69,7 +43,7 @@ "> +What:\t\t/sys/bus/iio/devices/iio:deviceX/in_voltageY_vccpsintlp\n" "> +Date:\t\tSeptember 2018\n" "> +KernelVersion:\t4.19.0\n" - "> +Contact:\tmnarani@xilinx.com\n" + "> +Contact:\tmnarani at xilinx.com\n" "> +Description:\n" "> +\t\tVoltage input for PS (Processing System) LPD (Low Power Domain)\n" "> +\t\tpower supply.\n" @@ -78,7 +52,7 @@ "> +What:\t\t/sys/bus/iio/devices/iio:deviceX/in_voltageY_vccpsintfp\n" "> +Date:\t\tSeptember 2018\n" "> +KernelVersion:\t4.19.0\n" - "> +Contact:\tmnarani@xilinx.com\n" + "> +Contact:\tmnarani at xilinx.com\n" "> +Description:\n" "> +\t\tVoltage input for PS (Processing System) FPD (Full Power Domain)\n" "> +\t\tpower supply.\n" @@ -87,7 +61,7 @@ "> +What:\t\t/sys/bus/iio/devices/iio:deviceX/in_voltageY_vccpsaux\n" "> +Date:\t\tSeptember 2018\n" "> +KernelVersion:\t4.19.0\n" - "> +Contact:\tmnarani@xilinx.com\n" + "> +Contact:\tmnarani at xilinx.com\n" "> +Description:\n" "> +\t\tVoltage input for PS (Processing System) Auxiliary power\n" "> +\t\tsupply.\n" @@ -96,7 +70,7 @@ "> +What:\t\t/sys/bus/iio/devices/iio:deviceX/in_voltageY_vccpsddr\n" "> +Date:\t\tSeptember 2018\n" "> +KernelVersion:\t4.19.0\n" - "> +Contact:\tmnarani@xilinx.com\n" + "> +Contact:\tmnarani at xilinx.com\n" "> +Description:\n" "> +\t\tVoltage input for PS (Processing System) I/O bank 504 (DDR\n" "> +\t\tPHY) power supply.\n" @@ -105,7 +79,7 @@ "> +What:\t\t/sys/bus/iio/devices/iio:deviceX/in_voltageY_vccpsio3\n" "> +Date:\t\tSeptember 2018\n" "> +KernelVersion:\t4.19.0\n" - "> +Contact:\tmnarani@xilinx.com\n" + "> +Contact:\tmnarani at xilinx.com\n" "> +Description:\n" "> +\t\tVoltage input for PS (Processing System) I/O bank 503\n" "> +\t\t(boot, config, JTAG, SRST, POR) power supply.\n" @@ -114,7 +88,7 @@ "> +What:\t\t/sys/bus/iio/devices/iio:deviceX/in_voltageY_vccpsio0\n" "> +Date:\t\tSeptember 2018\n" "> +KernelVersion:\t4.19.0\n" - "> +Contact:\tmnarani@xilinx.com\n" + "> +Contact:\tmnarani at xilinx.com\n" "> +Description:\n" "> +\t\tVoltage input for PS (Processing System) I/O bank 500\n" "> +\t\t(MIO[0:25]) power supply.\n" @@ -123,7 +97,7 @@ "> +What:\t\t/sys/bus/iio/devices/iio:deviceX/in_voltageY_vccpsio1\n" "> +Date:\t\tSeptember 2018\n" "> +KernelVersion:\t4.19.0\n" - "> +Contact:\tmnarani@xilinx.com\n" + "> +Contact:\tmnarani at xilinx.com\n" "> +Description:\n" "> +\t\tVoltage input for PS (Processing System) I/O bank 501\n" "> +\t\t(MIO[26:51]) power supply.\n" @@ -132,7 +106,7 @@ "> +What:\t\t/sys/bus/iio/devices/iio:deviceX/in_voltageY_vccpsio2\n" "> +Date:\t\tSeptember 2018\n" "> +KernelVersion:\t4.19.0\n" - "> +Contact:\tmnarani@xilinx.com\n" + "> +Contact:\tmnarani at xilinx.com\n" "> +Description:\n" "> +\t\tVoltage input for PS (Processing System) I/O bank 502\n" "> +\t\t(MIO[52:77]) power supply.\n" @@ -141,7 +115,7 @@ "> +What:\t\t/sys/bus/iio/devices/iio:deviceX/in_voltageY_psmgtravcc\n" "> +Date:\t\tSeptember 2018\n" "> +KernelVersion:\t4.19.0\n" - "> +Contact:\tmnarani@xilinx.com\n" + "> +Contact:\tmnarani at xilinx.com\n" "> +Description:\n" "> +\t\tVoltage input for PS (Processing System) GTR SerDes I/O\n" "> +\t\tpower supply.\n" @@ -150,7 +124,7 @@ "> +What:\t\t/sys/bus/iio/devices/iio:deviceX/in_voltageY_psmgtravtt\n" "> +Date:\t\tSeptember 2018\n" "> +KernelVersion:\t4.19.0\n" - "> +Contact:\tmnarani@xilinx.com\n" + "> +Contact:\tmnarani at xilinx.com\n" "> +Description:\n" "> +\t\tVoltage input for PS (Processing System) GTR SerDes\n" "> +\t\tterminators power supply.\n" @@ -159,7 +133,7 @@ "> +What:\t\t/sys/bus/iio/devices/iio:deviceX/in_voltageY_vccams\n" "> +Date:\t\tSeptember 2018\n" "> +KernelVersion:\t4.19.0\n" - "> +Contact:\tmnarani@xilinx.com\n" + "> +Contact:\tmnarani at xilinx.com\n" "> +Description:\n" "> +\t\tVoltage input for PS (Processing System) SYSMON ADC circuitry\n" "> +\t\tpower supply.\n" @@ -168,7 +142,7 @@ "> +What:\t\t/sys/bus/iio/devices/iio:deviceX/in_voltageY_vccint\n" "> +Date:\t\tSeptember 2018\n" "> +KernelVersion:\t4.19.0\n" - "> +Contact:\tmnarani@xilinx.com\n" + "> +Contact:\tmnarani at xilinx.com\n" "> +Description:\n" "> +\t\tVoltage input for PL (Programmable Logic) internal power supply.\n" "> +\n" @@ -176,7 +150,7 @@ "> +What:\t\t/sys/bus/iio/devices/iio:deviceX/in_voltageY_vccvrefp\n" "> +Date:\t\tSeptember 2018\n" "> +KernelVersion:\t4.19.0\n" - "> +Contact:\tmnarani@xilinx.com\n" + "> +Contact:\tmnarani at xilinx.com\n" "> +Description:\n" "> +\t\tVoltage input for PL (Programmable Logic) ADC positive V\n" "> +\t\treference power supply.\n" @@ -185,7 +159,7 @@ "> +What:\t\t/sys/bus/iio/devices/iio:deviceX/in_voltageY_vccvrefn\n" "> +Date:\t\tSeptember 2018\n" "> +KernelVersion:\t4.19.0\n" - "> +Contact:\tmnarani@xilinx.com\n" + "> +Contact:\tmnarani at xilinx.com\n" "> +Description:\n" "> +\t\tVoltage input for PL (Programmable Logic) ADC negative V\n" "> +\t\treference power supply.\n" @@ -194,7 +168,7 @@ "> +What:\t\t/sys/bus/iio/devices/iio:deviceX/in_voltageY_vccplintlp\n" "> +Date:\t\tSeptember 2018\n" "> +KernelVersion:\t4.19.0\n" - "> +Contact:\tmnarani@xilinx.com\n" + "> +Contact:\tmnarani at xilinx.com\n" "> +Description:\n" "> +\t\tVoltage input for PL (Programmable Logic) LPD (Low Power Domain)\n" "> +\t\tpower supply.\n" @@ -203,7 +177,7 @@ "> +What:\t\t/sys/bus/iio/devices/iio:deviceX/in_voltageY_vccplintfp\n" "> +Date:\t\tSeptember 2018\n" "> +KernelVersion:\t4.19.0\n" - "> +Contact:\tmnarani@xilinx.com\n" + "> +Contact:\tmnarani at xilinx.com\n" "> +Description:\n" "> +\t\tVoltage input for PL (Programmable Logic) FPD (Full Power\n" "> +\t\tDomain) power supply.\n" @@ -212,7 +186,7 @@ "> +What:\t\t/sys/bus/iio/devices/iio:deviceX/in_voltageY_vccplaux\n" "> +Date:\t\tSeptember 2018\n" "> +KernelVersion:\t4.19.0\n" - "> +Contact:\tmnarani@xilinx.com\n" + "> +Contact:\tmnarani at xilinx.com\n" "> +Description:\n" "> +\t\tVoltage input for PL (Programmable Logic) Auxiliary power\n" "> +\t\tsupply.\n" @@ -221,7 +195,7 @@ "> +What:\t\t/sys/bus/iio/devices/iio:deviceX/in_voltageY_vccvpvn\n" "> +Date:\t\tSeptember 2018\n" "> +KernelVersion:\t4.19.0\n" - "> +Contact:\tmnarani@xilinx.com\n" + "> +Contact:\tmnarani at xilinx.com\n" "> +Description:\n" "> +\t\tVoltage input for PL (Programmable Logic) Analog Input Pins\n" "> +\t\tpower supply.\n" @@ -230,7 +204,7 @@ "> +What:\t\t/sys/bus/iio/devices/iio:deviceX/in_voltageY_vuserZ\n" "> +Date:\t\tSeptember 2018\n" "> +KernelVersion:\t4.19.0\n" - "> +Contact:\tmnarani@xilinx.com\n" + "> +Contact:\tmnarani at xilinx.com\n" "> +Description:\n" "> +\t\tVoltage input for PL (Programmable Logic) Fabric Analog Wires \n" "> +\t\tpower supply. Z is the number in range of 0 to 3.\n" @@ -243,7 +217,7 @@ "> +What:\t\t/sys/bus/iio/devices/iio:deviceX/in_voltageY_vcc_pspll0\n" "> +Date:\t\tSeptember 2018\n" "> +KernelVersion:\t4.19.0\n" - "> +Contact:\tmnarani@xilinx.com\n" + "> +Contact:\tmnarani at xilinx.com\n" "> +Description:\n" "> +\t\tVoltage input for AMS (Analog Monitoring System) Systems PLLs\n" "> +\t\tpower supply.\n" @@ -252,7 +226,7 @@ "> +What:\t\t/sys/bus/iio/devices/iio:deviceX/in_voltageY_vcc_psbatt\n" "> +Date:\t\tSeptember 2018\n" "> +KernelVersion:\t4.19.0\n" - "> +Contact:\tmnarani@xilinx.com\n" + "> +Contact:\tmnarani at xilinx.com\n" "> +Description:\n" "> +\t\tVoltage input for AMS (Analog Monitoring System) Battery power\n" "> +\t\tsupply.\n" @@ -265,7 +239,7 @@ "> +What:\t\t/sys/bus/iio/devices/iio:deviceX/in_voltageY_vccbram\n" "> +Date:\t\tSeptember 2018\n" "> +KernelVersion:\t4.19.0\n" - "> +Contact:\tmnarani@xilinx.com\n" + "> +Contact:\tmnarani at xilinx.com\n" "> +Description:\n" "> +\t\tVoltage input for AMS (Analog Monitoring System) Block RAM power\n" "> +\t\tsupply.\n" @@ -274,7 +248,7 @@ "> +What:\t\t/sys/bus/iio/devices/iio:deviceX/in_voltageY_vccaux\n" "> +Date:\t\tSeptember 2018\n" "> +KernelVersion:\t4.19.0\n" - "> +Contact:\tmnarani@xilinx.com\n" + "> +Contact:\tmnarani at xilinx.com\n" "> +Description:\n" "> +\t\tVoltage input for AMS (Analog Monitoring System) Auxiliary power\n" "> +\t\tsupply.\n" @@ -283,7 +257,7 @@ "> +What:\t\t/sys/bus/iio/devices/iio:deviceX/in_voltageY_psddrpll\n" "> +Date:\t\tSeptember 2018\n" "> +KernelVersion:\t4.19.0\n" - "> +Contact:\tmnarani@xilinx.com\n" + "> +Contact:\tmnarani at xilinx.com\n" "> +Description:\n" "> +\t\tVoltage input for AMS (Analog Monitoring System) DDR I/O\n" "> +\t\tPLLs [0:5] power supply.\n" @@ -298,7 +272,7 @@ "\n" "> +Date:\t\tSeptember 2018\n" "> +KernelVersion:\t4.19.0\n" - "> +Contact:\tmnarani@xilinx.com\n" + "> +Contact:\tmnarani at xilinx.com\n" "> +Description:\n" "> +\t\tVoltage input for AMS (Analog Monitoring System) DDR controller\n" "> +\t\tpower supply.\n" @@ -308,7 +282,7 @@ "> +What:\t\t/sys/bus/iio/devices/iio:deviceX/in_tempY_ps_temp\n" "> +Date:\t\tSeptember 2018\n" "> +KernelVersion:\t4.19.0\n" - "> +Contact:\tmnarani@xilinx.com\n" + "> +Contact:\tmnarani at xilinx.com\n" "> +Description:\n" "> +\t\tTemperature input for PS (Processing System) RPU MPCore.\n" "> +\n" @@ -316,7 +290,7 @@ "> +What:\t\t/sys/bus/iio/devices/iio:deviceX/in_tempY_remote_temp\n" "> +Date:\t\tSeptember 2018\n" "> +KernelVersion:\t4.19.0\n" - "> +Contact:\tmnarani@xilinx.com\n" + "> +Contact:\tmnarani at xilinx.com\n" "> +Description:\n" "> +\t\tTemperature input for PS (Processing System) APU MPCore.\n" "\n" @@ -333,8 +307,8 @@ "> +What:\t\t/sys/bus/iio/devices/iio:deviceX/in_tempY_pl_temp\n" "> +Date:\t\tSeptember 2018\n" "> +KernelVersion:\t4.19.0\n" - "> +Contact:\tmnarani@xilinx.com\n" + "> +Contact:\tmnarani at xilinx.com\n" "> +Description:\n" "> +\t\tTemperature input for PL (Programmable Logic) SYSMON." -9adc0a9023a2e666b7d3cd92da33e1b6d0d64d1389d418b2425b8d43d0711593 +972b2bcb9c0f21449b57bda02cd8a117d35cc4ee26eae2e2cd07d4c91d866b9e
diff --git a/a/content_digest b/N2/content_digest index e1ee862..514f594 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -4,32 +4,32 @@ "Subject\0Re: [PATCH v2 2/4] iio: Documentation: Add Xilinx AMS sysfs documentation\0" "Date\0Sun, 16 Sep 2018 11:12:42 +0100\0" "To\0Manish Narani <manish.narani@xilinx.com>\0" - "Cc\0<knaack.h@gmx.de>" - <lars@metafoo.de> - <pmeerw@pmeerw.net> - <michal.simek@xilinx.com> - <robh+dt@kernel.org> - <mark.rutland@arm.com> - <sudeep.holla@arm.com> - <amit.kucheria@linaro.org> - <leoyang.li@nxp.com> - <broonie@kernel.org> - <arnaud.pouliquen@st.com> - <eugen.hristev@microchip.com> - <rdunlap@infradead.org> - <geert@linux-m68k.org> - <ak@it-klinger.de> - <freeman.liu@spreadtrum.com> - <lukas@wunner.de> - <vilhelm.gray@gmail.com> - <gregkh@linuxfoundation.org> - <kstewart@linuxfoundation.org> - <sgoud@xilinx.com> - <anirudh@xilinx.com> - <linux-iio@vger.kernel.org> - <linux-arm-kernel@lists.infradead.org> - <linux-kernel@vger.kernel.org> - " <devicetree@vger.kernel.org>\0" + "Cc\0knaack.h@gmx.de" + lars@metafoo.de + pmeerw@pmeerw.net + michal.simek@xilinx.com + robh+dt@kernel.org + mark.rutland@arm.com + sudeep.holla@arm.com + amit.kucheria@linaro.org + leoyang.li@nxp.com + broonie@kernel.org + arnaud.pouliquen@st.com + eugen.hristev@microchip.com + rdunlap@infradead.org + geert@linux-m68k.org + ak@it-klinger.de + freeman.liu@spreadtrum.com + lukas@wunner.de + vilhelm.gray@gmail.com + gregkh@linuxfoundation.org + kstewart@linuxfoundation.org + sgoud@xilinx.com + anirudh@xilinx.com + linux-iio@vger.kernel.org + linux-arm-kernel@lists.infradead.org + linux-kernel@vger.kernel.org + " devicetree@vger.kernel.org\0" "\00:1\0" "b\0" "On Fri, 14 Sep 2018 12:48:28 +0530\n" @@ -337,4 +337,4 @@ "> +Description:\n" "> +\t\tTemperature input for PL (Programmable Logic) SYSMON." -9adc0a9023a2e666b7d3cd92da33e1b6d0d64d1389d418b2425b8d43d0711593 +3e3f476ab951ff09aeeccbfda4f637c65e4cf2ec95c140101ce43022713f17d8
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