diff for duplicates of <20180917160252.6c016dbc@xhacker.debian> diff --git a/a/1.txt b/N1/1.txt index e90579e..161a492 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -37,7 +37,7 @@ index 000000000000..7331acf3874e + #address-cells = <1>; + #size-cells = <0>; + -+ cpu0: cpu at 0 { ++ cpu0: cpu@0 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x0>; @@ -46,7 +46,7 @@ index 000000000000..7331acf3874e + cpu-idle-states = <&CPU_SLEEP_0>; + }; + -+ cpu1: cpu at 1 { ++ cpu1: cpu@1 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x1>; @@ -55,7 +55,7 @@ index 000000000000..7331acf3874e + cpu-idle-states = <&CPU_SLEEP_0>; + }; + -+ cpu2: cpu at 2 { ++ cpu2: cpu@2 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x2>; @@ -64,7 +64,7 @@ index 000000000000..7331acf3874e + cpu-idle-states = <&CPU_SLEEP_0>; + }; + -+ cpu3: cpu at 3 { ++ cpu3: cpu@3 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x3>; @@ -116,13 +116,13 @@ index 000000000000..7331acf3874e + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + }; + -+ soc at f7000000 { ++ soc@f7000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xf7000000 0x1000000>; + -+ gic: interrupt-controller at 901000 { ++ gic: interrupt-controller@901000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-controller; @@ -133,13 +133,13 @@ index 000000000000..7331acf3874e + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + }; + -+ apb at e80000 { ++ apb@e80000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xe80000 0x10000>; + -+ uart0: serial at c00 { ++ uart0: serial@c00 { + compatible = "snps,dw-apb-uart"; + reg = <0xc00 0x100>; + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; @@ -148,13 +148,13 @@ index 000000000000..7331acf3874e + status = "disabled"; + }; + -+ gpio0: gpio at 1800 { ++ gpio0: gpio@1800 { + compatible = "snps,dw-apb-gpio"; + reg = <0x1800 0x400>; + #address-cells = <1>; + #size-cells = <0>; + -+ porta: gpio-port at 0 { ++ porta: gpio-port@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; @@ -166,13 +166,13 @@ index 000000000000..7331acf3874e + }; + }; + -+ gpio1: gpio at 2000 { ++ gpio1: gpio@2000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x2000 0x400>; + #address-cells = <1>; + #size-cells = <0>; + -+ portb: gpio-port at 1 { ++ portb: gpio-port@1 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; diff --git a/a/content_digest b/N1/content_digest index e7fe51e..6780cb0 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,8 +1,13 @@ "ref\020180917160015.05a1fc5b@xhacker.debian\0" - "From\0Jisheng.Zhang@synaptics.com (Jisheng Zhang)\0" + "From\0Jisheng Zhang <Jisheng.Zhang@synaptics.com>\0" "Subject\0[PATCH v2 3/3] arm64: dts: synaptics: add dtsi file for Synaptics AS370 SoC\0" "Date\0Mon, 17 Sep 2018 16:02:52 +0800\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Rob Herring <robh@kernel.org>" + " Mark Rutland <mark.rutland@arm.com>\0" + "Cc\0devicetree@vger.kernel.org" + linux-arm-kernel@lists.infradead.org + linux-kernel@vger.kernel.org + " Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>\0" "\00:1\0" "b\0" "Add initial dtsi file to support Synaptics AS370 SoC with quad\n" @@ -44,7 +49,7 @@ "+\t\t#address-cells = <1>;\n" "+\t\t#size-cells = <0>;\n" "+\n" - "+\t\tcpu0: cpu at 0 {\n" + "+\t\tcpu0: cpu@0 {\n" "+\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\treg = <0x0>;\n" @@ -53,7 +58,7 @@ "+\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n" "+\t\t};\n" "+\n" - "+\t\tcpu1: cpu at 1 {\n" + "+\t\tcpu1: cpu@1 {\n" "+\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\treg = <0x1>;\n" @@ -62,7 +67,7 @@ "+\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n" "+\t\t};\n" "+\n" - "+\t\tcpu2: cpu at 2 {\n" + "+\t\tcpu2: cpu@2 {\n" "+\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\treg = <0x2>;\n" @@ -71,7 +76,7 @@ "+\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n" "+\t\t};\n" "+\n" - "+\t\tcpu3: cpu at 3 {\n" + "+\t\tcpu3: cpu@3 {\n" "+\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\treg = <0x3>;\n" @@ -123,13 +128,13 @@ "+\t\t\t <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;\n" "+\t};\n" "+\n" - "+\tsoc at f7000000 {\n" + "+\tsoc@f7000000 {\n" "+\t\tcompatible = \"simple-bus\";\n" "+\t\t#address-cells = <1>;\n" "+\t\t#size-cells = <1>;\n" "+\t\tranges = <0 0 0xf7000000 0x1000000>;\n" "+\n" - "+\t\tgic: interrupt-controller at 901000 {\n" + "+\t\tgic: interrupt-controller@901000 {\n" "+\t\t\tcompatible = \"arm,gic-400\";\n" "+\t\t\t#interrupt-cells = <3>;\n" "+\t\t\tinterrupt-controller;\n" @@ -140,13 +145,13 @@ "+\t\t\tinterrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;\n" "+\t\t};\n" "+\n" - "+\t\tapb at e80000 {\n" + "+\t\tapb@e80000 {\n" "+\t\t\tcompatible = \"simple-bus\";\n" "+\t\t\t#address-cells = <1>;\n" "+\t\t\t#size-cells = <1>;\n" "+\t\t\tranges = <0 0xe80000 0x10000>;\n" "+\n" - "+\t\t\tuart0: serial at c00 {\n" + "+\t\t\tuart0: serial@c00 {\n" "+\t\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "+\t\t\t\treg = <0xc00 0x100>;\n" "+\t\t\t\tinterrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -155,13 +160,13 @@ "+\t\t\t\tstatus = \"disabled\";\n" "+\t\t\t};\n" "+\n" - "+\t\t\tgpio0: gpio at 1800 {\n" + "+\t\t\tgpio0: gpio@1800 {\n" "+\t\t\t\tcompatible = \"snps,dw-apb-gpio\";\n" "+\t\t\t\treg = <0x1800 0x400>;\n" "+\t\t\t\t#address-cells = <1>;\n" "+\t\t\t\t#size-cells = <0>;\n" "+\n" - "+\t\t\t\tporta: gpio-port at 0 {\n" + "+\t\t\t\tporta: gpio-port@0 {\n" "+\t\t\t\t\tcompatible = \"snps,dw-apb-gpio-port\";\n" "+\t\t\t\t\tgpio-controller;\n" "+\t\t\t\t\t#gpio-cells = <2>;\n" @@ -173,13 +178,13 @@ "+\t\t\t\t};\n" "+\t\t\t};\n" "+\n" - "+\t\t\tgpio1: gpio at 2000 {\n" + "+\t\t\tgpio1: gpio@2000 {\n" "+\t\t\t\tcompatible = \"snps,dw-apb-gpio\";\n" "+\t\t\t\treg = <0x2000 0x400>;\n" "+\t\t\t\t#address-cells = <1>;\n" "+\t\t\t\t#size-cells = <0>;\n" "+\n" - "+\t\t\t\tportb: gpio-port at 1 {\n" + "+\t\t\t\tportb: gpio-port@1 {\n" "+\t\t\t\t\tcompatible = \"snps,dw-apb-gpio-port\";\n" "+\t\t\t\t\tgpio-controller;\n" "+\t\t\t\t\t#gpio-cells = <2>;\n" @@ -196,4 +201,4 @@ "-- \n" 2.19.0 -d603da8533c8ed432aaa34ede08b43fe6922eac3bf006c6de7a3dcbc04095905 +699081f4d9c9a55da01dce21b78c4e2ace27186b0c17cf9a7380613acaba898c
diff --git a/a/1.txt b/N2/1.txt index e90579e..161a492 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -37,7 +37,7 @@ index 000000000000..7331acf3874e + #address-cells = <1>; + #size-cells = <0>; + -+ cpu0: cpu at 0 { ++ cpu0: cpu@0 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x0>; @@ -46,7 +46,7 @@ index 000000000000..7331acf3874e + cpu-idle-states = <&CPU_SLEEP_0>; + }; + -+ cpu1: cpu at 1 { ++ cpu1: cpu@1 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x1>; @@ -55,7 +55,7 @@ index 000000000000..7331acf3874e + cpu-idle-states = <&CPU_SLEEP_0>; + }; + -+ cpu2: cpu at 2 { ++ cpu2: cpu@2 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x2>; @@ -64,7 +64,7 @@ index 000000000000..7331acf3874e + cpu-idle-states = <&CPU_SLEEP_0>; + }; + -+ cpu3: cpu at 3 { ++ cpu3: cpu@3 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x3>; @@ -116,13 +116,13 @@ index 000000000000..7331acf3874e + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + }; + -+ soc at f7000000 { ++ soc@f7000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xf7000000 0x1000000>; + -+ gic: interrupt-controller at 901000 { ++ gic: interrupt-controller@901000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-controller; @@ -133,13 +133,13 @@ index 000000000000..7331acf3874e + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + }; + -+ apb at e80000 { ++ apb@e80000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xe80000 0x10000>; + -+ uart0: serial at c00 { ++ uart0: serial@c00 { + compatible = "snps,dw-apb-uart"; + reg = <0xc00 0x100>; + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; @@ -148,13 +148,13 @@ index 000000000000..7331acf3874e + status = "disabled"; + }; + -+ gpio0: gpio at 1800 { ++ gpio0: gpio@1800 { + compatible = "snps,dw-apb-gpio"; + reg = <0x1800 0x400>; + #address-cells = <1>; + #size-cells = <0>; + -+ porta: gpio-port at 0 { ++ porta: gpio-port@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; @@ -166,13 +166,13 @@ index 000000000000..7331acf3874e + }; + }; + -+ gpio1: gpio at 2000 { ++ gpio1: gpio@2000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x2000 0x400>; + #address-cells = <1>; + #size-cells = <0>; + -+ portb: gpio-port at 1 { ++ portb: gpio-port@1 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; diff --git a/a/content_digest b/N2/content_digest index e7fe51e..147ac5e 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,8 +1,13 @@ "ref\020180917160015.05a1fc5b@xhacker.debian\0" - "From\0Jisheng.Zhang@synaptics.com (Jisheng Zhang)\0" + "From\0Jisheng Zhang <Jisheng.Zhang@synaptics.com>\0" "Subject\0[PATCH v2 3/3] arm64: dts: synaptics: add dtsi file for Synaptics AS370 SoC\0" "Date\0Mon, 17 Sep 2018 16:02:52 +0800\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Rob Herring <robh@kernel.org>" + " Mark Rutland <mark.rutland@arm.com>\0" + "Cc\0<devicetree@vger.kernel.org>" + <linux-arm-kernel@lists.infradead.org> + <linux-kernel@vger.kernel.org> + " Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>\0" "\00:1\0" "b\0" "Add initial dtsi file to support Synaptics AS370 SoC with quad\n" @@ -44,7 +49,7 @@ "+\t\t#address-cells = <1>;\n" "+\t\t#size-cells = <0>;\n" "+\n" - "+\t\tcpu0: cpu at 0 {\n" + "+\t\tcpu0: cpu@0 {\n" "+\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\treg = <0x0>;\n" @@ -53,7 +58,7 @@ "+\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n" "+\t\t};\n" "+\n" - "+\t\tcpu1: cpu at 1 {\n" + "+\t\tcpu1: cpu@1 {\n" "+\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\treg = <0x1>;\n" @@ -62,7 +67,7 @@ "+\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n" "+\t\t};\n" "+\n" - "+\t\tcpu2: cpu at 2 {\n" + "+\t\tcpu2: cpu@2 {\n" "+\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\treg = <0x2>;\n" @@ -71,7 +76,7 @@ "+\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n" "+\t\t};\n" "+\n" - "+\t\tcpu3: cpu at 3 {\n" + "+\t\tcpu3: cpu@3 {\n" "+\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\treg = <0x3>;\n" @@ -123,13 +128,13 @@ "+\t\t\t <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;\n" "+\t};\n" "+\n" - "+\tsoc at f7000000 {\n" + "+\tsoc@f7000000 {\n" "+\t\tcompatible = \"simple-bus\";\n" "+\t\t#address-cells = <1>;\n" "+\t\t#size-cells = <1>;\n" "+\t\tranges = <0 0 0xf7000000 0x1000000>;\n" "+\n" - "+\t\tgic: interrupt-controller at 901000 {\n" + "+\t\tgic: interrupt-controller@901000 {\n" "+\t\t\tcompatible = \"arm,gic-400\";\n" "+\t\t\t#interrupt-cells = <3>;\n" "+\t\t\tinterrupt-controller;\n" @@ -140,13 +145,13 @@ "+\t\t\tinterrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;\n" "+\t\t};\n" "+\n" - "+\t\tapb at e80000 {\n" + "+\t\tapb@e80000 {\n" "+\t\t\tcompatible = \"simple-bus\";\n" "+\t\t\t#address-cells = <1>;\n" "+\t\t\t#size-cells = <1>;\n" "+\t\t\tranges = <0 0xe80000 0x10000>;\n" "+\n" - "+\t\t\tuart0: serial at c00 {\n" + "+\t\t\tuart0: serial@c00 {\n" "+\t\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "+\t\t\t\treg = <0xc00 0x100>;\n" "+\t\t\t\tinterrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -155,13 +160,13 @@ "+\t\t\t\tstatus = \"disabled\";\n" "+\t\t\t};\n" "+\n" - "+\t\t\tgpio0: gpio at 1800 {\n" + "+\t\t\tgpio0: gpio@1800 {\n" "+\t\t\t\tcompatible = \"snps,dw-apb-gpio\";\n" "+\t\t\t\treg = <0x1800 0x400>;\n" "+\t\t\t\t#address-cells = <1>;\n" "+\t\t\t\t#size-cells = <0>;\n" "+\n" - "+\t\t\t\tporta: gpio-port at 0 {\n" + "+\t\t\t\tporta: gpio-port@0 {\n" "+\t\t\t\t\tcompatible = \"snps,dw-apb-gpio-port\";\n" "+\t\t\t\t\tgpio-controller;\n" "+\t\t\t\t\t#gpio-cells = <2>;\n" @@ -173,13 +178,13 @@ "+\t\t\t\t};\n" "+\t\t\t};\n" "+\n" - "+\t\t\tgpio1: gpio at 2000 {\n" + "+\t\t\tgpio1: gpio@2000 {\n" "+\t\t\t\tcompatible = \"snps,dw-apb-gpio\";\n" "+\t\t\t\treg = <0x2000 0x400>;\n" "+\t\t\t\t#address-cells = <1>;\n" "+\t\t\t\t#size-cells = <0>;\n" "+\n" - "+\t\t\t\tportb: gpio-port at 1 {\n" + "+\t\t\t\tportb: gpio-port@1 {\n" "+\t\t\t\t\tcompatible = \"snps,dw-apb-gpio-port\";\n" "+\t\t\t\t\tgpio-controller;\n" "+\t\t\t\t\t#gpio-cells = <2>;\n" @@ -196,4 +201,4 @@ "-- \n" 2.19.0 -d603da8533c8ed432aaa34ede08b43fe6922eac3bf006c6de7a3dcbc04095905 +73f038225b2add40b9157c6b68309cec49a650a7325bae55405b16ef3fec5c45
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.