From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [v5,4/7] dmaengine: xilinx_dma: program hardware supported buffer length From: Vinod Koul Message-Id: <20180918162508.GD2613@vkoul-mobl> Date: Tue, 18 Sep 2018 09:25:08 -0700 To: Andrea Merello Cc: dan.j.williams@intel.com, michal.simek@xilinx.com, appana.durga.rao@xilinx.com, dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, radhey.shyam.pandey@xilinx.com List-ID: T24gMDctMDktMTgsIDA4OjI0LCBBbmRyZWEgTWVyZWxsbyB3cm90ZToKPiBGcm9tOiBSYWRoZXkg U2h5YW0gUGFuZGV5IDxyYWRoZXkuc2h5YW0ucGFuZGV5QHhpbGlueC5jb20+Cj4gCj4gQVhJLURN QSBJUCBzdXBwb3J0cyBjb25maWd1cmFibGUgKGNfc2dfbGVuZ3RoX3dpZHRoKSBidWZmZXIgbGVu Z3RoCj4gcmVnaXN0ZXIgd2lkdGgsIGhlbmNlIHJlYWQgYnVmZmVyIGxlbmd0aCAoeGxueCxzZy1s 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VFJBTlNfTEVOKTsKPiArCQkJICAgIGNoYW4tPnhkZXYtPm1heF9idWZmZXJfbGVuKTsKCmhtbSB3 aHkgbm90IGFkZCBtYXhfYnVmZmVyX2xlbiBpbiBwYXRjaCAxIGFnYWluLCBhbmQgdGhlbiB1c2Ug ZGVmYXVsdApsZW4gYXMgWElMSU5YX0RNQV9NQVhfVFJBTlNfTEVOIGFuZCBhZGQgbXVsdGlwbGUg bGVuZ3RocyBoZXJlIDopCgotIAp+Vmlub2QK From mboxrd@z Thu Jan 1 00:00:00 1970 From: vkoul@kernel.org (Vinod) Date: Tue, 18 Sep 2018 09:25:08 -0700 Subject: [PATCH v5 4/7] dmaengine: xilinx_dma: program hardware supported buffer length In-Reply-To: <20180907062502.8241-4-andrea.merello@gmail.com> References: <20180907062502.8241-1-andrea.merello@gmail.com> <20180907062502.8241-4-andrea.merello@gmail.com> Message-ID: <20180918162508.GD2613@vkoul-mobl> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 07-09-18, 08:24, Andrea Merello wrote: > From: Radhey Shyam Pandey > > AXI-DMA IP supports configurable (c_sg_length_width) buffer length > register width, hence read buffer length (xlnx,sg-length-width) DT > property and ensure that driver doesn't program buffer length > exceeding the supported limit. For VDMA and CDMA there is no change. > > Cc: Rob Herring > Cc: Mark Rutland > Cc: devicetree at vger.kernel.org > Signed-off-by: Radhey Shyam Pandey > Signed-off-by: Michal Simek > Signed-off-by: Andrea Merello [rebase, reword] > --- > Changes in v2: > - drop original patch and replace with the one in Xilinx tree > Changes in v3: > - cc DT maintainers/ML > Changes in v4: > - upper bound for the property should be 26, not 23 > - add warn for width > 23 as per xilinx original patch > - rework due to changes introduced in 1/6 > Changes in v5: > None > --- > drivers/dma/xilinx/xilinx_dma.c | 36 +++++++++++++++++++++++++-------- > 1 file changed, 28 insertions(+), 8 deletions(-) > > diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c > index aaa6de8a70e4..b17f24e4ec35 100644 > --- a/drivers/dma/xilinx/xilinx_dma.c > +++ b/drivers/dma/xilinx/xilinx_dma.c > @@ -158,7 +158,9 @@ > #define XILINX_DMA_REG_BTT 0x28 > > /* AXI DMA Specific Masks/Bit fields */ > -#define XILINX_DMA_MAX_TRANS_LEN GENMASK(22, 0) > +#define XILINX_DMA_MAX_TRANS_LEN_MIN 8 > +#define XILINX_DMA_MAX_TRANS_LEN_MAX 23 > +#define XILINX_DMA_V2_MAX_TRANS_LEN_MAX 26 > #define XILINX_DMA_CR_COALESCE_MAX GENMASK(23, 16) > #define XILINX_DMA_CR_CYCLIC_BD_EN_MASK BIT(4) > #define XILINX_DMA_CR_COALESCE_SHIFT 16 > @@ -418,6 +420,7 @@ struct xilinx_dma_config { > * @rxs_clk: DMA s2mm stream clock > * @nr_channels: Number of channels DMA device supports > * @chan_id: DMA channel identifier > + * @max_buffer_len: Max buffer length > */ > struct xilinx_dma_device { > void __iomem *regs; > @@ -437,6 +440,7 @@ struct xilinx_dma_device { > struct clk *rxs_clk; > u32 nr_channels; > u32 chan_id; > + u32 max_buffer_len; > }; > > /* Macros */ > @@ -964,7 +968,7 @@ static int xilinx_dma_calc_copysize(struct xilinx_dma_chan *chan, > int size, int done) > { > size_t copy = min_t(size_t, size - done, > - XILINX_DMA_MAX_TRANS_LEN); > + chan->xdev->max_buffer_len); hmm why not add max_buffer_len in patch 1 again, and then use default len as XILINX_DMA_MAX_TRANS_LEN and add multiple lengths here :) - ~Vinod From mboxrd@z Thu Jan 1 00:00:00 1970 From: Vinod Subject: Re: [PATCH v5 4/7] dmaengine: xilinx_dma: program hardware supported buffer length Date: Tue, 18 Sep 2018 09:25:08 -0700 Message-ID: <20180918162508.GD2613@vkoul-mobl> References: <20180907062502.8241-1-andrea.merello@gmail.com> <20180907062502.8241-4-andrea.merello@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: <20180907062502.8241-4-andrea.merello@gmail.com> Sender: linux-kernel-owner@vger.kernel.org To: Andrea Merello Cc: dan.j.williams@intel.com, michal.simek@xilinx.com, appana.durga.rao@xilinx.com, dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, radhey.shyam.pandey@xilinx.com List-Id: devicetree@vger.kernel.org On 07-09-18, 08:24, Andrea Merello wrote: > From: Radhey Shyam Pandey > > AXI-DMA IP supports configurable (c_sg_length_width) buffer length > register width, hence read buffer length (xlnx,sg-length-width) DT > property and ensure that driver doesn't program buffer length > exceeding the supported limit. For VDMA and CDMA there is no change. > > Cc: Rob Herring > Cc: Mark Rutland > Cc: devicetree@vger.kernel.org > Signed-off-by: Radhey Shyam Pandey > Signed-off-by: Michal Simek > Signed-off-by: Andrea Merello [rebase, reword] > --- > Changes in v2: > - drop original patch and replace with the one in Xilinx tree > Changes in v3: > - cc DT maintainers/ML > Changes in v4: > - upper bound for the property should be 26, not 23 > - add warn for width > 23 as per xilinx original patch > - rework due to changes introduced in 1/6 > Changes in v5: > None > --- > drivers/dma/xilinx/xilinx_dma.c | 36 +++++++++++++++++++++++++-------- > 1 file changed, 28 insertions(+), 8 deletions(-) > > diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c > index aaa6de8a70e4..b17f24e4ec35 100644 > --- a/drivers/dma/xilinx/xilinx_dma.c > +++ b/drivers/dma/xilinx/xilinx_dma.c > @@ -158,7 +158,9 @@ > #define XILINX_DMA_REG_BTT 0x28 > > /* AXI DMA Specific Masks/Bit fields */ > -#define XILINX_DMA_MAX_TRANS_LEN GENMASK(22, 0) > +#define XILINX_DMA_MAX_TRANS_LEN_MIN 8 > +#define XILINX_DMA_MAX_TRANS_LEN_MAX 23 > +#define XILINX_DMA_V2_MAX_TRANS_LEN_MAX 26 > #define XILINX_DMA_CR_COALESCE_MAX GENMASK(23, 16) > #define XILINX_DMA_CR_CYCLIC_BD_EN_MASK BIT(4) > #define XILINX_DMA_CR_COALESCE_SHIFT 16 > @@ -418,6 +420,7 @@ struct xilinx_dma_config { > * @rxs_clk: DMA s2mm stream clock > * @nr_channels: Number of channels DMA device supports > * @chan_id: DMA channel identifier > + * @max_buffer_len: Max buffer length > */ > struct xilinx_dma_device { > void __iomem *regs; > @@ -437,6 +440,7 @@ struct xilinx_dma_device { > struct clk *rxs_clk; > u32 nr_channels; > u32 chan_id; > + u32 max_buffer_len; > }; > > /* Macros */ > @@ -964,7 +968,7 @@ static int xilinx_dma_calc_copysize(struct xilinx_dma_chan *chan, > int size, int done) > { > size_t copy = min_t(size_t, size - done, > - XILINX_DMA_MAX_TRANS_LEN); > + chan->xdev->max_buffer_len); hmm why not add max_buffer_len in patch 1 again, and then use default len as XILINX_DMA_MAX_TRANS_LEN and add multiple lengths here :) - ~Vinod