From: Andrea Parri <andrea.parri@amarulasolutions.com>
To: Guo Ren <ren_guo@c-sky.com>
Cc: akpm@linux-foundation.org, arnd@arndb.de,
daniel.lezcano@linaro.org, davem@davemloft.net,
gregkh@linuxfoundation.org, jason@lakedaemon.net,
marc.zyngier@arm.com, mark.rutland@arm.com,
mchehab+samsung@kernel.org, peterz@infradead.org,
robh@kernel.org, robh+dt@kernel.org, tglx@linutronix.de,
linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org,
devicetree@vger.kernel.org, green.hu@gmail.com,
palmer@sifive.com
Subject: Re: [PATCH V5 17/30] csky: Misc headers
Date: Tue, 25 Sep 2018 12:08:03 +0200 [thread overview]
Message-ID: <20180925100803.GA6891@andrea> (raw)
In-Reply-To: <5ae1990e1863fe2293bba1e5ec0408892a9a7f0c.1537789737.git.ren_guo@c-sky.com>
Hi Guo,
> +/*
> + * set_bit - Atomically set a bit in memory
> + * @nr: the bit to set
> + * @addr: the address to start counting from
> + *
> + * This function is atomic and may not be reordered. See __set_bit()
> + * if you do not require the atomic guarantees.
> + *
> + * Note: there are no guarantees that this function will not be reordered
> + * on non x86 architectures, so if you are writing portable code,
> + * make sure not to rely on its reordering guarantees.
> + *
> + * Note that @nr may be almost arbitrarily large; this function is not
> + * restricted to acting on a single-word quantity.
> + */
> +static inline void set_bit(int nr, volatile unsigned long *addr)
> +{
> + unsigned long mask = BIT_MASK(nr);
> + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
> + unsigned long tmp;
> +
> + /* *p |= mask; */
> + smp_mb();
> + asm volatile (
> + "1: ldex.w %0, (%2) \n"
> + " or32 %0, %0, %1 \n"
> + " stex.w %0, (%2) \n"
> + " bez %0, 1b \n"
> + : "=&r"(tmp)
> + : "r"(mask), "r"(p)
> + : "memory");
> + smp_mb();
> +}
> +
> +/**
> + * clear_bit - Clears a bit in memory
> + * @nr: Bit to clear
> + * @addr: Address to start counting from
> + *
> + * clear_bit() is atomic and may not be reordered. However, it does
> + * not contain a memory barrier, so if it is used for locking purposes,
> + * you should call smp_mb__before_atomic() and/or smp_mb__after_atomic()
> + * in order to ensure changes are visible on other processors.
> + */
> +static inline void clear_bit(int nr, volatile unsigned long *addr)
> +{
> + unsigned long mask = BIT_MASK(nr);
> + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
> + unsigned long tmp;
> +
> + /* *p &= ~mask; */
> + mask = ~mask;
> + smp_mb();
> + asm volatile (
> + "1: ldex.w %0, (%2) \n"
> + " and32 %0, %0, %1 \n"
> + " stex.w %0, (%2) \n"
> + " bez %0, 1b \n"
> + : "=&r"(tmp)
> + : "r"(mask), "r"(p)
> + : "memory");
> + smp_mb();
> +}
> +
> +/**
> + * change_bit - Toggle a bit in memory
> + * @nr: Bit to change
> + * @addr: Address to start counting from
> + *
> + * change_bit() is atomic and may not be reordered. It may be
> + * reordered on other architectures than x86.
> + * Note that @nr may be almost arbitrarily large; this function is not
> + * restricted to acting on a single-word quantity.
> + */
> +static inline void change_bit(int nr, volatile unsigned long *addr)
> +{
> + unsigned long mask = BIT_MASK(nr);
> + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
> + unsigned long tmp;
> +
> + /* *p ^= mask; */
> + smp_mb();
> + asm volatile (
> + "1: ldex.w %0, (%2) \n"
> + " xor32 %0, %0, %1 \n"
> + " stex.w %0, (%2) \n"
> + " bez %0, 1b \n"
> + : "=&r"(tmp)
> + : "r"(mask), "r"(p)
> + : "memory");
> + smp_mb();
> +}
The {set,clear,change}_bit() operations don't have to be ordered: you
might want to remove the above smp_mb()s (and adjust the comments).
Andrea
next prev parent reply other threads:[~2018-09-25 10:08 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-09-24 14:34 [PATCH V5 00/30] C-SKY(csky) Linux Kernel Port Guo Ren
2018-09-24 14:36 ` [PATCH V5 01/30] csky: Build infrastructure Guo Ren
2018-09-24 14:36 ` [PATCH V5 02/30] csky: defconfig Guo Ren
2018-09-24 14:36 ` [PATCH V5 03/30] csky: Kernel booting Guo Ren
2018-09-24 14:36 ` [PATCH V5 04/30] csky: Exception handling and mm-fault Guo Ren
2018-09-24 14:36 ` [PATCH V5 05/30] csky: System Call Guo Ren
2018-09-24 14:36 ` [PATCH V5 06/30] csky: Cache and TLB routines Guo Ren
2018-09-25 7:24 ` Peter Zijlstra
2018-09-27 5:27 ` Guo Ren
2018-09-27 7:08 ` Peter Zijlstra
2018-09-27 8:11 ` Guo Ren
2018-09-27 9:01 ` Peter Zijlstra
2018-09-27 11:19 ` Guo Ren
2018-09-24 14:36 ` [PATCH V5 07/30] csky: MMU and page table management Guo Ren
2018-09-24 14:36 ` [PATCH V5 08/30] csky: Process management and Signal Guo Ren
2018-09-24 14:36 ` [PATCH V5 09/30] csky: VDSO and rt_sigreturn Guo Ren
2018-09-24 14:36 ` [PATCH V5 10/30] csky: IRQ handling Guo Ren
2018-09-24 14:36 ` [PATCH V5 11/30] csky: Atomic operations Guo Ren
2018-09-24 14:36 ` [PATCH V5 12/30] csky: ELF and module probe Guo Ren
2018-09-24 14:36 ` [PATCH V5 13/30] csky: Library functions Guo Ren
2018-09-24 14:36 ` [PATCH V5 14/30] csky: User access Guo Ren
2018-09-24 23:39 ` [PATCH V5 15/30] csky: Debug and Ptrace GDB Guo Ren
2018-09-24 23:39 ` [PATCH V5 16/30] csky: SMP support Guo Ren
2018-09-24 23:39 ` [PATCH V5 17/30] csky: Misc headers Guo Ren
2018-09-25 10:08 ` Andrea Parri [this message]
2018-09-25 10:45 ` Peter Zijlstra
2018-09-27 5:07 ` Guo Ren
2018-09-24 23:39 ` [PATCH V5 18/30] dt-bindings: csky CPU Bindings Guo Ren
2018-09-27 16:43 ` Rob Herring
2018-09-28 1:03 ` Guo Ren
2018-09-28 11:32 ` Rob Herring
2018-09-28 11:42 ` Guo Ren
2018-09-24 23:39 ` [PATCH V5 19/30] dt-bindings: Add vendor prefix for csky Guo Ren
2018-09-27 16:44 ` Rob Herring
2018-09-27 16:44 ` Rob Herring
2018-09-27 16:44 ` Rob Herring
2018-09-24 23:39 ` [PATCH V5 20/30] csky/dma: bugfix dma_sync_for_cpu/device Guo Ren
2018-09-24 23:39 ` [PATCH V5 21/30] csky: remove irq_mapping from smp.c Guo Ren
2018-09-24 23:39 ` [PATCH V5 22/30] irqchip: add C-SKY SMP interrupt controller Guo Ren
2018-09-24 23:39 ` [PATCH V5 23/30] dt-bindings: interrupt-controller: C-SKY SMP intc Guo Ren
2018-09-27 16:50 ` Rob Herring
2018-09-28 1:07 ` Guo Ren
2018-09-24 23:39 ` [PATCH V5 24/30] clocksource: add C-SKY SMP timer Guo Ren
2018-09-24 23:39 ` [PATCH V5 25/30] dt-bindings: timer: C-SKY Multi-processor timer Guo Ren
2018-09-27 17:35 ` Rob Herring
2018-09-28 1:08 ` Guo Ren
2018-09-24 23:39 ` [PATCH V5 26/30] MAINTAINERS: Add csky Guo Ren
2018-09-24 23:39 ` [PATCH V5 27/30] dt-bindings: interrupt-controller: C-SKY APB intc Guo Ren
2018-09-27 17:36 ` Rob Herring
2018-09-27 17:36 ` Rob Herring
2018-09-27 17:36 ` Rob Herring
2018-09-24 23:39 ` [PATCH V5 28/30] irqchip: add C-SKY APB bus interrupt controller Guo Ren
2018-09-24 23:39 ` [PATCH V5 29/30] dt-bindings: timer: gx6605s SOC timer Guo Ren
2018-09-24 23:39 ` [PATCH V5 30/30] clocksource: add gx6605s SOC system timer Guo Ren
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