From mboxrd@z Thu Jan 1 00:00:00 1970 From: miquel.raynal@bootlin.com (Miquel Raynal) Date: Tue, 2 Oct 2018 10:18:22 +0200 Subject: [PATCH v6 09/14] irqchip/irq-mvebu-icu: add support for System Error Interrupts (SEI) In-Reply-To: <86in2lvbmb.wl-marc.zyngier@arm.com> References: <20181001141358.31508-1-miquel.raynal@bootlin.com> <20181001141358.31508-10-miquel.raynal@bootlin.com> <86in2lvbmb.wl-marc.zyngier@arm.com> Message-ID: <20181002101822.107c2016@xps13> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi Marc, Marc Zyngier wrote on Mon, 01 Oct 2018 18:07:56 +0100: > On Mon, 01 Oct 2018 15:13:53 +0100, > Miquel Raynal wrote: > > > > So far the ICU only handled NSR interrupts through GICP. An SEI driver > > provides an MSI domain through which it is possible to raise SEI, so > > let's add SEI support to the ICU driver. > > > > Handle the NSR probe function in a more generic way to support other > > type of interrupts. > > > > Each interrupt domain is a tree domain to avoid allocation the 207 > > entries each time. Instead an ICU-wide bitmap is used to follow ICU > > slot allocations. > > > > Signed-off-by: Miquel Raynal > > --- > > drivers/irqchip/irq-mvebu-icu.c | 173 +++++++++++++++++++++++++------- > > 1 file changed, 139 insertions(+), 34 deletions(-) > > > > diff --git a/drivers/irqchip/irq-mvebu-icu.c b/drivers/irqchip/irq-mvebu-icu.c > > index c79d2cb787a0..21e7c5830fcc 100644 > > --- a/drivers/irqchip/irq-mvebu-icu.c > > +++ b/drivers/irqchip/irq-mvebu-icu.c > > @@ -27,6 +27,10 @@ > > #define ICU_SETSPI_NSR_AH 0x14 > > #define ICU_CLRSPI_NSR_AL 0x18 > > #define ICU_CLRSPI_NSR_AH 0x1c > > +#define ICU_SET_SEI_AL 0x50 > > +#define ICU_SET_SEI_AH 0x54 > > +#define ICU_CLR_SEI_AL 0x58 > > +#define ICU_CLR_SEI_AH 0x5C > > #define ICU_INT_CFG(x) (0x100 + 4 * (x)) > > #define ICU_INT_ENABLE BIT(24) > > #define ICU_IS_EDGE BIT(28) > > @@ -37,11 +41,27 @@ > > #define ICU_SATA0_ICU_ID 109 > > #define ICU_SATA1_ICU_ID 107 > > > > +struct mvebu_icu_subset_data { > > + unsigned int icu_group; > > + unsigned int offset_set_ah; > > + unsigned int offset_set_al; > > + unsigned int offset_clr_ah; > > + unsigned int offset_clr_al; > > +}; > > + > > struct mvebu_icu { > > - struct irq_chip irq_chip; > > void __iomem *base; > > struct device *dev; > > + > > + /* Lock on interrupt allocations/releases */ > > + struct mutex msi_lock; > > + DECLARE_BITMAP(msi_bitmap, ICU_MAX_IRQS); > > +}; > > + > > +struct mvebu_icu_msi_data { > > + struct mvebu_icu *icu; > > atomic_t initialized; > > + const struct mvebu_icu_subset_data *subset_data; > > }; > > > > struct mvebu_icu_irq_data { > > @@ -52,28 +72,38 @@ struct mvebu_icu_irq_data { > > > > DEFINE_STATIC_KEY_FALSE(legacy_bindings); > > > > -static void mvebu_icu_init(struct mvebu_icu *icu, struct msi_msg *msg) > > +static void mvebu_icu_init(struct mvebu_icu *icu, > > + struct mvebu_icu_msi_data *msi_data, > > + struct msi_msg *msg) > > { > > - if (atomic_cmpxchg(&icu->initialized, false, true)) > > + const struct mvebu_icu_subset_data *subset = msi_data->subset_data; > > + > > + if (atomic_cmpxchg(&msi_data->initialized, false, true)) > > + return; > > + > > + /* Set 'SET' ICU SPI message address in AP */ > > + writel_relaxed(msg[0].address_hi, icu->base + subset->offset_set_ah); > > + writel_relaxed(msg[0].address_lo, icu->base + subset->offset_set_al); > > + > > + if (subset->icu_group != ICU_GRP_NSR) > > return; > > > > - /* Set Clear/Set ICU SPI message address in AP */ > > - writel_relaxed(msg[0].address_hi, icu->base + ICU_SETSPI_NSR_AH); > > - writel_relaxed(msg[0].address_lo, icu->base + ICU_SETSPI_NSR_AL); > > - writel_relaxed(msg[1].address_hi, icu->base + ICU_CLRSPI_NSR_AH); > > - writel_relaxed(msg[1].address_lo, icu->base + ICU_CLRSPI_NSR_AL); > > + /* Set 'CLEAR' ICU SPI message address in AP (level-MSI only) */ > > + writel_relaxed(msg[1].address_hi, icu->base + subset->offset_clr_ah); > > + writel_relaxed(msg[1].address_lo, icu->base + subset->offset_clr_al); > > } > > > > static void mvebu_icu_write_msg(struct msi_desc *desc, struct msi_msg *msg) > > { > > struct irq_data *d = irq_get_irq_data(desc->irq); > > + struct mvebu_icu_msi_data *msi_data = platform_msi_get_host_data(d->domain); > > struct mvebu_icu_irq_data *icu_irqd = d->chip_data; > > struct mvebu_icu *icu = icu_irqd->icu; > > unsigned int icu_int; > > > > if (msg->address_lo || msg->address_hi) { > > - /* One off initialization */ > > - mvebu_icu_init(icu, msg); > > + /* One off initialization per domain */ > > + mvebu_icu_init(icu, msi_data, msg); > > /* Configure the ICU with irq number & type */ > > icu_int = msg->data | ICU_INT_ENABLE; > > if (icu_irqd->type & IRQ_TYPE_EDGE_RISING) > > @@ -103,10 +133,29 @@ static void mvebu_icu_write_msg(struct msi_desc *desc, struct msi_msg *msg) > > } > > } > > > > +static struct irq_chip mvebu_icu_nsr_chip = { > > + .name = "ICU-NSR", > > + .irq_mask = irq_chip_mask_parent, > > + .irq_unmask = irq_chip_unmask_parent, > > + .irq_eoi = irq_chip_eoi_parent, > > + .irq_set_type = irq_chip_set_type_parent, > > + .irq_set_affinity = irq_chip_set_affinity_parent, > > +}; > > + > > +static struct irq_chip mvebu_icu_sei_chip = { > > + .name = "ICU-SEI", > > + .irq_ack = irq_chip_ack_parent, > > + .irq_mask = irq_chip_mask_parent, > > + .irq_unmask = irq_chip_unmask_parent, > > + .irq_set_type = irq_chip_set_type_parent, > > + .irq_set_affinity = irq_chip_set_affinity_parent, > > +}; > > + > > static int > > mvebu_icu_irq_domain_translate(struct irq_domain *d, struct irq_fwspec *fwspec, > > unsigned long *hwirq, unsigned int *type) > > { > > + struct mvebu_icu_msi_data *msi_data = platform_msi_get_host_data(d); > > struct mvebu_icu *icu = platform_msi_get_host_data(d); > > unsigned int param_count = static_branch_unlikely(&legacy_bindings) ? 3 : 2; > > > > @@ -128,6 +177,14 @@ mvebu_icu_irq_domain_translate(struct irq_domain *d, struct irq_fwspec *fwspec, > > } else { > > *hwirq = fwspec->param[0]; > > *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK; > > + > > + /* > > + * The ICU receives level interrupts. While the NSR are also > > + * level interrupts, SEI are edge interrupts. Force the type > > + * here in this case. > > + */ > > + if (msi_data->subset_data->icu_group == ICU_GRP_SEI) > > + *type = IRQ_TYPE_EDGE_RISING; > > Please add a comment indicating that this makes the interrupt handling > unreliable. I really don't want anyone to think that this kind of hack > is to be relied upon (interrupt fires, driver ignores the interrupt > and legitimately expects it to fire again, interrupts doesn't fire, > device is dead). Done. Added the mention: "Note that this makes the interrupt handling unreliable." > > > } > > > > if (*hwirq >= ICU_MAX_IRQS) { > > @@ -138,6 +195,25 @@ mvebu_icu_irq_domain_translate(struct irq_domain *d, struct irq_fwspec *fwspec, > > return 0; > > } > > > > +static int mvebu_icu_msi_bitmap_region_alloc(struct mvebu_icu *icu, int hwirq) > > +{ > > + int ret; > > + > > + mutex_lock(&icu->msi_lock); > > + ret = test_and_set_bit(hwirq, icu->msi_bitmap); > > + mutex_unlock(&icu->msi_lock); > > test_and_set_bit is atomic. Why do we have a mutex to guard it? Mutexes removed, that's right we don't need them anymore since we passed to test_and_set_bit(). > More importantly, what is it used for? You only seem to use it as some > paranoid check to validate the DT, which makes no sense to me. I'm not sure if this test is really paranoid as, in theory, we might have more interrupts than available slots in the ICU and I feel good warning the user if an ICU slot is re-used. Anyway, if you prefer not to check that, I will simply get rid of the whole bitmap which then makes no more sense. Thanks, Miqu?l From mboxrd@z Thu Jan 1 00:00:00 1970 From: Miquel Raynal Subject: Re: [PATCH v6 09/14] irqchip/irq-mvebu-icu: add support for System Error Interrupts (SEI) Date: Tue, 2 Oct 2018 10:18:22 +0200 Message-ID: <20181002101822.107c2016@xps13> References: <20181001141358.31508-1-miquel.raynal@bootlin.com> <20181001141358.31508-10-miquel.raynal@bootlin.com> <86in2lvbmb.wl-marc.zyngier@arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <86in2lvbmb.wl-marc.zyngier@arm.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Marc Zyngier Cc: Mark Rutland , Andrew Lunn , Jason Cooper , devicetree@vger.kernel.org, Antoine Tenart , Catalin Marinas , Gregory Clement , Haim Boot , Will Deacon , Maxime Chevallier , Nadav Haklai , Rob Herring , Thomas Petazzoni , Thomas Gleixner , Hanna Hawa , linux-arm-kernel@lists.infradead.org, Sebastian Hesselbarth List-Id: devicetree@vger.kernel.org SGkgTWFyYywKCk1hcmMgWnluZ2llciA8bWFyYy56eW5naWVyQGFybS5jb20+IHdyb3RlIG9uIE1v biwgMDEgT2N0IDIwMTggMTg6MDc6NTYKKzAxMDA6Cgo+IE9uIE1vbiwgMDEgT2N0IDIwMTggMTU6 MTM6NTMgKzAxMDAsCj4gTWlxdWVsIFJheW5hbCA8bWlxdWVsLnJheW5hbEBib290bGluLmNvbT4g d3JvdGU6Cj4gPiAKPiA+IFNvIGZhciB0aGUgSUNVIG9ubHkgaGFuZGxlZCBOU1IgaW50ZXJydXB0 cyB0aHJvdWdoIEdJQ1AuIEFuIFNFSSBkcml2ZXIKPiA+IHByb3ZpZGVzIGFuIE1TSSBkb21haW4g dGhyb3VnaCB3aGljaCBpdCBpcyBwb3NzaWJsZSB0byByYWlzZSBTRUksIHNvCj4gPiBsZXQncyBh ZGQgU0VJIHN1cHBvcnQgdG8gdGhlIElDVSBkcml2ZXIuCj4gPiAKPiA+IEhhbmRsZSB0aGUgTlNS IHByb2JlIGZ1bmN0aW9uIGluIGEgbW9yZSBnZW5lcmljIHdheSB0byBzdXBwb3J0IG90aGVyCj4g PiB0eXBlIG9mIGludGVycnVwdHMuCj4gPiAKPiA+IEVhY2ggaW50ZXJydXB0IGRvbWFpbiBpcyBh IHRyZWUgZG9tYWluIHRvIGF2b2lkIGFsbG9jYXRpb24gdGhlIDIwNwo+ID4gZW50cmllcyBlYWNo IHRpbWUuIEluc3RlYWQgYW4gSUNVLXdpZGUgYml0bWFwIGlzIHVzZWQgdG8gZm9sbG93IElDVQo+ ID4gc2xvdCBhbGxvY2F0aW9ucy4KPiA+IAo+ID4gU2lnbmVkLW9mZi1ieTogTWlxdWVsIFJheW5h bCA8bWlxdWVsLnJheW5hbEBib290bGluLmNvbT4KPiA+IC0tLQo+ID4gIGRyaXZlcnMvaXJxY2hp cC9pcnEtbXZlYnUtaWN1LmMgfCAxNzMgKysrKysrKysrKysrKysrKysrKysrKysrKy0tLS0tLS0K PiA+ICAxIGZpbGUgY2hhbmdlZCwgMTM5IGluc2VydGlvbnMoKyksIDM0IGRlbGV0aW9ucygtKQo+ ID4gCj4gPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9pcnFjaGlwL2lycS1tdmVidS1pY3UuYyBiL2Ry aXZlcnMvaXJxY2hpcC9pcnEtbXZlYnUtaWN1LmMKPiA+IGluZGV4IGM3OWQyY2I3ODdhMC4uMjFl N2M1ODMwZmNjIDEwMDY0NAo+ID4gLS0tIGEvZHJpdmVycy9pcnFjaGlwL2lycS1tdmVidS1pY3Uu Ywo+ID4gKysrIGIvZHJpdmVycy9pcnFjaGlwL2lycS1tdmVidS1pY3UuYwo+ID4gQEAgLTI3LDYg KzI3LDEwIEBACj4gPiAgI2RlZmluZSBJQ1VfU0VUU1BJX05TUl9BSAkweDE0Cj4gPiAgI2RlZmlu ZSBJQ1VfQ0xSU1BJX05TUl9BTAkweDE4Cj4gPiAgI2RlZmluZSBJQ1VfQ0xSU1BJX05TUl9BSAkw eDFjCj4gPiArI2RlZmluZSBJQ1VfU0VUX1NFSV9BTAkJMHg1MAo+ID4gKyNkZWZpbmUgSUNVX1NF VF9TRUlfQUgJCTB4NTQKPiA+ICsjZGVmaW5lIElDVV9DTFJfU0VJX0FMCQkweDU4Cj4gPiArI2Rl ZmluZSBJQ1VfQ0xSX1NFSV9BSAkJMHg1Qwo+ID4gICNkZWZpbmUgSUNVX0lOVF9DRkcoeCkgICAg ICAgICAgKDB4MTAwICsgNCAqICh4KSkKPiA+ICAjZGVmaW5lICAgSUNVX0lOVF9FTkFCTEUJQklU KDI0KQo+ID4gICNkZWZpbmUgICBJQ1VfSVNfRURHRQkJQklUKDI4KQo+ID4gQEAgLTM3LDExICs0 MSwyNyBAQAo+ID4gICNkZWZpbmUgSUNVX1NBVEEwX0lDVV9JRAkxMDkKPiA+ICAjZGVmaW5lIElD VV9TQVRBMV9JQ1VfSUQJMTA3Cj4gPiAgCj4gPiArc3RydWN0IG12ZWJ1X2ljdV9zdWJzZXRfZGF0 YSB7Cj4gPiArCXVuc2lnbmVkIGludCBpY3VfZ3JvdXA7Cj4gPiArCXVuc2lnbmVkIGludCBvZmZz ZXRfc2V0X2FoOwo+ID4gKwl1bnNpZ25lZCBpbnQgb2Zmc2V0X3NldF9hbDsKPiA+ICsJdW5zaWdu ZWQgaW50IG9mZnNldF9jbHJfYWg7Cj4gPiArCXVuc2lnbmVkIGludCBvZmZzZXRfY2xyX2FsOwo+ ID4gK307Cj4gPiArCj4gPiAgc3RydWN0IG12ZWJ1X2ljdSB7Cj4gPiAtCXN0cnVjdCBpcnFfY2hp cCBpcnFfY2hpcDsKPiA+ICAJdm9pZCBfX2lvbWVtICpiYXNlOwo+ID4gIAlzdHJ1Y3QgZGV2aWNl ICpkZXY7Cj4gPiArCj4gPiArCS8qIExvY2sgb24gaW50ZXJydXB0IGFsbG9jYXRpb25zL3JlbGVh c2VzICovCj4gPiArCXN0cnVjdCBtdXRleCBtc2lfbG9jazsKPiA+ICsJREVDTEFSRV9CSVRNQVAo bXNpX2JpdG1hcCwgSUNVX01BWF9JUlFTKTsKPiA+ICt9Owo+ID4gKwo+ID4gK3N0cnVjdCBtdmVi dV9pY3VfbXNpX2RhdGEgewo+ID4gKwlzdHJ1Y3QgbXZlYnVfaWN1ICppY3U7Cj4gPiAgCWF0b21p Y190IGluaXRpYWxpemVkOwo+ID4gKwljb25zdCBzdHJ1Y3QgbXZlYnVfaWN1X3N1YnNldF9kYXRh ICpzdWJzZXRfZGF0YTsKPiA+ICB9Owo+ID4gIAo+ID4gIHN0cnVjdCBtdmVidV9pY3VfaXJxX2Rh dGEgewo+ID4gQEAgLTUyLDI4ICs3MiwzOCBAQCBzdHJ1Y3QgbXZlYnVfaWN1X2lycV9kYXRhIHsK PiA+ICAKPiA+ICBERUZJTkVfU1RBVElDX0tFWV9GQUxTRShsZWdhY3lfYmluZGluZ3MpOwo+ID4g IAo+ID4gLXN0YXRpYyB2b2lkIG12ZWJ1X2ljdV9pbml0KHN0cnVjdCBtdmVidV9pY3UgKmljdSwg c3RydWN0IG1zaV9tc2cgKm1zZykKPiA+ICtzdGF0aWMgdm9pZCBtdmVidV9pY3VfaW5pdChzdHJ1 Y3QgbXZlYnVfaWN1ICppY3UsCj4gPiArCQkJICAgc3RydWN0IG12ZWJ1X2ljdV9tc2lfZGF0YSAq bXNpX2RhdGEsCj4gPiArCQkJICAgc3RydWN0IG1zaV9tc2cgKm1zZykKPiA+ICB7Cj4gPiAtCWlm IChhdG9taWNfY21weGNoZygmaWN1LT5pbml0aWFsaXplZCwgZmFsc2UsIHRydWUpKQo+ID4gKwlj b25zdCBzdHJ1Y3QgbXZlYnVfaWN1X3N1YnNldF9kYXRhICpzdWJzZXQgPSBtc2lfZGF0YS0+c3Vi c2V0X2RhdGE7Cj4gPiArCj4gPiArCWlmIChhdG9taWNfY21weGNoZygmbXNpX2RhdGEtPmluaXRp YWxpemVkLCBmYWxzZSwgdHJ1ZSkpCj4gPiArCQlyZXR1cm47Cj4gPiArCj4gPiArCS8qIFNldCAn U0VUJyBJQ1UgU1BJIG1lc3NhZ2UgYWRkcmVzcyBpbiBBUCAqLwo+ID4gKwl3cml0ZWxfcmVsYXhl ZChtc2dbMF0uYWRkcmVzc19oaSwgaWN1LT5iYXNlICsgc3Vic2V0LT5vZmZzZXRfc2V0X2FoKTsK PiA+ICsJd3JpdGVsX3JlbGF4ZWQobXNnWzBdLmFkZHJlc3NfbG8sIGljdS0+YmFzZSArIHN1YnNl dC0+b2Zmc2V0X3NldF9hbCk7Cj4gPiArCj4gPiArCWlmIChzdWJzZXQtPmljdV9ncm91cCAhPSBJ Q1VfR1JQX05TUikKPiA+ICAJCXJldHVybjsKPiA+ICAKPiA+IC0JLyogU2V0IENsZWFyL1NldCBJ Q1UgU1BJIG1lc3NhZ2UgYWRkcmVzcyBpbiBBUCAqLwo+ID4gLQl3cml0ZWxfcmVsYXhlZChtc2db MF0uYWRkcmVzc19oaSwgaWN1LT5iYXNlICsgSUNVX1NFVFNQSV9OU1JfQUgpOwo+ID4gLQl3cml0 ZWxfcmVsYXhlZChtc2dbMF0uYWRkcmVzc19sbywgaWN1LT5iYXNlICsgSUNVX1NFVFNQSV9OU1Jf QUwpOwo+ID4gLQl3cml0ZWxfcmVsYXhlZChtc2dbMV0uYWRkcmVzc19oaSwgaWN1LT5iYXNlICsg SUNVX0NMUlNQSV9OU1JfQUgpOwo+ID4gLQl3cml0ZWxfcmVsYXhlZChtc2dbMV0uYWRkcmVzc19s bywgaWN1LT5iYXNlICsgSUNVX0NMUlNQSV9OU1JfQUwpOwo+ID4gKwkvKiBTZXQgJ0NMRUFSJyBJ Q1UgU1BJIG1lc3NhZ2UgYWRkcmVzcyBpbiBBUCAobGV2ZWwtTVNJIG9ubHkpICovCj4gPiArCXdy aXRlbF9yZWxheGVkKG1zZ1sxXS5hZGRyZXNzX2hpLCBpY3UtPmJhc2UgKyBzdWJzZXQtPm9mZnNl dF9jbHJfYWgpOwo+ID4gKwl3cml0ZWxfcmVsYXhlZChtc2dbMV0uYWRkcmVzc19sbywgaWN1LT5i YXNlICsgc3Vic2V0LT5vZmZzZXRfY2xyX2FsKTsKPiA+ICB9Cj4gPiAgCj4gPiAgc3RhdGljIHZv aWQgbXZlYnVfaWN1X3dyaXRlX21zZyhzdHJ1Y3QgbXNpX2Rlc2MgKmRlc2MsIHN0cnVjdCBtc2lf bXNnICptc2cpCj4gPiAgewo+ID4gIAlzdHJ1Y3QgaXJxX2RhdGEgKmQgPSBpcnFfZ2V0X2lycV9k YXRhKGRlc2MtPmlycSk7Cj4gPiArCXN0cnVjdCBtdmVidV9pY3VfbXNpX2RhdGEgKm1zaV9kYXRh ID0gcGxhdGZvcm1fbXNpX2dldF9ob3N0X2RhdGEoZC0+ZG9tYWluKTsKPiA+ICAJc3RydWN0IG12 ZWJ1X2ljdV9pcnFfZGF0YSAqaWN1X2lycWQgPSBkLT5jaGlwX2RhdGE7Cj4gPiAgCXN0cnVjdCBt dmVidV9pY3UgKmljdSA9IGljdV9pcnFkLT5pY3U7Cj4gPiAgCXVuc2lnbmVkIGludCBpY3VfaW50 Owo+ID4gIAo+ID4gIAlpZiAobXNnLT5hZGRyZXNzX2xvIHx8IG1zZy0+YWRkcmVzc19oaSkgewo+ ID4gLQkJLyogT25lIG9mZiBpbml0aWFsaXphdGlvbiAqLwo+ID4gLQkJbXZlYnVfaWN1X2luaXQo aWN1LCBtc2cpOwo+ID4gKwkJLyogT25lIG9mZiBpbml0aWFsaXphdGlvbiBwZXIgZG9tYWluICov Cj4gPiArCQltdmVidV9pY3VfaW5pdChpY3UsIG1zaV9kYXRhLCBtc2cpOwo+ID4gIAkJLyogQ29u ZmlndXJlIHRoZSBJQ1Ugd2l0aCBpcnEgbnVtYmVyICYgdHlwZSAqLwo+ID4gIAkJaWN1X2ludCA9 IG1zZy0+ZGF0YSB8IElDVV9JTlRfRU5BQkxFOwo+ID4gIAkJaWYgKGljdV9pcnFkLT50eXBlICYg SVJRX1RZUEVfRURHRV9SSVNJTkcpCj4gPiBAQCAtMTAzLDEwICsxMzMsMjkgQEAgc3RhdGljIHZv aWQgbXZlYnVfaWN1X3dyaXRlX21zZyhzdHJ1Y3QgbXNpX2Rlc2MgKmRlc2MsIHN0cnVjdCBtc2lf bXNnICptc2cpCj4gPiAgCX0KPiA+ICB9Cj4gPiAgCj4gPiArc3RhdGljIHN0cnVjdCBpcnFfY2hp cCBtdmVidV9pY3VfbnNyX2NoaXAgPSB7Cj4gPiArCS5uYW1lCQkJPSAiSUNVLU5TUiIsCj4gPiAr CS5pcnFfbWFzawkJPSBpcnFfY2hpcF9tYXNrX3BhcmVudCwKPiA+ICsJLmlycV91bm1hc2sJCT0g aXJxX2NoaXBfdW5tYXNrX3BhcmVudCwKPiA+ICsJLmlycV9lb2kJCT0gaXJxX2NoaXBfZW9pX3Bh cmVudCwKPiA+ICsJLmlycV9zZXRfdHlwZQkJPSBpcnFfY2hpcF9zZXRfdHlwZV9wYXJlbnQsCj4g PiArCS5pcnFfc2V0X2FmZmluaXR5CT0gaXJxX2NoaXBfc2V0X2FmZmluaXR5X3BhcmVudCwKPiA+ ICt9Owo+ID4gKwo+ID4gK3N0YXRpYyBzdHJ1Y3QgaXJxX2NoaXAgbXZlYnVfaWN1X3NlaV9jaGlw ID0gewo+ID4gKwkubmFtZQkJCT0gIklDVS1TRUkiLAo+ID4gKwkuaXJxX2FjawkJPSBpcnFfY2hp cF9hY2tfcGFyZW50LAo+ID4gKwkuaXJxX21hc2sJCT0gaXJxX2NoaXBfbWFza19wYXJlbnQsCj4g PiArCS5pcnFfdW5tYXNrCQk9IGlycV9jaGlwX3VubWFza19wYXJlbnQsCj4gPiArCS5pcnFfc2V0 X3R5cGUJCT0gaXJxX2NoaXBfc2V0X3R5cGVfcGFyZW50LAo+ID4gKwkuaXJxX3NldF9hZmZpbml0 eQk9IGlycV9jaGlwX3NldF9hZmZpbml0eV9wYXJlbnQsCj4gPiArfTsKPiA+ICsKPiA+ICBzdGF0 aWMgaW50Cj4gPiAgbXZlYnVfaWN1X2lycV9kb21haW5fdHJhbnNsYXRlKHN0cnVjdCBpcnFfZG9t YWluICpkLCBzdHJ1Y3QgaXJxX2Z3c3BlYyAqZndzcGVjLAo+ID4gIAkJCSAgICAgICB1bnNpZ25l ZCBsb25nICpod2lycSwgdW5zaWduZWQgaW50ICp0eXBlKQo+ID4gIHsKPiA+ICsJc3RydWN0IG12 ZWJ1X2ljdV9tc2lfZGF0YSAqbXNpX2RhdGEgPSBwbGF0Zm9ybV9tc2lfZ2V0X2hvc3RfZGF0YShk KTsKPiA+ICAJc3RydWN0IG12ZWJ1X2ljdSAqaWN1ID0gcGxhdGZvcm1fbXNpX2dldF9ob3N0X2Rh dGEoZCk7Cj4gPiAgCXVuc2lnbmVkIGludCBwYXJhbV9jb3VudCA9IHN0YXRpY19icmFuY2hfdW5s aWtlbHkoJmxlZ2FjeV9iaW5kaW5ncykgPyAzIDogMjsKPiA+ICAKPiA+IEBAIC0xMjgsNiArMTc3 LDE0IEBAIG12ZWJ1X2ljdV9pcnFfZG9tYWluX3RyYW5zbGF0ZShzdHJ1Y3QgaXJxX2RvbWFpbiAq ZCwgc3RydWN0IGlycV9md3NwZWMgKmZ3c3BlYywKPiA+ICAJfSBlbHNlIHsKPiA+ICAJCSpod2ly cSA9IGZ3c3BlYy0+cGFyYW1bMF07Cj4gPiAgCQkqdHlwZSA9IGZ3c3BlYy0+cGFyYW1bMV0gJiBJ UlFfVFlQRV9TRU5TRV9NQVNLOwo+ID4gKwo+ID4gKwkJLyoKPiA+ICsJCSAqIFRoZSBJQ1UgcmVj ZWl2ZXMgbGV2ZWwgaW50ZXJydXB0cy4gV2hpbGUgdGhlIE5TUiBhcmUgYWxzbwo+ID4gKwkJICog bGV2ZWwgaW50ZXJydXB0cywgU0VJIGFyZSBlZGdlIGludGVycnVwdHMuIEZvcmNlIHRoZSB0eXBl Cj4gPiArCQkgKiBoZXJlIGluIHRoaXMgY2FzZS4KPiA+ICsJCSAqLwo+ID4gKwkJaWYgKG1zaV9k YXRhLT5zdWJzZXRfZGF0YS0+aWN1X2dyb3VwID09IElDVV9HUlBfU0VJKQo+ID4gKwkJCSp0eXBl ID0gSVJRX1RZUEVfRURHRV9SSVNJTkc7ICAKPiAKPiBQbGVhc2UgYWRkIGEgY29tbWVudCBpbmRp Y2F0aW5nIHRoYXQgdGhpcyBtYWtlcyB0aGUgaW50ZXJydXB0IGhhbmRsaW5nCj4gdW5yZWxpYWJs ZS4gSSByZWFsbHkgZG9uJ3Qgd2FudCBhbnlvbmUgdG8gdGhpbmsgdGhhdCB0aGlzIGtpbmQgb2Yg aGFjawo+IGlzIHRvIGJlIHJlbGllZCB1cG9uIChpbnRlcnJ1cHQgZmlyZXMsIGRyaXZlciBpZ25v cmVzIHRoZSBpbnRlcnJ1cHQKPiBhbmQgbGVnaXRpbWF0ZWx5IGV4cGVjdHMgaXQgdG8gZmlyZSBh Z2FpbiwgaW50ZXJydXB0cyBkb2Vzbid0IGZpcmUsCj4gZGV2aWNlIGlzIGRlYWQpLgoKRG9uZS4g QWRkZWQgdGhlIG1lbnRpb246CgogICAgIk5vdGUgdGhhdCB0aGlzIG1ha2VzIHRoZSBpbnRlcnJ1 cHQgaGFuZGxpbmcgdW5yZWxpYWJsZS4iCgo+IAo+ID4gIAl9Cj4gPiAgCj4gPiAgCWlmICgqaHdp cnEgPj0gSUNVX01BWF9JUlFTKSB7Cj4gPiBAQCAtMTM4LDYgKzE5NSwyNSBAQCBtdmVidV9pY3Vf aXJxX2RvbWFpbl90cmFuc2xhdGUoc3RydWN0IGlycV9kb21haW4gKmQsIHN0cnVjdCBpcnFfZndz cGVjICpmd3NwZWMsCj4gPiAgCXJldHVybiAwOwo+ID4gIH0KPiA+ICAKPiA+ICtzdGF0aWMgaW50 IG12ZWJ1X2ljdV9tc2lfYml0bWFwX3JlZ2lvbl9hbGxvYyhzdHJ1Y3QgbXZlYnVfaWN1ICppY3Us IGludCBod2lycSkKPiA+ICt7Cj4gPiArCWludCByZXQ7Cj4gPiArCj4gPiArCW11dGV4X2xvY2so JmljdS0+bXNpX2xvY2spOwo+ID4gKwlyZXQgPSB0ZXN0X2FuZF9zZXRfYml0KGh3aXJxLCBpY3Ut Pm1zaV9iaXRtYXApOwo+ID4gKwltdXRleF91bmxvY2soJmljdS0+bXNpX2xvY2spOyAgCj4gCj4g dGVzdF9hbmRfc2V0X2JpdCBpcyBhdG9taWMuIFdoeSBkbyB3ZSBoYXZlIGEgbXV0ZXggdG8gZ3Vh cmQgaXQ/CgpNdXRleGVzIHJlbW92ZWQsIHRoYXQncyByaWdodCB3ZSBkb24ndCBuZWVkIHRoZW0g YW55bW9yZSBzaW5jZSB3ZQpwYXNzZWQgdG8gdGVzdF9hbmRfc2V0X2JpdCgpLgoKPiBNb3JlIGlt cG9ydGFudGx5LCB3aGF0IGlzIGl0IHVzZWQgZm9yPyBZb3Ugb25seSBzZWVtIHRvIHVzZSBpdCBh cyBzb21lCj4gcGFyYW5vaWQgY2hlY2sgdG8gdmFsaWRhdGUgdGhlIERULCB3aGljaCBtYWtlcyBu byBzZW5zZSB0byBtZS4KCkknbSBub3Qgc3VyZSBpZiB0aGlzIHRlc3QgaXMgcmVhbGx5IHBhcmFu b2lkIGFzLCBpbiB0aGVvcnksIHdlIG1pZ2h0CmhhdmUgbW9yZSBpbnRlcnJ1cHRzIHRoYW4gYXZh aWxhYmxlIHNsb3RzIGluIHRoZSBJQ1UgYW5kIEkgZmVlbCBnb29kCndhcm5pbmcgdGhlIHVzZXIg aWYgYW4gSUNVIHNsb3QgaXMgcmUtdXNlZC4gQW55d2F5LCBpZiB5b3UgcHJlZmVyIG5vdAp0byBj aGVjayB0aGF0LCBJIHdpbGwgc2ltcGx5IGdldCByaWQgb2YgdGhlIHdob2xlIGJpdG1hcCB3aGlj aCB0aGVuCm1ha2VzIG5vIG1vcmUgc2Vuc2UuCgpUaGFua3MsCk1pcXXDqGwKCl9fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCmxpbnV4LWFybS1rZXJuZWwgbWFp bGluZyBsaXN0CmxpbnV4LWFybS1rZXJuZWxAbGlzdHMuaW5mcmFkZWFkLm9yZwpodHRwOi8vbGlz dHMuaW5mcmFkZWFkLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2xpbnV4LWFybS1rZXJuZWwK