From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [v5,2/7] dmaengine: xilinx_dma: in axidma slave_sg and dma_cyclic mode align split descriptors From: Vinod Koul Message-Id: <20181002145820.GH19792@vkoul-mobl> Date: Tue, 2 Oct 2018 20:28:20 +0530 To: Andrea Merello Cc: dan.j.williams@intel.com, michal.simek@xilinx.com, appana.durga.rao@xilinx.com, dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel , Rob Herring , Mark Rutland , devicetree , Radhey Shyam Pandey List-ID: T24gMjgtMDktMTgsIDA5OjExLCBBbmRyZWEgTWVyZWxsbyB3cm90ZToKPiBPbiBUdWUsIFNlcCAx OCwgMjAxOCBhdCA2OjIxIFBNIFZpbm9kIDx2a291bEBrZXJuZWwub3JnPiB3cm90ZToKCj4gPiA+ IEBAIC0xODA0LDcgKzE4MTcsNyBAQCBzdGF0aWMgc3RydWN0IGRtYV9hc3luY190eF9kZXNjcmlw dG9yICp4aWxpbnhfZG1hX3ByZXBfc2xhdmVfc2coCj4gPiA+ICAgICAgICAgICAgICAgICAgICAg ICAgKiBDYWxjdWxhdGUgdGhlIG1heGltdW0gbnVtYmVyIG9mIGJ5dGVzIHRvIHRyYW5zZmVyLAo+ ID4gPiAgICAgICAgICAgICAgICAgICAgICAgICogbWFraW5nIHN1cmUgaXQgaXMgbGVzcyB0aGFu IHRoZSBodyBsaW1pdAo+ID4gPiAgICAgICAgICAgICAgICAgICAgICAgICovCj4gPiA+IC0gICAg ICAgICAgICAgICAgICAgICBjb3B5ID0geGlsaW54X2RtYV9jYWxjX2NvcHlzaXplKHNnX2RtYV9s ZW4oc2cpLAo+ID4gPiArICAgICAgICAgICAgICAgICAgICAgY29weSA9IHhpbGlueF9kbWFfY2Fs Y19jb3B5c2l6ZShjaGFuLCBzZ19kbWFfbGVuKHNnKSwKPiA+Cj4gPiB3aHkgbm90IGtlZXAgY2hh biBpbiBwYXRjaCAxIGFuZCBhZGQgb25seSBoYW5kbGluZyBpbiBwYXRjaCAyLCBzZWVtcwo+ID4g bGVzcyBjaHVybiB0byBtZS4uCj4gCj4gSW5kZWVkIHRoaXMgd2FzIHNvbWV0aGluZyBJIHdhcyB1 bnN1cmUgYWJvdXQuLiBJIGVuZGVkIHVwIGluIGZlZWxpbmcKPiBiZXR0ZXIgbm90IHRvIGFkZCBp bnRyb2R1Y2UgYSBmdW5jdGlvbiB0aGF0IHRha2VzIGFuIHVudXNlZCAoeWV0KQo+IGFyZ3VtZW50 LCBidXQgSSBjYW4gY2hhbmdlIHRoaXMgb2YgY291cnNlIDopCgpJTU8gSXQgaXMgZmluZSB0byBh ZGQgYSB1c2VyIGluIHN1YnNlcXVlbnQgcGF0Y2ggaW4gYSBzZXJpZXMuIE5vdCBmaW5lIHRvCmFk ZCBzb21ldGhpbmcgYW5kIG5vdCB1c2UgaW4gInRoYXQiIHNlcmllcyA6KQo= From mboxrd@z Thu Jan 1 00:00:00 1970 From: vkoul@kernel.org (Vinod) Date: Tue, 2 Oct 2018 20:28:20 +0530 Subject: [PATCH v5 2/7] dmaengine: xilinx_dma: in axidma slave_sg and dma_cyclic mode align split descriptors In-Reply-To: References: <20180907062502.8241-1-andrea.merello@gmail.com> <20180907062502.8241-2-andrea.merello@gmail.com> <20180918162105.GC2613@vkoul-mobl> Message-ID: <20181002145820.GH19792@vkoul-mobl> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 28-09-18, 09:11, Andrea Merello wrote: > On Tue, Sep 18, 2018 at 6:21 PM Vinod wrote: > > > @@ -1804,7 +1817,7 @@ static struct dma_async_tx_descriptor *xilinx_dma_prep_slave_sg( > > > * Calculate the maximum number of bytes to transfer, > > > * making sure it is less than the hw limit > > > */ > > > - copy = xilinx_dma_calc_copysize(sg_dma_len(sg), > > > + copy = xilinx_dma_calc_copysize(chan, sg_dma_len(sg), > > > > why not keep chan in patch 1 and add only handling in patch 2, seems > > less churn to me.. > > Indeed this was something I was unsure about.. I ended up in feeling > better not to add introduce a function that takes an unused (yet) > argument, but I can change this of course :) IMO It is fine to add a user in subsequent patch in a series. Not fine to add something and not use in "that" series :) -- ~Vinod From mboxrd@z Thu Jan 1 00:00:00 1970 From: Vinod Subject: Re: [PATCH v5 2/7] dmaengine: xilinx_dma: in axidma slave_sg and dma_cyclic mode align split descriptors Date: Tue, 2 Oct 2018 20:28:20 +0530 Message-ID: <20181002145820.GH19792@vkoul-mobl> References: <20180907062502.8241-1-andrea.merello@gmail.com> <20180907062502.8241-2-andrea.merello@gmail.com> <20180918162105.GC2613@vkoul-mobl> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: Sender: linux-kernel-owner@vger.kernel.org To: Andrea Merello Cc: dan.j.williams@intel.com, michal.simek@xilinx.com, appana.durga.rao@xilinx.com, dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel , Rob Herring , Mark Rutland , devicetree , Radhey Shyam Pandey List-Id: devicetree@vger.kernel.org On 28-09-18, 09:11, Andrea Merello wrote: > On Tue, Sep 18, 2018 at 6:21 PM Vinod wrote: > > > @@ -1804,7 +1817,7 @@ static struct dma_async_tx_descriptor *xilinx_dma_prep_slave_sg( > > > * Calculate the maximum number of bytes to transfer, > > > * making sure it is less than the hw limit > > > */ > > > - copy = xilinx_dma_calc_copysize(sg_dma_len(sg), > > > + copy = xilinx_dma_calc_copysize(chan, sg_dma_len(sg), > > > > why not keep chan in patch 1 and add only handling in patch 2, seems > > less churn to me.. > > Indeed this was something I was unsure about.. I ended up in feeling > better not to add introduce a function that takes an unused (yet) > argument, but I can change this of course :) IMO It is fine to add a user in subsequent patch in a series. Not fine to add something and not use in "that" series :) -- ~Vinod