From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [v3,3/7] dt-bindings: stm32-mdma: Add DMA/MDMA chaining support bindings From: Vinod Koul Message-Id: <20181007145930.GA2372@vkoul-mobl> Date: Sun, 7 Oct 2018 20:29:30 +0530 To: Pierre-Yves MORDRET Cc: Rob Herring , Mark Rutland , Alexandre Torgue , Maxime Coquelin , Dan Williams , devicetree@vger.kernel.org, dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org List-ID: T24gMjgtMDktMTgsIDE1OjAxLCBQaWVycmUtWXZlcyBNT1JEUkVUIHdyb3RlOgo+IEZyb206IE0n Ym91bWJhIENlZHJpYyBNYWRpYW5nYSA8Y2VkcmljLm1hZGlhbmdhQGdtYWlsLmNvbT4KPiAKPiBU aGlzIHBhdGNoIGFkZHMgdGhlIGRlc2NyaXB0aW9uIG9mIHRoZSAyIHByb3BlcnRpZXMgbmVlZGVk IHRvIHN1cHBvcnQgTTJNCj4gdHJhbnNmZXIgdHJpZ2dlcmVkIGJ5IFNUTTMyIERNQSB3aGVuIGhp cyB0cmFuc2ZlciBpcyBjb21wbGV0ZS4KPiAKPiBTaWduZWQtb2ZmLWJ5OiBQaWVycmUtWXZlcyBN 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PiArICAgdHJhbnNmZXIgd2l0aCBIVyB0cmlnZ2VyICgxKSBvciBub3QgKDApLiBUaGlzIGJpdGZp ZWxkIHNob3VsZCBiZSBvbmx5Cj4gKyAgIGVuYWJsZWQgZm9yIE0yTSB0cmFuc2ZlciB0cmlnZ2Vy ZWQgYnkgU1RNMzIgRE1BIGNsaWVudC4gVGhlIG1lbW9yeSBkZXZpY2VzCj4gKyAgIGludm9sdmVk IGluIHRoaXMga2luZCBvZiB0cmFuc2ZlciBhcmUgU1JBTSBhbmQgRERSLgo+ICAKPiAgRXhhbXBs ZToKPiAgCj4gLS0gCj4gMi43LjQK From mboxrd@z Thu Jan 1 00:00:00 1970 From: vkoul@kernel.org (Vinod) Date: Sun, 7 Oct 2018 20:29:30 +0530 Subject: [PATCH v3 3/7] dt-bindings: stm32-mdma: Add DMA/MDMA chaining support bindings In-Reply-To: <1538139715-24406-4-git-send-email-pierre-yves.mordret@st.com> References: <1538139715-24406-1-git-send-email-pierre-yves.mordret@st.com> <1538139715-24406-4-git-send-email-pierre-yves.mordret@st.com> Message-ID: <20181007145930.GA2372@vkoul-mobl> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 28-09-18, 15:01, Pierre-Yves MORDRET wrote: > From: M'boumba Cedric Madianga > > This patch adds the description of the 2 properties needed to support M2M > transfer triggered by STM32 DMA when his transfer is complete. > > Signed-off-by: Pierre-Yves MORDRET > --- > Version history: > v3: > v2: > * rework content > v1: > * Initial > --- > --- > Documentation/devicetree/bindings/dma/stm32-mdma.txt | 12 ++++++++---- > 1 file changed, 8 insertions(+), 4 deletions(-) > > diff --git a/Documentation/devicetree/bindings/dma/stm32-mdma.txt b/Documentation/devicetree/bindings/dma/stm32-mdma.txt > index d18772d..27c2812 100644 > --- a/Documentation/devicetree/bindings/dma/stm32-mdma.txt > +++ b/Documentation/devicetree/bindings/dma/stm32-mdma.txt > @@ -10,7 +10,7 @@ Required properties: > - interrupts: Should contain the MDMA interrupt. > - clocks: Should contain the input clock of the DMA instance. > - resets: Reference to a reset controller asserting the DMA controller. > -- #dma-cells : Must be <5>. See DMA client paragraph for more details. > +- #dma-cells : Must be <6>. See DMA client paragraph for more details. can you update the example for 6 cells? Also what happens to dts using 5 cells.. > > Optional properties: > - dma-channels: Number of DMA channels supported by the controller. > @@ -26,7 +26,7 @@ Example: > interrupts = <122>; > clocks = <&timer_clk>; > resets = <&rcc 992>; > - #dma-cells = <5>; > + #dma-cells = <6>; > dma-channels = <16>; > dma-requests = <32>; > st,ahb-addr-masks = <0x20000000>, <0x00000000>; > @@ -35,8 +35,8 @@ Example: > * DMA client > > DMA clients connected to the STM32 MDMA controller must use the format > -described in the dma.txt file, using a five-cell specifier for each channel: > -a phandle to the MDMA controller plus the following five integer cells: > +described in the dma.txt file, using a six-cell specifier for each channel: > +a phandle to the MDMA controller plus the following six integer cells: > > 1. The request line number > 2. The priority level > @@ -76,6 +76,10 @@ a phandle to the MDMA controller plus the following five integer cells: > if no HW ack signal is used by the MDMA client > 5. A 32bit mask specifying the value to be written to acknowledge the request > if no HW ack signal is used by the MDMA client > +6. A bitfield value specifying if the MDMA client wants to generate M2M > + transfer with HW trigger (1) or not (0). This bitfield should be only > + enabled for M2M transfer triggered by STM32 DMA client. The memory devices > + involved in this kind of transfer are SRAM and DDR. > > Example: > > -- > 2.7.4 -- ~Vinod From mboxrd@z Thu Jan 1 00:00:00 1970 From: Vinod Subject: Re: [PATCH v3 3/7] dt-bindings: stm32-mdma: Add DMA/MDMA chaining support bindings Date: Sun, 7 Oct 2018 20:29:30 +0530 Message-ID: <20181007145930.GA2372@vkoul-mobl> References: <1538139715-24406-1-git-send-email-pierre-yves.mordret@st.com> <1538139715-24406-4-git-send-email-pierre-yves.mordret@st.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: <1538139715-24406-4-git-send-email-pierre-yves.mordret@st.com> Sender: linux-kernel-owner@vger.kernel.org To: Pierre-Yves MORDRET Cc: Rob Herring , Mark Rutland , Alexandre Torgue , Maxime Coquelin , Dan Williams , devicetree@vger.kernel.org, dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org List-Id: devicetree@vger.kernel.org On 28-09-18, 15:01, Pierre-Yves MORDRET wrote: > From: M'boumba Cedric Madianga > > This patch adds the description of the 2 properties needed to support M2M > transfer triggered by STM32 DMA when his transfer is complete. > > Signed-off-by: Pierre-Yves MORDRET > --- > Version history: > v3: > v2: > * rework content > v1: > * Initial > --- > --- > Documentation/devicetree/bindings/dma/stm32-mdma.txt | 12 ++++++++---- > 1 file changed, 8 insertions(+), 4 deletions(-) > > diff --git a/Documentation/devicetree/bindings/dma/stm32-mdma.txt b/Documentation/devicetree/bindings/dma/stm32-mdma.txt > index d18772d..27c2812 100644 > --- a/Documentation/devicetree/bindings/dma/stm32-mdma.txt > +++ b/Documentation/devicetree/bindings/dma/stm32-mdma.txt > @@ -10,7 +10,7 @@ Required properties: > - interrupts: Should contain the MDMA interrupt. > - clocks: Should contain the input clock of the DMA instance. > - resets: Reference to a reset controller asserting the DMA controller. > -- #dma-cells : Must be <5>. See DMA client paragraph for more details. > +- #dma-cells : Must be <6>. See DMA client paragraph for more details. can you update the example for 6 cells? Also what happens to dts using 5 cells.. > > Optional properties: > - dma-channels: Number of DMA channels supported by the controller. > @@ -26,7 +26,7 @@ Example: > interrupts = <122>; > clocks = <&timer_clk>; > resets = <&rcc 992>; > - #dma-cells = <5>; > + #dma-cells = <6>; > dma-channels = <16>; > dma-requests = <32>; > st,ahb-addr-masks = <0x20000000>, <0x00000000>; > @@ -35,8 +35,8 @@ Example: > * DMA client > > DMA clients connected to the STM32 MDMA controller must use the format > -described in the dma.txt file, using a five-cell specifier for each channel: > -a phandle to the MDMA controller plus the following five integer cells: > +described in the dma.txt file, using a six-cell specifier for each channel: > +a phandle to the MDMA controller plus the following six integer cells: > > 1. The request line number > 2. The priority level > @@ -76,6 +76,10 @@ a phandle to the MDMA controller plus the following five integer cells: > if no HW ack signal is used by the MDMA client > 5. A 32bit mask specifying the value to be written to acknowledge the request > if no HW ack signal is used by the MDMA client > +6. A bitfield value specifying if the MDMA client wants to generate M2M > + transfer with HW trigger (1) or not (0). This bitfield should be only > + enabled for M2M transfer triggered by STM32 DMA client. The memory devices > + involved in this kind of transfer are SRAM and DDR. > > Example: > > -- > 2.7.4 -- ~Vinod