diff for duplicates of <20181008054510.GG3587@dragon> diff --git a/a/content_digest b/N1/content_digest index 2833fa7..8c72364 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -32,10 +32,7 @@ pankaj.bansal@nxp.com Ramneek Mehresh <ramneek.mehresh@nxp.com> Zhang Ying-22455 <ying.zhang22455@nxp.com> - Nipun Gupta <nipun.gupta@nxp.com> - Priyanka Jain <priyanka.jain@nxp.com> - Yogesh Gaur <yogeshnarayan.gaur@nxp.com> - " Sriram Dash <sriram.dash@nxp.com>\0" + " Nipun Gupta <nipun.gupta@nxp.com>Priyanka Jain <p>\0" "\00:1\0" "b\0" "On Thu, Oct 04, 2018 at 06:33:50AM +0530, Vabhav Sharma wrote:\n" @@ -802,4 +799,4 @@ "> 2.7.4\n" > -35bbcbb4d7bf73d2d714a65007c302d5f45502cdf05c11332866a9bd193c3362 +5165f60fec5c032cf3eac8abd759282f3d0910778c705072509a31d901a0a8da
diff --git a/a/content_digest b/N2/content_digest index 2833fa7..c0aa09d 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -4,38 +4,38 @@ "Subject\0Re: [PATCH v4 5/6] arm64: dts: add QorIQ LX2160A SoC support\0" "Date\0Mon, 8 Oct 2018 13:45:16 +0800\0" "To\0Vabhav Sharma <vabhav.sharma@nxp.com>\0" - "Cc\0sudeep.holla@arm.com" - oss@buserror.net - linux-kernel@vger.kernel.org - devicetree@vger.kernel.org - robh+dt@kernel.org - mark.rutland@arm.com - linuxppc-dev@lists.ozlabs.org - linux-arm-kernel@lists.infradead.org - mturquette@baylibre.com - sboyd@kernel.org - rjw@rjwysocki.net - viresh.kumar@linaro.org - linux-clk@vger.kernel.org - linux-pm@vger.kernel.org + "Cc\0mark.rutland@arm.com" + kstewart@linuxfoundation.org + Yogesh Gaur <yogeshnarayan.gaur@nxp.com> linux-kernel-owner@vger.kernel.org catalin.marinas@arm.com + mturquette@baylibre.com will.deacon@arm.com - gregkh@linuxfoundation.org - arnd@arndb.de - kstewart@linuxfoundation.org yamada.masahiro@socionext.com - leoyang.li@nxp.com + Sriram Dash <sriram.dash@nxp.com> + linux-clk@vger.kernel.org + pankaj.bansal@nxp.com + udit.kumar@nxp.com linux@armlinux.org.uk + Priyanka Jain <priyanka.jain@nxp.com> + viresh.kumar@linaro.org + devicetree@vger.kernel.org + arnd@arndb.de + linux-pm@vger.kernel.org + oss@buserror.net + robh+dt@kernel.org V.Sethi@nxp.com - udit.kumar@nxp.com - pankaj.bansal@nxp.com + Nipun Gupta <nipun.gupta@nxp.com> + linux-arm-kernel@lists.infradead.org Ramneek Mehresh <ramneek.mehresh@nxp.com> + sboyd@kernel.org + gregkh@linuxfoundation.org Zhang Ying-22455 <ying.zhang22455@nxp.com> - Nipun Gupta <nipun.gupta@nxp.com> - Priyanka Jain <priyanka.jain@nxp.com> - Yogesh Gaur <yogeshnarayan.gaur@nxp.com> - " Sriram Dash <sriram.dash@nxp.com>\0" + rjw@rjwysocki.net + linux-kernel@vger.kernel.org + leoyang.li@nxp.com + sudeep.holla@arm.com + " linuxppc-dev@lists.ozlabs.org\0" "\00:1\0" "b\0" "On Thu, Oct 04, 2018 at 06:33:50AM +0530, Vabhav Sharma wrote:\n" @@ -802,4 +802,4 @@ "> 2.7.4\n" > -35bbcbb4d7bf73d2d714a65007c302d5f45502cdf05c11332866a9bd193c3362 +b4f89e3a1aa5dff52ed7d57a782562c37153a6223f5360ae90d6368b25abc42f
diff --git a/a/1.txt b/N3/1.txt index 1ed93c5..5f197c9 100644 --- a/a/1.txt +++ b/N3/1.txt @@ -45,7 +45,7 @@ On Thu, Oct 04, 2018 at 06:33:50AM +0530, Vabhav Sharma wrote: > + #size-cells = <0>; > + > + // 8 clusters having 2 Cortex-A72 cores each -> + cpu@0 { +> + cpu at 0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + enable-method = "psci"; @@ -60,7 +60,7 @@ On Thu, Oct 04, 2018 at 06:33:50AM +0530, Vabhav Sharma wrote: > + next-level-cache = <&cluster0_l2>; > + }; > + -> + cpu@1 { +> + cpu at 1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + enable-method = "psci"; @@ -75,7 +75,7 @@ On Thu, Oct 04, 2018 at 06:33:50AM +0530, Vabhav Sharma wrote: > + next-level-cache = <&cluster0_l2>; > + }; > + -> + cpu@100 { +> + cpu at 100 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + enable-method = "psci"; @@ -90,7 +90,7 @@ On Thu, Oct 04, 2018 at 06:33:50AM +0530, Vabhav Sharma wrote: > + next-level-cache = <&cluster1_l2>; > + }; > + -> + cpu@101 { +> + cpu at 101 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + enable-method = "psci"; @@ -105,7 +105,7 @@ On Thu, Oct 04, 2018 at 06:33:50AM +0530, Vabhav Sharma wrote: > + next-level-cache = <&cluster1_l2>; > + }; > + -> + cpu@200 { +> + cpu at 200 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + enable-method = "psci"; @@ -120,7 +120,7 @@ On Thu, Oct 04, 2018 at 06:33:50AM +0530, Vabhav Sharma wrote: > + next-level-cache = <&cluster2_l2>; > + }; > + -> + cpu@201 { +> + cpu at 201 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + enable-method = "psci"; @@ -135,7 +135,7 @@ On Thu, Oct 04, 2018 at 06:33:50AM +0530, Vabhav Sharma wrote: > + next-level-cache = <&cluster2_l2>; > + }; > + -> + cpu@300 { +> + cpu at 300 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + enable-method = "psci"; @@ -150,7 +150,7 @@ On Thu, Oct 04, 2018 at 06:33:50AM +0530, Vabhav Sharma wrote: > + next-level-cache = <&cluster3_l2>; > + }; > + -> + cpu@301 { +> + cpu at 301 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + enable-method = "psci"; @@ -165,7 +165,7 @@ On Thu, Oct 04, 2018 at 06:33:50AM +0530, Vabhav Sharma wrote: > + next-level-cache = <&cluster3_l2>; > + }; > + -> + cpu@400 { +> + cpu at 400 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + enable-method = "psci"; @@ -180,7 +180,7 @@ On Thu, Oct 04, 2018 at 06:33:50AM +0530, Vabhav Sharma wrote: > + next-level-cache = <&cluster4_l2>; > + }; > + -> + cpu@401 { +> + cpu at 401 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + enable-method = "psci"; @@ -195,7 +195,7 @@ On Thu, Oct 04, 2018 at 06:33:50AM +0530, Vabhav Sharma wrote: > + next-level-cache = <&cluster4_l2>; > + }; > + -> + cpu@500 { +> + cpu at 500 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + enable-method = "psci"; @@ -210,7 +210,7 @@ On Thu, Oct 04, 2018 at 06:33:50AM +0530, Vabhav Sharma wrote: > + next-level-cache = <&cluster5_l2>; > + }; > + -> + cpu@501 { +> + cpu at 501 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + enable-method = "psci"; @@ -225,7 +225,7 @@ On Thu, Oct 04, 2018 at 06:33:50AM +0530, Vabhav Sharma wrote: > + next-level-cache = <&cluster5_l2>; > + }; > + -> + cpu@600 { +> + cpu at 600 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + enable-method = "psci"; @@ -240,7 +240,7 @@ On Thu, Oct 04, 2018 at 06:33:50AM +0530, Vabhav Sharma wrote: > + next-level-cache = <&cluster6_l2>; > + }; > + -> + cpu@601 { +> + cpu at 601 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + enable-method = "psci"; @@ -255,7 +255,7 @@ On Thu, Oct 04, 2018 at 06:33:50AM +0530, Vabhav Sharma wrote: > + next-level-cache = <&cluster6_l2>; > + }; > + -> + cpu@700 { +> + cpu at 700 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + enable-method = "psci"; @@ -270,7 +270,7 @@ On Thu, Oct 04, 2018 at 06:33:50AM +0530, Vabhav Sharma wrote: > + next-level-cache = <&cluster7_l2>; > + }; > + -> + cpu@701 { +> + cpu at 701 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + enable-method = "psci"; @@ -350,7 +350,7 @@ On Thu, Oct 04, 2018 at 06:33:50AM +0530, Vabhav Sharma wrote: > + }; > + }; > + -> + gic: interrupt-controller@6000000 { +> + gic: interrupt-controller at 6000000 { > + compatible = "arm,gic-v3"; > + reg = <0x0 0x06000000 0 0x10000>, // GIC Dist > + <0x0 0x06200000 0 0x200000>, // GICR (RD_base + @@ -365,7 +365,7 @@ On Thu, Oct 04, 2018 at 06:33:50AM +0530, Vabhav Sharma wrote: > + interrupt-controller; > + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; > + -> + its: gic-its@6020000 { +> + its: gic-its at 6020000 { > + compatible = "arm,gic-v3-its"; > + msi-controller; > + reg = <0x0 0x6020000 0 0x20000>; @@ -390,20 +390,20 @@ On Thu, Oct 04, 2018 at 06:33:50AM +0530, Vabhav Sharma wrote: > + method = "smc"; > + }; > + -> + memory@80000000 { +> + memory at 80000000 { > + // DRAM space - 1, size : 2 GB DRAM > + device_type = "memory"; > + reg = <0x00000000 0x80000000 0 0x80000000>; > + }; > + -> + ddr1: memory-controller@1080000 { +> + ddr1: memory-controller at 1080000 { > + compatible = "fsl,qoriq-memory-controller"; > + reg = <0x0 0x1080000 0x0 0x1000>; > + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; > + little-endian; > + }; > + -> + ddr2: memory-controller@1090000 { +> + ddr2: memory-controller at 1090000 { > + compatible = "fsl,qoriq-memory-controller"; > + reg = <0x0 0x1090000 0x0 0x1000>; > + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; @@ -426,7 +426,7 @@ Name the node a bit generic like clock-xxx. > + #size-cells = <2>; > + ranges; > + -> + clockgen: clocking@1300000 { +> + clockgen: clocking at 1300000 { clock-controller for node name. @@ -436,7 +436,7 @@ clock-controller for node name. > + clocks = <&sysclk>; > + }; > + -> + crypto: crypto@8000000 { +> + crypto: crypto at 8000000 { > + compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; > + fsl,sec-era = <10>; > + #address-cells = <1>; @@ -447,28 +447,28 @@ clock-controller for node name. > + dma-coherent; > + status = "disabled"; > + -> + sec_jr0: jr@10000 { +> + sec_jr0: jr at 10000 { > + compatible = "fsl,sec-v5.0-job-ring", > + "fsl,sec-v4.0-job-ring"; > + reg = <0x10000 0x10000>; > + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; > + }; > + -> + sec_jr1: jr@20000 { +> + sec_jr1: jr at 20000 { > + compatible = "fsl,sec-v5.0-job-ring", > + "fsl,sec-v4.0-job-ring"; > + reg = <0x20000 0x10000>; > + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; > + }; > + -> + sec_jr2: jr@30000 { +> + sec_jr2: jr at 30000 { > + compatible = "fsl,sec-v5.0-job-ring", > + "fsl,sec-v4.0-job-ring"; > + reg = <0x30000 0x10000>; > + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; > + }; > + -> + sec_jr3: jr@40000 { +> + sec_jr3: jr at 40000 { > + compatible = "fsl,sec-v5.0-job-ring", > + "fsl,sec-v4.0-job-ring"; > + reg = <0x40000 0x10000>; @@ -476,7 +476,7 @@ clock-controller for node name. > + }; > + }; > + -> + dcfg: dcfg@1e00000 { +> + dcfg: dcfg at 1e00000 { As per suggestion from devicetree specification, we can "syscon" as a more generic node name? @@ -486,7 +486,7 @@ a more generic node name? > + little-endian; > + }; > + -> + gpio0: gpio@2300000 { +> + gpio0: gpio at 2300000 { > + compatible = "fsl,qoriq-gpio"; > + reg = <0x0 0x2300000 0x0 0x10000>; > + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; @@ -497,7 +497,7 @@ a more generic node name? > + #interrupt-cells = <2>; > + }; > + -> + gpio1: gpio@2310000 { +> + gpio1: gpio at 2310000 { > + compatible = "fsl,qoriq-gpio"; > + reg = <0x0 0x2310000 0x0 0x10000>; > + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; @@ -508,7 +508,7 @@ a more generic node name? > + #interrupt-cells = <2>; > + }; > + -> + gpio2: gpio@2320000 { +> + gpio2: gpio at 2320000 { > + compatible = "fsl,qoriq-gpio"; > + reg = <0x0 0x2320000 0x0 0x10000>; > + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; @@ -519,7 +519,7 @@ a more generic node name? > + #interrupt-cells = <2>; > + }; > + -> + gpio3: gpio@2330000 { +> + gpio3: gpio at 2330000 { > + compatible = "fsl,qoriq-gpio"; > + reg = <0x0 0x2330000 0x0 0x10000>; > + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; @@ -530,7 +530,7 @@ a more generic node name? > + #interrupt-cells = <2>; > + }; > + -> + i2c0: i2c@2000000 { +> + i2c0: i2c at 2000000 { Sort the nodes under bus in order of unit-address. @@ -548,7 +548,7 @@ I cannot find this property in fsl,vf610-i2c bindings. > + status = "disabled"; > + }; > + -> + i2c1: i2c@2010000 { +> + i2c1: i2c at 2010000 { > + compatible = "fsl,vf610-i2c"; > + #address-cells = <1>; > + #size-cells = <0>; @@ -559,7 +559,7 @@ I cannot find this property in fsl,vf610-i2c bindings. > + status = "disabled"; > + }; > + -> + i2c2: i2c@2020000 { +> + i2c2: i2c at 2020000 { > + compatible = "fsl,vf610-i2c"; > + #address-cells = <1>; > + #size-cells = <0>; @@ -570,7 +570,7 @@ I cannot find this property in fsl,vf610-i2c bindings. > + status = "disabled"; > + }; > + -> + i2c3: i2c@2030000 { +> + i2c3: i2c at 2030000 { > + compatible = "fsl,vf610-i2c"; > + #address-cells = <1>; > + #size-cells = <0>; @@ -581,7 +581,7 @@ I cannot find this property in fsl,vf610-i2c bindings. > + status = "disabled"; > + }; > + -> + i2c4: i2c@2040000 { +> + i2c4: i2c at 2040000 { > + compatible = "fsl,vf610-i2c"; > + #address-cells = <1>; > + #size-cells = <0>; @@ -593,7 +593,7 @@ I cannot find this property in fsl,vf610-i2c bindings. > + status = "disabled"; > + }; > + -> + i2c5: i2c@2050000 { +> + i2c5: i2c at 2050000 { > + compatible = "fsl,vf610-i2c"; > + #address-cells = <1>; > + #size-cells = <0>; @@ -604,7 +604,7 @@ I cannot find this property in fsl,vf610-i2c bindings. > + status = "disabled"; > + }; > + -> + i2c6: i2c@2060000 { +> + i2c6: i2c at 2060000 { > + compatible = "fsl,vf610-i2c"; > + #address-cells = <1>; > + #size-cells = <0>; @@ -615,7 +615,7 @@ I cannot find this property in fsl,vf610-i2c bindings. > + status = "disabled"; > + }; > + -> + i2c7: i2c@2070000 { +> + i2c7: i2c at 2070000 { > + compatible = "fsl,vf610-i2c"; > + #address-cells = <1>; > + #size-cells = <0>; @@ -626,15 +626,15 @@ I cannot find this property in fsl,vf610-i2c bindings. > + status = "disabled"; > + }; > + -> + uart0: serial@21c0000 { +> + uart0: serial at 21c0000 { > + device_type = "serial"; Quote from devicetree specification: -The device_type property was used in IEEE 1275 to describe the device’s +The device_type property was used in IEEE 1275 to describe the device?s FCode programming model. Because DTSpec does not have FCode, new use of the property is deprecated, and it should be included only on cpu and -memory nodes for compatibility with IEEE 1275–derived devicetrees. +memory nodes for compatibility with IEEE 1275?derived devicetrees. > + compatible = "arm,sbsa-uart","arm,pl011"; > + reg = <0x0 0x21c0000 0x0 0x1000>; @@ -643,7 +643,7 @@ memory nodes for compatibility with IEEE 1275–derived devicetrees. > + status = "disabled"; > + }; > + -> + uart1: serial@21d0000 { +> + uart1: serial at 21d0000 { > + device_type = "serial"; > + compatible = "arm,sbsa-uart","arm,pl011"; > + reg = <0x0 0x21d0000 0x0 0x1000>; @@ -652,7 +652,7 @@ memory nodes for compatibility with IEEE 1275–derived devicetrees. > + status = "disabled"; > + }; > + -> + uart2: serial@21e0000 { +> + uart2: serial at 21e0000 { > + device_type = "serial"; > + compatible = "arm,sbsa-uart","arm,pl011"; > + reg = <0x0 0x21e0000 0x0 0x1000>; @@ -661,7 +661,7 @@ memory nodes for compatibility with IEEE 1275–derived devicetrees. > + status = "disabled"; > + }; > + -> + uart3: serial@21f0000 { +> + uart3: serial at 21f0000 { > + device_type = "serial"; > + compatible = "arm,sbsa-uart","arm,pl011"; > + reg = <0x0 0x21f0000 0x0 0x1000>; @@ -670,7 +670,7 @@ memory nodes for compatibility with IEEE 1275–derived devicetrees. > + status = "disabled"; > + }; > + -> + smmu: iommu@5000000 { +> + smmu: iommu at 5000000 { > + compatible = "arm,mmu-500"; > + reg = <0 0x5000000 0 0x800000>; > + #iommu-cells = <1>; @@ -724,7 +724,7 @@ Can we use defines for interrupt cells just like other device nodes? > + dma-coherent; > + }; > + -> + usb0: usb3@3100000 { +> + usb0: usb3 at 3100000 { usb for node name. @@ -739,7 +739,7 @@ Shawn > + status = "disabled"; > + }; > + -> + usb1: usb3@3110000 { +> + usb1: usb3 at 3110000 { > + compatible = "snps,dwc3"; > + reg = <0x0 0x3110000 0x0 0x10000>; > + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; @@ -749,7 +749,7 @@ Shawn > + status = "disabled"; > + }; > + -> + watchdog@23a0000 { +> + watchdog at 23a0000 { > + compatible = "arm,sbsa-gwdt"; > + reg = <0x0 0x23a0000 0 0x1000>, > + <0x0 0x2390000 0 0x1000>; diff --git a/a/content_digest b/N3/content_digest index 2833fa7..ec0962f 100644 --- a/a/content_digest +++ b/N3/content_digest @@ -1,41 +1,9 @@ "ref\01538615031-7507-1-git-send-email-vabhav.sharma@nxp.com\0" "ref\01538615031-7507-6-git-send-email-vabhav.sharma@nxp.com\0" - "From\0Shawn Guo <shawnguo@kernel.org>\0" - "Subject\0Re: [PATCH v4 5/6] arm64: dts: add QorIQ LX2160A SoC support\0" + "From\0shawnguo@kernel.org (Shawn Guo)\0" + "Subject\0[PATCH v4 5/6] arm64: dts: add QorIQ LX2160A SoC support\0" "Date\0Mon, 8 Oct 2018 13:45:16 +0800\0" - "To\0Vabhav Sharma <vabhav.sharma@nxp.com>\0" - "Cc\0sudeep.holla@arm.com" - oss@buserror.net - linux-kernel@vger.kernel.org - devicetree@vger.kernel.org - robh+dt@kernel.org - mark.rutland@arm.com - linuxppc-dev@lists.ozlabs.org - linux-arm-kernel@lists.infradead.org - mturquette@baylibre.com - sboyd@kernel.org - rjw@rjwysocki.net - viresh.kumar@linaro.org - linux-clk@vger.kernel.org - linux-pm@vger.kernel.org - linux-kernel-owner@vger.kernel.org - catalin.marinas@arm.com - will.deacon@arm.com - gregkh@linuxfoundation.org - arnd@arndb.de - kstewart@linuxfoundation.org - yamada.masahiro@socionext.com - leoyang.li@nxp.com - linux@armlinux.org.uk - V.Sethi@nxp.com - udit.kumar@nxp.com - pankaj.bansal@nxp.com - Ramneek Mehresh <ramneek.mehresh@nxp.com> - Zhang Ying-22455 <ying.zhang22455@nxp.com> - Nipun Gupta <nipun.gupta@nxp.com> - Priyanka Jain <priyanka.jain@nxp.com> - Yogesh Gaur <yogeshnarayan.gaur@nxp.com> - " Sriram Dash <sriram.dash@nxp.com>\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "On Thu, Oct 04, 2018 at 06:33:50AM +0530, Vabhav Sharma wrote:\n" @@ -85,7 +53,7 @@ "> +\t\t#size-cells = <0>;\n" "> +\n" "> +\t\t// 8 clusters having 2 Cortex-A72 cores each\n" - "> +\t\tcpu@0 {\n" + "> +\t\tcpu at 0 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\";\n" "> +\t\t\tenable-method = \"psci\";\n" @@ -100,7 +68,7 @@ "> +\t\t\tnext-level-cache = <&cluster0_l2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu@1 {\n" + "> +\t\tcpu at 1 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\";\n" "> +\t\t\tenable-method = \"psci\";\n" @@ -115,7 +83,7 @@ "> +\t\t\tnext-level-cache = <&cluster0_l2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu@100 {\n" + "> +\t\tcpu at 100 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\";\n" "> +\t\t\tenable-method = \"psci\";\n" @@ -130,7 +98,7 @@ "> +\t\t\tnext-level-cache = <&cluster1_l2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu@101 {\n" + "> +\t\tcpu at 101 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\";\n" "> +\t\t\tenable-method = \"psci\";\n" @@ -145,7 +113,7 @@ "> +\t\t\tnext-level-cache = <&cluster1_l2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu@200 {\n" + "> +\t\tcpu at 200 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\";\n" "> +\t\t\tenable-method = \"psci\";\n" @@ -160,7 +128,7 @@ "> +\t\t\tnext-level-cache = <&cluster2_l2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu@201 {\n" + "> +\t\tcpu at 201 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\";\n" "> +\t\t\tenable-method = \"psci\";\n" @@ -175,7 +143,7 @@ "> +\t\t\tnext-level-cache = <&cluster2_l2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu@300 {\n" + "> +\t\tcpu at 300 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\";\n" "> +\t\t\tenable-method = \"psci\";\n" @@ -190,7 +158,7 @@ "> +\t\t\tnext-level-cache = <&cluster3_l2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu@301 {\n" + "> +\t\tcpu at 301 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\";\n" "> +\t\t\tenable-method = \"psci\";\n" @@ -205,7 +173,7 @@ "> +\t\t\tnext-level-cache = <&cluster3_l2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu@400 {\n" + "> +\t\tcpu at 400 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\";\n" "> +\t\t\tenable-method = \"psci\";\n" @@ -220,7 +188,7 @@ "> +\t\t\tnext-level-cache = <&cluster4_l2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu@401 {\n" + "> +\t\tcpu at 401 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\";\n" "> +\t\t\tenable-method = \"psci\";\n" @@ -235,7 +203,7 @@ "> +\t\t\tnext-level-cache = <&cluster4_l2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu@500 {\n" + "> +\t\tcpu at 500 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\";\n" "> +\t\t\tenable-method = \"psci\";\n" @@ -250,7 +218,7 @@ "> +\t\t\tnext-level-cache = <&cluster5_l2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu@501 {\n" + "> +\t\tcpu at 501 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\";\n" "> +\t\t\tenable-method = \"psci\";\n" @@ -265,7 +233,7 @@ "> +\t\t\tnext-level-cache = <&cluster5_l2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu@600 {\n" + "> +\t\tcpu at 600 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\";\n" "> +\t\t\tenable-method = \"psci\";\n" @@ -280,7 +248,7 @@ "> +\t\t\tnext-level-cache = <&cluster6_l2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu@601 {\n" + "> +\t\tcpu at 601 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\";\n" "> +\t\t\tenable-method = \"psci\";\n" @@ -295,7 +263,7 @@ "> +\t\t\tnext-level-cache = <&cluster6_l2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu@700 {\n" + "> +\t\tcpu at 700 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\";\n" "> +\t\t\tenable-method = \"psci\";\n" @@ -310,7 +278,7 @@ "> +\t\t\tnext-level-cache = <&cluster7_l2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu@701 {\n" + "> +\t\tcpu at 701 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\";\n" "> +\t\t\tenable-method = \"psci\";\n" @@ -390,7 +358,7 @@ "> +\t\t};\n" "> +\t};\n" "> +\n" - "> +\tgic: interrupt-controller@6000000 {\n" + "> +\tgic: interrupt-controller at 6000000 {\n" "> +\t\tcompatible = \"arm,gic-v3\";\n" "> +\t\treg = <0x0 0x06000000 0 0x10000>, // GIC Dist\n" "> +\t\t\t<0x0 0x06200000 0 0x200000>, // GICR (RD_base +\n" @@ -405,7 +373,7 @@ "> +\t\tinterrupt-controller;\n" "> +\t\tinterrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;\n" "> +\n" - "> +\t\tits: gic-its@6020000 {\n" + "> +\t\tits: gic-its at 6020000 {\n" "> +\t\t\tcompatible = \"arm,gic-v3-its\";\n" "> +\t\t\tmsi-controller;\n" "> +\t\t\treg = <0x0 0x6020000 0 0x20000>;\n" @@ -430,20 +398,20 @@ "> +\t\tmethod = \"smc\";\n" "> +\t};\n" "> +\n" - "> +\tmemory@80000000 {\n" + "> +\tmemory at 80000000 {\n" "> +\t\t// DRAM space - 1, size : 2 GB DRAM\n" "> +\t\tdevice_type = \"memory\";\n" "> +\t\treg = <0x00000000 0x80000000 0 0x80000000>;\n" "> +\t};\n" "> +\n" - "> +\tddr1: memory-controller@1080000 {\n" + "> +\tddr1: memory-controller at 1080000 {\n" "> +\t\tcompatible = \"fsl,qoriq-memory-controller\";\n" "> +\t\treg = <0x0 0x1080000 0x0 0x1000>;\n" "> +\t\tinterrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;\n" "> +\t\tlittle-endian;\n" "> +\t};\n" "> +\n" - "> +\tddr2: memory-controller@1090000 {\n" + "> +\tddr2: memory-controller at 1090000 {\n" "> +\t\tcompatible = \"fsl,qoriq-memory-controller\";\n" "> +\t\treg = <0x0 0x1090000 0x0 0x1000>;\n" "> +\t\tinterrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -466,7 +434,7 @@ "> +\t\t#size-cells = <2>;\n" "> +\t\tranges;\n" "> +\n" - "> +\t\tclockgen: clocking@1300000 {\n" + "> +\t\tclockgen: clocking at 1300000 {\n" "\n" "clock-controller for node name.\n" "\n" @@ -476,7 +444,7 @@ "> +\t\t\tclocks = <&sysclk>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcrypto: crypto@8000000 {\n" + "> +\t\tcrypto: crypto at 8000000 {\n" "> +\t\t\tcompatible = \"fsl,sec-v5.0\", \"fsl,sec-v4.0\";\n" "> +\t\t\tfsl,sec-era = <10>;\n" "> +\t\t\t#address-cells = <1>;\n" @@ -487,28 +455,28 @@ "> +\t\t\tdma-coherent;\n" "> +\t\t\tstatus = \"disabled\";\n" "> +\n" - "> +\t\t\tsec_jr0: jr@10000 {\n" + "> +\t\t\tsec_jr0: jr at 10000 {\n" "> +\t\t\t\tcompatible = \"fsl,sec-v5.0-job-ring\",\n" "> +\t\t\t\t\t \"fsl,sec-v4.0-job-ring\";\n" "> +\t\t\t\treg = <0x10000 0x10000>;\n" "> +\t\t\t\tinterrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tsec_jr1: jr@20000 {\n" + "> +\t\t\tsec_jr1: jr at 20000 {\n" "> +\t\t\t\tcompatible = \"fsl,sec-v5.0-job-ring\",\n" "> +\t\t\t\t\t \"fsl,sec-v4.0-job-ring\";\n" "> +\t\t\t\treg = <0x20000 0x10000>;\n" "> +\t\t\t\tinterrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tsec_jr2: jr@30000 {\n" + "> +\t\t\tsec_jr2: jr at 30000 {\n" "> +\t\t\t\tcompatible = \"fsl,sec-v5.0-job-ring\",\n" "> +\t\t\t\t\t \"fsl,sec-v4.0-job-ring\";\n" "> +\t\t\t\treg = <0x30000 0x10000>;\n" "> +\t\t\t\tinterrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tsec_jr3: jr@40000 {\n" + "> +\t\t\tsec_jr3: jr at 40000 {\n" "> +\t\t\t\tcompatible = \"fsl,sec-v5.0-job-ring\",\n" "> +\t\t\t\t\t \"fsl,sec-v4.0-job-ring\";\n" "> +\t\t\t\treg = <0x40000 0x10000>;\n" @@ -516,7 +484,7 @@ "> +\t\t\t};\n" "> +\t\t};\n" "> +\n" - "> +\t\tdcfg: dcfg@1e00000 {\n" + "> +\t\tdcfg: dcfg at 1e00000 {\n" "\n" "As per suggestion from devicetree specification, we can \"syscon\" as\n" "a more generic node name?\n" @@ -526,7 +494,7 @@ "> +\t\t\tlittle-endian;\n" "> +\t\t};\n" "> +\n" - "> +\t\tgpio0: gpio@2300000 {\n" + "> +\t\tgpio0: gpio at 2300000 {\n" "> +\t\t\tcompatible = \"fsl,qoriq-gpio\";\n" "> +\t\t\treg = <0x0 0x2300000 0x0 0x10000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -537,7 +505,7 @@ "> +\t\t\t#interrupt-cells = <2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tgpio1: gpio@2310000 {\n" + "> +\t\tgpio1: gpio at 2310000 {\n" "> +\t\t\tcompatible = \"fsl,qoriq-gpio\";\n" "> +\t\t\treg = <0x0 0x2310000 0x0 0x10000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -548,7 +516,7 @@ "> +\t\t\t#interrupt-cells = <2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tgpio2: gpio@2320000 {\n" + "> +\t\tgpio2: gpio at 2320000 {\n" "> +\t\t\tcompatible = \"fsl,qoriq-gpio\";\n" "> +\t\t\treg = <0x0 0x2320000 0x0 0x10000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -559,7 +527,7 @@ "> +\t\t\t#interrupt-cells = <2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tgpio3: gpio@2330000 {\n" + "> +\t\tgpio3: gpio at 2330000 {\n" "> +\t\t\tcompatible = \"fsl,qoriq-gpio\";\n" "> +\t\t\treg = <0x0 0x2330000 0x0 0x10000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -570,7 +538,7 @@ "> +\t\t\t#interrupt-cells = <2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\ti2c0: i2c@2000000 {\n" + "> +\t\ti2c0: i2c at 2000000 {\n" "\n" "Sort the nodes under bus in order of unit-address.\n" "\n" @@ -588,7 +556,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\ti2c1: i2c@2010000 {\n" + "> +\t\ti2c1: i2c at 2010000 {\n" "> +\t\t\tcompatible = \"fsl,vf610-i2c\";\n" "> +\t\t\t#address-cells = <1>;\n" "> +\t\t\t#size-cells = <0>;\n" @@ -599,7 +567,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\ti2c2: i2c@2020000 {\n" + "> +\t\ti2c2: i2c at 2020000 {\n" "> +\t\t\tcompatible = \"fsl,vf610-i2c\";\n" "> +\t\t\t#address-cells = <1>;\n" "> +\t\t\t#size-cells = <0>;\n" @@ -610,7 +578,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\ti2c3: i2c@2030000 {\n" + "> +\t\ti2c3: i2c at 2030000 {\n" "> +\t\t\tcompatible = \"fsl,vf610-i2c\";\n" "> +\t\t\t#address-cells = <1>;\n" "> +\t\t\t#size-cells = <0>;\n" @@ -621,7 +589,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\ti2c4: i2c@2040000 {\n" + "> +\t\ti2c4: i2c at 2040000 {\n" "> +\t\t\tcompatible = \"fsl,vf610-i2c\";\n" "> +\t\t\t#address-cells = <1>;\n" "> +\t\t\t#size-cells = <0>;\n" @@ -633,7 +601,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\ti2c5: i2c@2050000 {\n" + "> +\t\ti2c5: i2c at 2050000 {\n" "> +\t\t\tcompatible = \"fsl,vf610-i2c\";\n" "> +\t\t\t#address-cells = <1>;\n" "> +\t\t\t#size-cells = <0>;\n" @@ -644,7 +612,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\ti2c6: i2c@2060000 {\n" + "> +\t\ti2c6: i2c at 2060000 {\n" "> +\t\t\tcompatible = \"fsl,vf610-i2c\";\n" "> +\t\t\t#address-cells = <1>;\n" "> +\t\t\t#size-cells = <0>;\n" @@ -655,7 +623,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\ti2c7: i2c@2070000 {\n" + "> +\t\ti2c7: i2c at 2070000 {\n" "> +\t\t\tcompatible = \"fsl,vf610-i2c\";\n" "> +\t\t\t#address-cells = <1>;\n" "> +\t\t\t#size-cells = <0>;\n" @@ -666,15 +634,15 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tuart0: serial@21c0000 {\n" + "> +\t\tuart0: serial at 21c0000 {\n" "> +\t\t\tdevice_type = \"serial\";\n" "\n" "Quote from devicetree specification:\n" "\n" - "The device_type property was used in IEEE 1275 to describe the device\342\200\231s\n" + "The device_type property was used in IEEE 1275 to describe the device?s\n" "FCode programming model. Because DTSpec does not have FCode, new use of\n" "the property is deprecated, and it should be included only on cpu and\n" - "memory nodes for compatibility with IEEE 1275\342\200\223derived devicetrees.\n" + "memory nodes for compatibility with IEEE 1275?derived devicetrees.\n" "\n" "> +\t\t\tcompatible = \"arm,sbsa-uart\",\"arm,pl011\";\n" "> +\t\t\treg = <0x0 0x21c0000 0x0 0x1000>;\n" @@ -683,7 +651,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tuart1: serial@21d0000 {\n" + "> +\t\tuart1: serial at 21d0000 {\n" "> +\t\t\tdevice_type = \"serial\";\n" "> +\t\t\tcompatible = \"arm,sbsa-uart\",\"arm,pl011\";\n" "> +\t\t\treg = <0x0 0x21d0000 0x0 0x1000>;\n" @@ -692,7 +660,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tuart2: serial@21e0000 {\n" + "> +\t\tuart2: serial at 21e0000 {\n" "> +\t\t\tdevice_type = \"serial\";\n" "> +\t\t\tcompatible = \"arm,sbsa-uart\",\"arm,pl011\";\n" "> +\t\t\treg = <0x0 0x21e0000 0x0 0x1000>;\n" @@ -701,7 +669,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tuart3: serial@21f0000 {\n" + "> +\t\tuart3: serial at 21f0000 {\n" "> +\t\t\tdevice_type = \"serial\";\n" "> +\t\t\tcompatible = \"arm,sbsa-uart\",\"arm,pl011\";\n" "> +\t\t\treg = <0x0 0x21f0000 0x0 0x1000>;\n" @@ -710,7 +678,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tsmmu: iommu@5000000 {\n" + "> +\t\tsmmu: iommu at 5000000 {\n" "> +\t\t\tcompatible = \"arm,mmu-500\";\n" "> +\t\t\treg = <0 0x5000000 0 0x800000>;\n" "> +\t\t\t#iommu-cells = <1>;\n" @@ -764,7 +732,7 @@ "> +\t\t\tdma-coherent;\n" "> +\t\t};\n" "> +\n" - "> +\t\tusb0: usb3@3100000 {\n" + "> +\t\tusb0: usb3 at 3100000 {\n" "\n" "usb for node name.\n" "\n" @@ -779,7 +747,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tusb1: usb3@3110000 {\n" + "> +\t\tusb1: usb3 at 3110000 {\n" "> +\t\t\tcompatible = \"snps,dwc3\";\n" "> +\t\t\treg = <0x0 0x3110000 0x0 0x10000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -789,7 +757,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\twatchdog@23a0000 {\n" + "> +\t\twatchdog at 23a0000 {\n" "> +\t\t\tcompatible = \"arm,sbsa-gwdt\";\n" "> +\t\t\treg = <0x0 0x23a0000 0 0x1000>,\n" "> +\t\t\t <0x0 0x2390000 0 0x1000>;\n" @@ -802,4 +770,4 @@ "> 2.7.4\n" > -35bbcbb4d7bf73d2d714a65007c302d5f45502cdf05c11332866a9bd193c3362 +a43a35779b0c541eff0d4049f5e302b3eaa35cf63496a01ffbf097c2d1400393
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