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Ip=[149.199.60.83]; Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO1PR02MB094 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 40.107.69.54 Subject: Re: [Qemu-arm] [PATCH v1 06/12] net: cadence_gem: Add support for selecting the DMA MemoryRegion X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: figlesia@xilinx.com, Stefano Stabellini , Sai Pavan Boddu , Francisco Iglesias , Alistair Francis , Richard Henderson , QEMU Developers , KONRAD Frederic , qemu-arm Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: "Qemu-arm" X-TUID: TIapXpPcegvn On Mon, Oct 08, 2018 at 01:30:20PM +0100, Peter Maydell wrote: > On 3 October 2018 at 16:07, Edgar E. Iglesias wrote: > > From: "Edgar E. Iglesias" > > > > Add support for selecting the Memory Region that the GEM > > will do DMA to. > > > > Signed-off-by: Edgar E. Iglesias > > --- > > hw/net/cadence_gem.c | 63 ++++++++++++++++++++++++++++---------------- > > include/hw/net/cadence_gem.h | 2 ++ > > 2 files changed, 43 insertions(+), 22 deletions(-) > > > > diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c > > index 759c1d7..ab02515 100644 > > --- a/hw/net/cadence_gem.c > > +++ b/hw/net/cadence_gem.c > > @@ -28,6 +28,7 @@ > > #include "hw/net/cadence_gem.h" > > #include "qapi/error.h" > > #include "qemu/log.h" > > +#include "sysemu/dma.h" > > #include "net/checksum.h" > > > > #ifdef CADENCE_GEM_ERR_DEBUG > > @@ -835,9 +836,9 @@ static void gem_get_rx_desc(CadenceGEMState *s, int q) > > { > > DB_PRINT("read descriptor 0x%x\n", (unsigned)s->rx_desc_addr[q]); > > /* read current descriptor */ > > - cpu_physical_memory_read(s->rx_desc_addr[q], > > - (uint8_t *)s->rx_desc[q], > > - sizeof(uint32_t) * gem_get_desc_len(s, true)); > > + address_space_read(s->dma_as, s->rx_desc_addr[q], MEMTXATTRS_UNSPECIFIED, > > + (uint8_t *)s->rx_desc[q], > > + sizeof(uint32_t) * gem_get_desc_len(s, true)); > > At some point you might want to add support for handling "descriptor > read/write failed", incidentally: address_space_read/write return a > MemTxResult which you can check for != MEMTX_OK. Yes, the GEM can report those errors to SW so that's a nice feature to follow up with. Thanks, Edgar From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33288) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g9bd6-0002Ca-8u for qemu-devel@nongnu.org; Mon, 08 Oct 2018 15:55:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g9bd5-0001ZL-Ae for qemu-devel@nongnu.org; Mon, 08 Oct 2018 15:55:48 -0400 Date: Mon, 8 Oct 2018 21:55:21 +0200 From: "Edgar E. Iglesias" Message-ID: <20181008195521.GB4229@toto> References: <1538579266-8389-1-git-send-email-edgar.iglesias@gmail.com> <1538579266-8389-7-git-send-email-edgar.iglesias@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: Subject: Re: [Qemu-devel] [PATCH v1 06/12] net: cadence_gem: Add support for selecting the DMA MemoryRegion List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: "Edgar E. Iglesias" , QEMU Developers , qemu-arm , Richard Henderson , KONRAD Frederic , Alistair Francis , Francisco Iglesias , figlesia@xilinx.com, Stefano Stabellini , Sai Pavan Boddu On Mon, Oct 08, 2018 at 01:30:20PM +0100, Peter Maydell wrote: > On 3 October 2018 at 16:07, Edgar E. Iglesias wrote: > > From: "Edgar E. Iglesias" > > > > Add support for selecting the Memory Region that the GEM > > will do DMA to. > > > > Signed-off-by: Edgar E. Iglesias > > --- > > hw/net/cadence_gem.c | 63 ++++++++++++++++++++++++++++---------------- > > include/hw/net/cadence_gem.h | 2 ++ > > 2 files changed, 43 insertions(+), 22 deletions(-) > > > > diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c > > index 759c1d7..ab02515 100644 > > --- a/hw/net/cadence_gem.c > > +++ b/hw/net/cadence_gem.c > > @@ -28,6 +28,7 @@ > > #include "hw/net/cadence_gem.h" > > #include "qapi/error.h" > > #include "qemu/log.h" > > +#include "sysemu/dma.h" > > #include "net/checksum.h" > > > > #ifdef CADENCE_GEM_ERR_DEBUG > > @@ -835,9 +836,9 @@ static void gem_get_rx_desc(CadenceGEMState *s, int q) > > { > > DB_PRINT("read descriptor 0x%x\n", (unsigned)s->rx_desc_addr[q]); > > /* read current descriptor */ > > - cpu_physical_memory_read(s->rx_desc_addr[q], > > - (uint8_t *)s->rx_desc[q], > > - sizeof(uint32_t) * gem_get_desc_len(s, true)); > > + address_space_read(s->dma_as, s->rx_desc_addr[q], MEMTXATTRS_UNSPECIFIED, > > + (uint8_t *)s->rx_desc[q], > > + sizeof(uint32_t) * gem_get_desc_len(s, true)); > > At some point you might want to add support for handling "descriptor > read/write failed", incidentally: address_space_read/write return a > MemTxResult which you can check for != MEMTX_OK. Yes, the GEM can report those errors to SW so that's a nice feature to follow up with. Thanks, Edgar