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Ip=[149.199.60.83]; Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY2PR02MB091 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 2a01:111:f400:fe50::630 Subject: Re: [Qemu-devel] [PATCH v1 09/12] target-arm: powerctl: Enable HVC when starting CPUs to EL2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: figlesia@xilinx.com, Stefano Stabellini , Sai Pavan Boddu , Francisco Iglesias , Alistair Francis , Richard Henderson , QEMU Developers , KONRAD Frederic , qemu-arm , "Edgar E. Iglesias" Errors-To: qemu-devel-bounces+alex.bennee=linaro.org@nongnu.org Sender: "Qemu-devel" X-TUID: hT6rZyGMBAMS On Mon, Oct 08, 2018 at 01:41:36PM +0100, Peter Maydell wrote: > On 3 October 2018 at 16:07, Edgar E. Iglesias wrote: > > From: "Edgar E. Iglesias" > > > > When QEMU provides the equivalent of the EL3 firmware, we > > need to enable HVCs in scr_el3 when turning on CPUs that > > target EL2. > > > > Signed-off-by: Edgar E. Iglesias > > --- > > target/arm/arm-powerctl.c | 11 +++++++++++ > > 1 file changed, 11 insertions(+) > > > > diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c > > index ce55eeb..54f2974 100644 > > --- a/target/arm/arm-powerctl.c > > +++ b/target/arm/arm-powerctl.c > > @@ -63,6 +63,7 @@ static void arm_set_cpu_on_async_work(CPUState *target_cpu_state, > > struct CpuOnInfo *info = (struct CpuOnInfo *) data.host_ptr; > > > > /* Initialize the cpu we are turning on */ > > + qemu_log("CPU%d reset\n", target_cpu_state->cpu_index); > > qemu_log logging should always be masked to a particular > log kind (either via qemu_log_mask() or by explicit check on > the log level). If this was accidentally left-in debug, you could > just drop it :-) Hah, yes this is an accidental leftover... > > > cpu_reset(target_cpu_state); > > target_cpu_state->halted = 0; > > > > @@ -103,6 +104,16 @@ static void arm_set_cpu_on_async_work(CPUState *target_cpu_state, > > } else { > > /* Processor is not in secure mode */ > > target_cpu->env.cp15.scr_el3 |= SCR_NS; > > + > > + /* > > + * If QEMU is providing the equivalent of EL3 firmware, then we need > > + * to make sure a CPU targeting EL2 comes out of reset with a > > + * functional HVC insn. > > + */ > > + if (arm_feature(&target_cpu->env, ARM_FEATURE_EL3) > > + && info->target_el == 2) { > > + target_cpu->env.cp15.scr_el3 |= SCR_HCE; > > + } > > } > > Otherwise > Reviewed-by: Peter Maydell > This is definitely required for PSCI and I think it makes sense > in other cases that end up in this powerctl code with EL3 set. Thanks, Edgar From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33570) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g9beK-00032Y-6m for qemu-devel@nongnu.org; Mon, 08 Oct 2018 15:57:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g9beJ-00026w-42 for qemu-devel@nongnu.org; Mon, 08 Oct 2018 15:57:04 -0400 Date: Mon, 8 Oct 2018 21:56:33 +0200 From: "Edgar E. Iglesias" Message-ID: <20181008195633.GC4229@toto> References: <1538579266-8389-1-git-send-email-edgar.iglesias@gmail.com> <1538579266-8389-10-git-send-email-edgar.iglesias@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: Subject: Re: [Qemu-devel] [PATCH v1 09/12] target-arm: powerctl: Enable HVC when starting CPUs to EL2 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: "Edgar E. Iglesias" , QEMU Developers , qemu-arm , Richard Henderson , KONRAD Frederic , Alistair Francis , Francisco Iglesias , figlesia@xilinx.com, Stefano Stabellini , Sai Pavan Boddu On Mon, Oct 08, 2018 at 01:41:36PM +0100, Peter Maydell wrote: > On 3 October 2018 at 16:07, Edgar E. Iglesias wrote: > > From: "Edgar E. Iglesias" > > > > When QEMU provides the equivalent of the EL3 firmware, we > > need to enable HVCs in scr_el3 when turning on CPUs that > > target EL2. > > > > Signed-off-by: Edgar E. Iglesias > > --- > > target/arm/arm-powerctl.c | 11 +++++++++++ > > 1 file changed, 11 insertions(+) > > > > diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c > > index ce55eeb..54f2974 100644 > > --- a/target/arm/arm-powerctl.c > > +++ b/target/arm/arm-powerctl.c > > @@ -63,6 +63,7 @@ static void arm_set_cpu_on_async_work(CPUState *target_cpu_state, > > struct CpuOnInfo *info = (struct CpuOnInfo *) data.host_ptr; > > > > /* Initialize the cpu we are turning on */ > > + qemu_log("CPU%d reset\n", target_cpu_state->cpu_index); > > qemu_log logging should always be masked to a particular > log kind (either via qemu_log_mask() or by explicit check on > the log level). If this was accidentally left-in debug, you could > just drop it :-) Hah, yes this is an accidental leftover... > > > cpu_reset(target_cpu_state); > > target_cpu_state->halted = 0; > > > > @@ -103,6 +104,16 @@ static void arm_set_cpu_on_async_work(CPUState *target_cpu_state, > > } else { > > /* Processor is not in secure mode */ > > target_cpu->env.cp15.scr_el3 |= SCR_NS; > > + > > + /* > > + * If QEMU is providing the equivalent of EL3 firmware, then we need > > + * to make sure a CPU targeting EL2 comes out of reset with a > > + * functional HVC insn. > > + */ > > + if (arm_feature(&target_cpu->env, ARM_FEATURE_EL3) > > + && info->target_el == 2) { > > + target_cpu->env.cp15.scr_el3 |= SCR_HCE; > > + } > > } > > Otherwise > Reviewed-by: Peter Maydell > This is definitely required for PSCI and I think it makes sense > in other cases that end up in this powerctl code with EL3 set. Thanks, Edgar