From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stefan Roese Date: Tue, 9 Oct 2018 08:59:04 +0200 Subject: [U-Boot] [PATCH 02/14] mips: mt76xx: lowlevel_init.S: Add missing memory controller reset in DDR init In-Reply-To: <20181009065916.31977-1-sr@denx.de> References: <20181009065916.31977-1-sr@denx.de> Message-ID: <20181009065916.31977-2-sr@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de This fixes an issue which has been noticed on the Gardena board, with the watchdog enabled, where the watdchdog reset (after a system hang) did result in reporting of 2.9 GiB and a hang after this. With this patch applied the memory controller is correctly reset and initialized again even after a watchdog reset. Signed-off-by: Stefan Roese Cc: Daniel Schwierzeck --- arch/mips/mach-mt7620/lowlevel_init.S | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/mips/mach-mt7620/lowlevel_init.S b/arch/mips/mach-mt7620/lowlevel_init.S index 1a50f160fe..aa707e0de6 100644 --- a/arch/mips/mach-mt7620/lowlevel_init.S +++ b/arch/mips/mach-mt7620/lowlevel_init.S @@ -108,6 +108,12 @@ CPLL_READY: sw t3, 0(t0) CPLL_DONE: + /* Reset MC */ + lw t2, 0x34(s0) + ori t2, BIT(10) + sw t2, 0x34(s0) + nop + /* * SDR and DDR initialization: delay 200us */ -- 2.19.1