diff for duplicates of <20181009125747.GS4229@toto> diff --git a/a/1.txt b/N1/1.txt index 1f60a4d..7f4a0a8 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -55,7 +55,7 @@ users really want to pass one. At the moment, Versal only exists in FPGA based emulation boards. These implementations are flexible in that different configurations can be re-programmed onto the FPGAs at any time. -From my perspective, the name of the board is not so important. We can +>From my perspective, the name of the board is not so important. We can call it Xilinx Versal QEMU Developer board, Xilinx Versal Emulation Board, or what ever but it would be nice to keep the characteristics of an phsyically unconstrained board and the auto-generated device-tree. diff --git a/a/content_digest b/N1/content_digest index 608b9e2..633912c 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,18 +1,19 @@ "ref\01538579266-8389-1-git-send-email-edgar.iglesias@gmail.com\0" "ref\0CAFEAcA8PHLZGfYpwU=zsG8eZ==hWu-b9CLJ_7Z+8+C5YvgZfuQ@mail.gmail.com\0" "From\0Edgar E. Iglesias <edgar.iglesias@xilinx.com>\0" - "Subject\0Re: [Qemu-arm] [PATCH v1 00/12] arm: Add first models of Xilinx Versal SoC\0" + "Subject\0Re: [Qemu-devel] [PATCH v1 00/12] arm: Add first models of Xilinx Versal SoC\0" "Date\0Tue, 9 Oct 2018 14:57:47 +0200\0" "To\0Peter Maydell <peter.maydell@linaro.org>\0" - "Cc\0figlesia@xilinx.com" - Stefano Stabellini <sstabellini@kernel.org> - Sai Pavan Boddu <sai.pavan.boddu@xilinx.com> - Francisco Iglesias <frasse.iglesias@gmail.com> - Alistair Francis <alistair@alistair23.me> - Richard Henderson <richard.henderson@linaro.org> + "Cc\0Edgar E. Iglesias <edgar.iglesias@gmail.com>" QEMU Developers <qemu-devel@nongnu.org> + qemu-arm <qemu-arm@nongnu.org> + Richard Henderson <richard.henderson@linaro.org> KONRAD Frederic <frederic.konrad@adacore.com> - " qemu-arm <qemu-arm@nongnu.org>\0" + Alistair Francis <alistair@alistair23.me> + Francisco Iglesias <frasse.iglesias@gmail.com> + figlesia@xilinx.com + Stefano Stabellini <sstabellini@kernel.org> + " Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>\0" "\00:1\0" "b\0" "On Mon, Oct 08, 2018 at 03:08:14PM +0100, Peter Maydell wrote:\n" @@ -72,7 +73,7 @@ "At the moment, Versal only exists in FPGA based emulation boards.\n" "These implementations are flexible in that different configurations can\n" "be re-programmed onto the FPGAs at any time.\n" - "From my perspective, the name of the board is not so important. We can\n" + ">From my perspective, the name of the board is not so important. We can\n" "call it Xilinx Versal QEMU Developer board, Xilinx Versal Emulation Board,\n" "or what ever but it would be nice to keep the characteristics of an\n" "phsyically unconstrained board and the auto-generated device-tree.\n" @@ -82,4 +83,4 @@ "Thanks and Best regards,\n" Edgar -45ceb31852630780337ca33ce240ed9af75743d4c180142122c7fe2390b19a6b +17788cad8b6252ab48ec2301f8f6d0d0c59945175eaeef4db02115bcc660057d
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