From mboxrd@z Thu Jan 1 00:00:00 1970 From: Boris Brezillon Subject: Re: [PATCH 2/4] drm/v3d: Add a little debugfs entry for measuring the core clock. Date: Tue, 9 Oct 2018 15:26:40 +0200 Message-ID: <20181009152640.791c709d@bbrezillon> References: <20180928232126.4332-1-eric@anholt.net> <20180928232126.4332-2-eric@anholt.net> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mail.bootlin.com (mail.bootlin.com [62.4.15.54]) by gabe.freedesktop.org (Postfix) with ESMTP id CD14A6E32F for ; Tue, 9 Oct 2018 13:26:42 +0000 (UTC) In-Reply-To: <20180928232126.4332-2-eric@anholt.net> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Eric Anholt Cc: linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org List-Id: dri-devel@lists.freedesktop.org T24gRnJpLCAyOCBTZXAgMjAxOCAxNjoyMToyNCAtMDcwMApFcmljIEFuaG9sdCA8ZXJpY0Bhbmhv bHQubmV0PiB3cm90ZToKCj4gVGhpcyBhZGRzIGp1c3QgZW5vdWdoIHBlcmZvcm1hbmNlIGNvdW50 ZXIgc3VwcG9ydCB0byBtZWFzdXJlIHRoZQo+IGNsb2NrLiAgV2UgZG9uJ3QgaGF2ZSBsaW51eCBr ZXJuZWwgZHJpdmVycyBmb3IgdGhlIGNsb2NrIGRyaXZpbmcgdGhlCj4gSFcsIGFuZCB0aGlzIHdh cyB1c2VmdWwgZm9yIGRldGVybWluaW5nIHRoYXQgdGhlIFYzRCBIVyBpcyBydW5uaW5nIG9uCj4g YSBzbG93IGNsb2NrLCBub3QgdGhhdCB0aGUgZHJpdmVyIHdhcyBzbG93Lgo+IAo+IFNpZ25lZC1v ZmYtYnk6IEVyaWMgQW5ob2x0IDxlcmljQGFuaG9sdC5uZXQ+CgpSZXZpZXdlZC1ieTogQm9yaXMg QnJlemlsbG9uIDxib3Jpcy5icmV6aWxsb25AYm9vdGxpbi5jb20+Cgo+IC0tLQo+ICBkcml2ZXJz L2dwdS9kcm0vdjNkL3YzZF9kZWJ1Z2ZzLmMgfCAzNSArKysrKysrKysrKysrKysrKysrKysrKysr KysrKysrCj4gIGRyaXZlcnMvZ3B1L2RybS92M2QvdjNkX3JlZ3MuaCAgICB8IDMwICsrKysrKysr KysrKysrKysrKysrKysrKysrCj4gIDIgZmlsZXMgY2hhbmdlZCwgNjUgaW5zZXJ0aW9ucygrKQo+ IAo+IGRpZmYgLS1naXQgYS9kcml2ZXJzL2dwdS9kcm0vdjNkL3YzZF9kZWJ1Z2ZzLmMgYi9kcml2 ZXJzL2dwdS9kcm0vdjNkL3YzZF9kZWJ1Z2ZzLmMKPiBpbmRleCA0ZGI2MmM1NDU3NDguLmQ0ODAw OGFkYjA4NSAxMDA2NDQKPiAtLS0gYS9kcml2ZXJzL2dwdS9kcm0vdjNkL3YzZF9kZWJ1Z2ZzLmMK PiArKysgYi9kcml2ZXJzL2dwdS9kcm0vdjNkL3YzZF9kZWJ1Z2ZzLmMKPiBAQCAtMTc2LDkgKzE3 Niw0NCBAQCBzdGF0aWMgaW50IHYzZF9kZWJ1Z2ZzX2JvX3N0YXRzKHN0cnVjdCBzZXFfZmlsZSAq bSwgdm9pZCAqdW51c2VkKQo+ICAJcmV0dXJuIDA7Cj4gIH0KPiAgCj4gK3N0YXRpYyBpbnQgdjNk X21lYXN1cmVfY2xvY2soc3RydWN0IHNlcV9maWxlICptLCB2b2lkICp1bnVzZWQpCj4gK3sKPiAr CXN0cnVjdCBkcm1faW5mb19ub2RlICpub2RlID0gKHN0cnVjdCBkcm1faW5mb19ub2RlICopbS0+ cHJpdmF0ZTsKPiArCXN0cnVjdCBkcm1fZGV2aWNlICpkZXYgPSBub2RlLT5taW5vci0+ZGV2Owo+ ICsJc3RydWN0IHYzZF9kZXYgKnYzZCA9IHRvX3YzZF9kZXYoZGV2KTsKPiArCXVpbnQzMl90IGN5 Y2xlczsKPiArCWludCBjb3JlID0gMDsKPiArCWludCBtZWFzdXJlX21zID0gMTAwMDsKPiArCj4g KwlpZiAodjNkLT52ZXIgPj0gNDApIHsKPiArCQlWM0RfQ09SRV9XUklURShjb3JlLCBWM0RfVjRf UENUUl8wX1NSQ18wXzMsCj4gKwkJCSAgICAgICBWM0RfU0VUX0ZJRUxEKFYzRF9QQ1RSX0NZQ0xF X0NPVU5ULAo+ICsJCQkJCSAgICAgVjNEX1BDVFJfUzApKTsKPiArCQlWM0RfQ09SRV9XUklURShj b3JlLCBWM0RfVjRfUENUUl8wX0NMUiwgMSk7Cj4gKwkJVjNEX0NPUkVfV1JJVEUoY29yZSwgVjNE X1Y0X1BDVFJfMF9FTiwgMSk7Cj4gKwl9IGVsc2Ugewo+ICsJCVYzRF9DT1JFX1dSSVRFKGNvcmUs IFYzRF9WM19QQ1RSXzBfUENUUlMwLAo+ICsJCQkgICAgICAgVjNEX1BDVFJfQ1lDTEVfQ09VTlQp Owo+ICsJCVYzRF9DT1JFX1dSSVRFKGNvcmUsIFYzRF9WM19QQ1RSXzBfQ0xSLCAxKTsKPiArCQlW M0RfQ09SRV9XUklURShjb3JlLCBWM0RfVjNfUENUUl8wX0VOLAo+ICsJCQkgICAgICAgVjNEX1Yz X1BDVFJfMF9FTl9FTkFCTEUgfAo+ICsJCQkgICAgICAgMSk7Cj4gKwl9Cj4gKwltc2xlZXAobWVh c3VyZV9tcyk7Cj4gKwljeWNsZXMgPSBWM0RfQ09SRV9SRUFEKGNvcmUsIFYzRF9QQ1RSXzBfUENU UjApOwo+ICsKPiArCXNlcV9wcmludGYobSwgImN5Y2xlczogJWQgKCVkLiVkIE1oeilcbiIsCj4g KwkJICAgY3ljbGVzLAo+ICsJCSAgIGN5Y2xlcyAvIChtZWFzdXJlX21zICogMTAwMCksCj4gKwkJ ICAgKGN5Y2xlcyAvIChtZWFzdXJlX21zICogMTAwKSkgJSAxMCk7Cj4gKwo+ICsJcmV0dXJuIDA7 Cj4gK30KPiArCj4gIHN0YXRpYyBjb25zdCBzdHJ1Y3QgZHJtX2luZm9fbGlzdCB2M2RfZGVidWdm c19saXN0W10gPSB7Cj4gIAl7InYzZF9pZGVudCIsIHYzZF92M2RfZGVidWdmc19pZGVudCwgMH0s Cj4gIAl7InYzZF9yZWdzIiwgdjNkX3YzZF9kZWJ1Z2ZzX3JlZ3MsIDB9LAo+ICsJeyJtZWFzdXJl X2Nsb2NrIiwgdjNkX21lYXN1cmVfY2xvY2ssIDB9LAo+ICAJeyJib19zdGF0cyIsIHYzZF9kZWJ1 Z2ZzX2JvX3N0YXRzLCAwfSwKPiAgfTsKPiAgCj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2Ry bS92M2QvdjNkX3JlZ3MuaCBiL2RyaXZlcnMvZ3B1L2RybS92M2QvdjNkX3JlZ3MuaAo+IGluZGV4 IDg1NDA0NjU2NTk4OS4uYzNhNWU0ZTQ0ZjczIDEwMDY0NAo+IC0tLSBhL2RyaXZlcnMvZ3B1L2Ry bS92M2QvdjNkX3JlZ3MuaAo+ICsrKyBiL2RyaXZlcnMvZ3B1L2RybS92M2QvdjNkX3JlZ3MuaAo+ IEBAIC0yNjcsNiArMjY3LDM2IEBACj4gICMgZGVmaW5lIFYzRF9QVEJfQlhDRl9SV09SREVSRElT QSAgICAgICAgICAgICAgICAgICAgICBCSVQoMSkKPiAgIyBkZWZpbmUgVjNEX1BUQl9CWENGX0NM SVBESVNBICAgICAgICAgICAgICAgICAgICAgICAgIEJJVCgwKQo+ICAKPiArI2RlZmluZSBWM0Rf VjNfUENUUl8wX0VOICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIDB4MDA2NzQKPiArI2Rl ZmluZSBWM0RfVjNfUENUUl8wX0VOX0VOQUJMRSAgICAgICAgICAgICAgICAgICAgICAgIEJJVCgz MSkKPiArI2RlZmluZSBWM0RfVjRfUENUUl8wX0VOICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgIDB4MDA2NTAKPiArLyogV2hlbiBhIGJpdCBpcyBzZXQsIHJlc2V0cyB0aGUgY291bnRlciB0 byAwLiAqLwo+ICsjZGVmaW5lIFYzRF9WM19QQ1RSXzBfQ0xSICAgICAgICAgICAgICAgICAgICAg ICAgICAgICAgMHgwMDY3MAo+ICsjZGVmaW5lIFYzRF9WNF9QQ1RSXzBfQ0xSICAgICAgICAgICAg ICAgICAgICAgICAgICAgICAgMHgwMDY1NAo+ICsjZGVmaW5lIFYzRF9QQ1RSXzBfT1ZFUkZMT1cg ICAgICAgICAgICAgICAgICAgICAgICAgICAgMHgwMDY1OAo+ICsKPiArI2RlZmluZSBWM0RfVjNf UENUUl8wX1BDVFJTMCAgICAgICAgICAgICAgICAgICAgICAgICAgIDB4MDA2ODQKPiArI2RlZmlu ZSBWM0RfVjNfUENUUl8wX1BDVFJTMTUgICAgICAgICAgICAgICAgICAgICAgICAgIDB4MDA2NjAK PiArI2RlZmluZSBWM0RfVjNfUENUUl8wX1BDVFJTWCh4KSAgICAgICAgICAgICAgICAgICAgICAg IChWM0RfVjNfUENUUl8wX1BDVFJTMCArIFwKPiArCQkJCQkJCTQgKiAoeCkpCj4gKy8qIEVhY2gg c3JjIHJlZyBtdXhlcyBmb3VyIGNvdW50ZXJzIGVhY2guICovCj4gKyNkZWZpbmUgVjNEX1Y0X1BD VFJfMF9TUkNfMF8zICAgICAgICAgICAgICAgICAgICAgICAgICAweDAwNjYwCj4gKyNkZWZpbmUg VjNEX1Y0X1BDVFJfMF9TUkNfMjhfMzEgICAgICAgICAgICAgICAgICAgICAgICAweDAwNjdjCj4g KyMgZGVmaW5lIFYzRF9QQ1RSX1MwX01BU0sgICAgICAgICAgICAgICAgICAgICAgICAgICAgICBW M0RfTUFTSyg2LCAwKQo+ICsjIGRlZmluZSBWM0RfUENUUl9TMF9TSElGVCAgICAgICAgICAgICAg ICAgICAgICAgICAgICAgMAo+ICsjIGRlZmluZSBWM0RfUENUUl9TMV9NQVNLICAgICAgICAgICAg ICAgICAgICAgICAgICAgICAgVjNEX01BU0soMTQsIDgpCj4gKyMgZGVmaW5lIFYzRF9QQ1RSX1Mx X1NISUZUICAgICAgICAgICAgICAgICAgICAgICAgICAgICA4Cj4gKyMgZGVmaW5lIFYzRF9QQ1RS X1MyX01BU0sgICAgICAgICAgICAgICAgICAgICAgICAgICAgICBWM0RfTUFTSygyMiwgMTYpCj4g KyMgZGVmaW5lIFYzRF9QQ1RSX1MyX1NISUZUICAgICAgICAgICAgICAgICAgICAgICAgICAgICAx Ngo+ICsjIGRlZmluZSBWM0RfUENUUl9TM19NQVNLICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgVjNEX01BU0soMzAsIDI0KQo+ICsjIGRlZmluZSBWM0RfUENUUl9TM19TSElGVCAgICAgICAg ICAgICAgICAgICAgICAgICAgICAgMjQKPiArIyBkZWZpbmUgVjNEX1BDVFJfQ1lDTEVfQ09VTlQg ICAgICAgICAgICAgICAgICAgICAgICAgIDMyCj4gKwo+ICsvKiBPdXRwdXQgdmFsdWVzIG9mIHRo ZSBjb3VudGVycy4gKi8KPiArI2RlZmluZSBWM0RfUENUUl8wX1BDVFIwICAgICAgICAgICAgICAg ICAgICAgICAgICAgICAgIDB4MDA2ODAKPiArI2RlZmluZSBWM0RfUENUUl8wX1BDVFIzMSAgICAg ICAgICAgICAgICAgICAgICAgICAgICAgIDB4MDA2ZmMKPiArI2RlZmluZSBWM0RfUENUUl8wX1BD VFJYKHgpICAgICAgICAgICAgICAgICAgICAgICAgICAgIChWM0RfUENUUl8wX1BDVFIwICsgXAo+ ICsJCQkJCQkJNCAqICh4KSkKPiAgI2RlZmluZSBWM0RfR01QX1NUQVRVUyAgICAgICAgICAgICAg ICAgICAgICAgICAgICAgICAgIDB4MDA4MDAKPiAgIyBkZWZpbmUgVjNEX0dNUF9TVEFUVVNfR01Q UlNUICAgICAgICAgICAgICAgICAgICAgICAgIEJJVCgzMSkKPiAgIyBkZWZpbmUgVjNEX0dNUF9T VEFUVVNfV1JfQ09VTlRfTUFTSyAgICAgICAgICAgICAgICAgIFYzRF9NQVNLKDMwLCAyNCkKCl9f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCmRyaS1kZXZlbCBt YWlsaW5nIGxpc3QKZHJpLWRldmVsQGxpc3RzLmZyZWVkZXNrdG9wLm9yZwpodHRwczovL2xpc3Rz LmZyZWVkZXNrdG9wLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2RyaS1kZXZlbAo= From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5F803C64EB8 for ; Tue, 9 Oct 2018 13:26:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3176D2054F for ; Tue, 9 Oct 2018 13:26:46 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3176D2054F Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bootlin.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728026AbeJIUnk (ORCPT ); Tue, 9 Oct 2018 16:43:40 -0400 Received: from mail.bootlin.com ([62.4.15.54]:51035 "EHLO mail.bootlin.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726496AbeJIUnj (ORCPT ); Tue, 9 Oct 2018 16:43:39 -0400 Received: by mail.bootlin.com (Postfix, from userid 110) id D02A1207C3; Tue, 9 Oct 2018 15:26:40 +0200 (CEST) Received: from bbrezillon (AAubervilliers-681-1-28-153.w90-88.abo.wanadoo.fr [90.88.148.153]) by mail.bootlin.com (Postfix) with ESMTPSA id 95F1820712; Tue, 9 Oct 2018 15:26:40 +0200 (CEST) Date: Tue, 9 Oct 2018 15:26:40 +0200 From: Boris Brezillon To: Eric Anholt Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 2/4] drm/v3d: Add a little debugfs entry for measuring the core clock. Message-ID: <20181009152640.791c709d@bbrezillon> In-Reply-To: <20180928232126.4332-2-eric@anholt.net> References: <20180928232126.4332-1-eric@anholt.net> <20180928232126.4332-2-eric@anholt.net> X-Mailer: Claws Mail 3.15.0-dirty (GTK+ 2.24.31; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, 28 Sep 2018 16:21:24 -0700 Eric Anholt wrote: > This adds just enough performance counter support to measure the > clock. We don't have linux kernel drivers for the clock driving the > HW, and this was useful for determining that the V3D HW is running on > a slow clock, not that the driver was slow. > > Signed-off-by: Eric Anholt Reviewed-by: Boris Brezillon > --- > drivers/gpu/drm/v3d/v3d_debugfs.c | 35 +++++++++++++++++++++++++++++++ > drivers/gpu/drm/v3d/v3d_regs.h | 30 ++++++++++++++++++++++++++ > 2 files changed, 65 insertions(+) > > diff --git a/drivers/gpu/drm/v3d/v3d_debugfs.c b/drivers/gpu/drm/v3d/v3d_debugfs.c > index 4db62c545748..d48008adb085 100644 > --- a/drivers/gpu/drm/v3d/v3d_debugfs.c > +++ b/drivers/gpu/drm/v3d/v3d_debugfs.c > @@ -176,9 +176,44 @@ static int v3d_debugfs_bo_stats(struct seq_file *m, void *unused) > return 0; > } > > +static int v3d_measure_clock(struct seq_file *m, void *unused) > +{ > + struct drm_info_node *node = (struct drm_info_node *)m->private; > + struct drm_device *dev = node->minor->dev; > + struct v3d_dev *v3d = to_v3d_dev(dev); > + uint32_t cycles; > + int core = 0; > + int measure_ms = 1000; > + > + if (v3d->ver >= 40) { > + V3D_CORE_WRITE(core, V3D_V4_PCTR_0_SRC_0_3, > + V3D_SET_FIELD(V3D_PCTR_CYCLE_COUNT, > + V3D_PCTR_S0)); > + V3D_CORE_WRITE(core, V3D_V4_PCTR_0_CLR, 1); > + V3D_CORE_WRITE(core, V3D_V4_PCTR_0_EN, 1); > + } else { > + V3D_CORE_WRITE(core, V3D_V3_PCTR_0_PCTRS0, > + V3D_PCTR_CYCLE_COUNT); > + V3D_CORE_WRITE(core, V3D_V3_PCTR_0_CLR, 1); > + V3D_CORE_WRITE(core, V3D_V3_PCTR_0_EN, > + V3D_V3_PCTR_0_EN_ENABLE | > + 1); > + } > + msleep(measure_ms); > + cycles = V3D_CORE_READ(core, V3D_PCTR_0_PCTR0); > + > + seq_printf(m, "cycles: %d (%d.%d Mhz)\n", > + cycles, > + cycles / (measure_ms * 1000), > + (cycles / (measure_ms * 100)) % 10); > + > + return 0; > +} > + > static const struct drm_info_list v3d_debugfs_list[] = { > {"v3d_ident", v3d_v3d_debugfs_ident, 0}, > {"v3d_regs", v3d_v3d_debugfs_regs, 0}, > + {"measure_clock", v3d_measure_clock, 0}, > {"bo_stats", v3d_debugfs_bo_stats, 0}, > }; > > diff --git a/drivers/gpu/drm/v3d/v3d_regs.h b/drivers/gpu/drm/v3d/v3d_regs.h > index 854046565989..c3a5e4e44f73 100644 > --- a/drivers/gpu/drm/v3d/v3d_regs.h > +++ b/drivers/gpu/drm/v3d/v3d_regs.h > @@ -267,6 +267,36 @@ > # define V3D_PTB_BXCF_RWORDERDISA BIT(1) > # define V3D_PTB_BXCF_CLIPDISA BIT(0) > > +#define V3D_V3_PCTR_0_EN 0x00674 > +#define V3D_V3_PCTR_0_EN_ENABLE BIT(31) > +#define V3D_V4_PCTR_0_EN 0x00650 > +/* When a bit is set, resets the counter to 0. */ > +#define V3D_V3_PCTR_0_CLR 0x00670 > +#define V3D_V4_PCTR_0_CLR 0x00654 > +#define V3D_PCTR_0_OVERFLOW 0x00658 > + > +#define V3D_V3_PCTR_0_PCTRS0 0x00684 > +#define V3D_V3_PCTR_0_PCTRS15 0x00660 > +#define V3D_V3_PCTR_0_PCTRSX(x) (V3D_V3_PCTR_0_PCTRS0 + \ > + 4 * (x)) > +/* Each src reg muxes four counters each. */ > +#define V3D_V4_PCTR_0_SRC_0_3 0x00660 > +#define V3D_V4_PCTR_0_SRC_28_31 0x0067c > +# define V3D_PCTR_S0_MASK V3D_MASK(6, 0) > +# define V3D_PCTR_S0_SHIFT 0 > +# define V3D_PCTR_S1_MASK V3D_MASK(14, 8) > +# define V3D_PCTR_S1_SHIFT 8 > +# define V3D_PCTR_S2_MASK V3D_MASK(22, 16) > +# define V3D_PCTR_S2_SHIFT 16 > +# define V3D_PCTR_S3_MASK V3D_MASK(30, 24) > +# define V3D_PCTR_S3_SHIFT 24 > +# define V3D_PCTR_CYCLE_COUNT 32 > + > +/* Output values of the counters. */ > +#define V3D_PCTR_0_PCTR0 0x00680 > +#define V3D_PCTR_0_PCTR31 0x006fc > +#define V3D_PCTR_0_PCTRX(x) (V3D_PCTR_0_PCTR0 + \ > + 4 * (x)) > #define V3D_GMP_STATUS 0x00800 > # define V3D_GMP_STATUS_GMPRST BIT(31) > # define V3D_GMP_STATUS_WR_COUNT_MASK V3D_MASK(30, 24)