From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [v3,4/7] dmaengine: stm32-dma: Add DMA/MDMA chaining support From: Vinod Koul Message-Id: <20181010040343.GO2372@vkoul-mobl> Date: Wed, 10 Oct 2018 09:33:43 +0530 To: Pierre Yves MORDRET Cc: Rob Herring , Mark Rutland , Alexandre Torgue , Maxime Coquelin , Dan Williams , devicetree@vger.kernel.org, dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org List-ID: T24gMDktMTAtMTgsIDEwOjQwLCBQaWVycmUgWXZlcyBNT1JEUkVUIHdyb3RlOgo+IAo+IAo+IE9u IDEwLzA3LzIwMTggMDY6MDAgUE0sIFZpbm9kIHdyb3RlOgo+ID4gT24gMjgtMDktMTgsIDE1OjAx LCBQaWVycmUtWXZlcyBNT1JEUkVUIHdyb3RlOgo+ID4+IFRoaXMgcGF0Y2ggYWRkcyBzdXBwb3J0 IG9mIERNQS9NRE1BIGNoYWluaW5nIHN1cHBvcnQuCj4gPj4gSXQgaW50cm9kdWNlcyBhbiBpbnRl cm1lZGlhdGUgdHJhbnNmZXIgYmV0d2VlbiBwZXJpcGhlcmFscyBhbmQgU1RNMzIgRE1BLgo+ID4+ IFRoaXMgaW50ZXJtZWRpYXRlIHRyYW5zZmVyIGlzIHRyaWdnZXJlZCBieSBTVyBmb3Igc2luZ2xl IE0yRCB0cmFuc2ZlciBhbmQKPiA+PiBieSBTVE0zMiBETUEgSVAgZm9yIGFsbCBvdGhlciBtb2Rl cyAoc2csIGN5Y2xpYykgYW5kIGRpcmVjdGlvbiAoRDJNKS4KPiA+Pgo+ID4+IEEgZ2VuZXJpYyBT UkFNIGFsbG9jYXRvciBpcyB1c2VkIGZvciB0aGlzIGludGVybWVkaWF0ZSBidWZmZXIKPiA+PiBF YWNoIERNQSBjaGFubmVsIHdpbGwgYmUgYWJsZSB0byBkZWZpbmUgaXRzIFNSQU0gbmVlZHMgdG8g YWNoaWV2ZSBjaGFpbmluZwo+ID4+IGZlYXR1cmUgOiAoMiBeIG9yZGVyKSAqIFBBR0VfU0laRS4K PiA+PiBGb3IgY3ljbGljLCBTUkFNIGJ1ZmZlciBpcyBkZXJpdmVkIGZyb20gcGVyaW9kIGxlbmd0 aCAocm91bmRlZCBvbgo+ID4+IFBBR0VfU0laRSkuCj4gPiAKPiA+IFNvIElJVUMsIHlvdSBjaGFp biB0d28gZG1hIHR4bnMgdG9nZXRoZXIgYW5kIHRyYW5zZmVyIGRhdGEgdmlhIGFuIFNSQU0/Cj4g Cj4gQ29ycmVjdC4gb25lIERNQSBpcyBETUF2MiAoc3RtMzItZG1hKSBhbmQgdGhlIG90aGVyIGlz IE1ETUEoc3RtMzItbWRtYSkuCj4gSW50ZXJtZWRpYXRlIHRyYW5zZmVyIGlzIGJldHdlZW4gZGV2 aWNlIGFuZCBtZW1vcnkuCj4gVGhpcyBpbnRlcm1lZGlhdGUgdHJhbnNmZXIgaXMgdXNpbmcgU0RS QU0uCgpBaCBzbyB5b3UgdXNlIGRtYSBjYWxscyB0byBzZXR1cCBtZG1hIHh0ZmVycz8gSSBkb250 IHRoaW5rIHRoYXQgaXMgYQpnb29kIGlkZWEuIEhvdyBkbyB5b3Uga25vdyB5b3Ugc2hvdWxkIHVz ZSBtZG1hIGZvciBzdWJzZXF1ZW50IHRyYW5zZmVyPwoKCj4gPj4gIGRyaXZlcnMvZG1hL3N0bTMy LWRtYS5jIHwgODc5ICsrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKy0t LS0tLQo+ID4gCj4gPiB0aGF0IGlzIGEgbG90IG9mIGNoYW5nZSBmb3IgYSBkcml2ZXIsIGNvbnNp ZGVyIHNwbGl0dGluZyBpdCB1cAo+ID4gbG9naWNhbGx5IGluIHNtYWxsZXIgY2hhbmdlcy4uLgo+ ID4gCj4gCj4gVGhpcyBmZWF0dXJlIGlzIHJhdGhlciBtb25vbGl0aGljLiBEaWZmaWN1bHQgdG8g c3BsaXQgdXAuCj4gQWxsIHRoZSBjb2RlIGlzIHJlcXVpcmVkIGF0IG9uY2UuCgpJdCBjYW4gYmUg ZW5hYmxlZCBhdCBsYXN0IGJ1dCBzcGxpdCB1cCBsb2dpY2FsbHkuIEludHJ1c2l2ZSBjaGFuZ2Vz IHRvIGEKZHJpdmVyIG1ha2UgaXQgaGFyZCB0byByZXZpZXcuLgo= From mboxrd@z Thu Jan 1 00:00:00 1970 From: vkoul@kernel.org (Vinod) Date: Wed, 10 Oct 2018 09:33:43 +0530 Subject: [PATCH v3 4/7] dmaengine: stm32-dma: Add DMA/MDMA chaining support In-Reply-To: References: <1538139715-24406-1-git-send-email-pierre-yves.mordret@st.com> <1538139715-24406-5-git-send-email-pierre-yves.mordret@st.com> <20181007160030.GB2372@vkoul-mobl> Message-ID: <20181010040343.GO2372@vkoul-mobl> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 09-10-18, 10:40, Pierre Yves MORDRET wrote: > > > On 10/07/2018 06:00 PM, Vinod wrote: > > On 28-09-18, 15:01, Pierre-Yves MORDRET wrote: > >> This patch adds support of DMA/MDMA chaining support. > >> It introduces an intermediate transfer between peripherals and STM32 DMA. > >> This intermediate transfer is triggered by SW for single M2D transfer and > >> by STM32 DMA IP for all other modes (sg, cyclic) and direction (D2M). > >> > >> A generic SRAM allocator is used for this intermediate buffer > >> Each DMA channel will be able to define its SRAM needs to achieve chaining > >> feature : (2 ^ order) * PAGE_SIZE. > >> For cyclic, SRAM buffer is derived from period length (rounded on > >> PAGE_SIZE). > > > > So IIUC, you chain two dma txns together and transfer data via an SRAM? > > Correct. one DMA is DMAv2 (stm32-dma) and the other is MDMA(stm32-mdma). > Intermediate transfer is between device and memory. > This intermediate transfer is using SDRAM. Ah so you use dma calls to setup mdma xtfers? I dont think that is a good idea. How do you know you should use mdma for subsequent transfer? > >> drivers/dma/stm32-dma.c | 879 ++++++++++++++++++++++++++++++++++++++++++------ > > > > that is a lot of change for a driver, consider splitting it up > > logically in smaller changes... > > > > This feature is rather monolithic. Difficult to split up. > All the code is required at once. It can be enabled at last but split up logically. Intrusive changes to a driver make it hard to review.. -- ~Vinod From mboxrd@z Thu Jan 1 00:00:00 1970 From: Vinod Subject: Re: [PATCH v3 4/7] dmaengine: stm32-dma: Add DMA/MDMA chaining support Date: Wed, 10 Oct 2018 09:33:43 +0530 Message-ID: <20181010040343.GO2372@vkoul-mobl> References: <1538139715-24406-1-git-send-email-pierre-yves.mordret@st.com> <1538139715-24406-5-git-send-email-pierre-yves.mordret@st.com> <20181007160030.GB2372@vkoul-mobl> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: Sender: linux-kernel-owner@vger.kernel.org To: Pierre Yves MORDRET Cc: Rob Herring , Mark Rutland , Alexandre Torgue , Maxime Coquelin , Dan Williams , devicetree@vger.kernel.org, dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org List-Id: devicetree@vger.kernel.org On 09-10-18, 10:40, Pierre Yves MORDRET wrote: > > > On 10/07/2018 06:00 PM, Vinod wrote: > > On 28-09-18, 15:01, Pierre-Yves MORDRET wrote: > >> This patch adds support of DMA/MDMA chaining support. > >> It introduces an intermediate transfer between peripherals and STM32 DMA. > >> This intermediate transfer is triggered by SW for single M2D transfer and > >> by STM32 DMA IP for all other modes (sg, cyclic) and direction (D2M). > >> > >> A generic SRAM allocator is used for this intermediate buffer > >> Each DMA channel will be able to define its SRAM needs to achieve chaining > >> feature : (2 ^ order) * PAGE_SIZE. > >> For cyclic, SRAM buffer is derived from period length (rounded on > >> PAGE_SIZE). > > > > So IIUC, you chain two dma txns together and transfer data via an SRAM? > > Correct. one DMA is DMAv2 (stm32-dma) and the other is MDMA(stm32-mdma). > Intermediate transfer is between device and memory. > This intermediate transfer is using SDRAM. Ah so you use dma calls to setup mdma xtfers? I dont think that is a good idea. How do you know you should use mdma for subsequent transfer? > >> drivers/dma/stm32-dma.c | 879 ++++++++++++++++++++++++++++++++++++++++++------ > > > > that is a lot of change for a driver, consider splitting it up > > logically in smaller changes... > > > > This feature is rather monolithic. Difficult to split up. > All the code is required at once. It can be enabled at last but split up logically. Intrusive changes to a driver make it hard to review.. -- ~Vinod