From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: Mahesh Kumar <mahesh1.kumar@intel.com>
Cc: intel-gfx@lists.freedesktop.org,
Lucas De Marchi <lucas.demarchi@intel.com>
Subject: Re: [PATCH 6/8] drm/i915/icl: Combine all port/combophy macros at one place
Date: Fri, 12 Oct 2018 15:09:24 -0700 [thread overview]
Message-ID: <20181012220924.GT10727@intel.com> (raw)
In-Reply-To: <20181003072203.12848-7-mahesh1.kumar@intel.com>
On Wed, Oct 03, 2018 at 12:52:01PM +0530, Mahesh Kumar wrote:
> This patch combines CNL/ICL specific port/combophy macros together
> at one location. This is prework for patches later in series where
> new macros to find port/combophy register will be introduced.
>
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 138 +++++++++++++++++++++-------------------
> 1 file changed, 73 insertions(+), 65 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 27e650fe591b..e3ac65f5aa81 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1631,14 +1631,42 @@ enum i915_power_well_id {
> #define PHY_RESERVED (1 << 7)
> #define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC)
>
> -#define CNL_PORT_CL1CM_DW5 _MMIO(0x162014)
> -#define CL_POWER_DOWN_ENABLE (1 << 4)
> -#define SUS_CLOCK_CONFIG (3 << 0)
> +#define _PORT_CL1CM_DW9_A 0x162024
> +#define _PORT_CL1CM_DW9_BC 0x6C024
> +#define IREF0RC_OFFSET_SHIFT 8
> +#define IREF0RC_OFFSET_MASK (0xFF << IREF0RC_OFFSET_SHIFT)
> +#define BXT_PORT_CL1CM_DW9(phy) _BXT_PHY((phy), _PORT_CL1CM_DW9_BC)
> +
> +#define _PORT_CL1CM_DW10_A 0x162028
> +#define _PORT_CL1CM_DW10_BC 0x6C028
> +#define IREF1RC_OFFSET_SHIFT 8
> +#define IREF1RC_OFFSET_MASK (0xFF << IREF1RC_OFFSET_SHIFT)
> +#define BXT_PORT_CL1CM_DW10(phy) _BXT_PHY((phy), _PORT_CL1CM_DW10_BC)
> +
> +#define _PORT_CL1CM_DW28_A 0x162070
> +#define _PORT_CL1CM_DW28_BC 0x6C070
> +#define OCL1_POWER_DOWN_EN (1 << 23)
> +#define DW28_OLDO_DYN_PWR_DOWN_EN (1 << 22)
> +#define SUS_CLK_CONFIG 0x3
> +#define BXT_PORT_CL1CM_DW28(phy) _BXT_PHY((phy), _PORT_CL1CM_DW28_BC)
> +
> +#define _PORT_CL1CM_DW30_A 0x162078
> +#define _PORT_CL1CM_DW30_BC 0x6C078
> +#define OCL2_LDOFUSE_PWR_DIS (1 << 6)
> +#define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC)
> +
> +/*
> + * CNL/ICL Port/COMBO-PHY Registers
> + */
> +/* CNL/ICL Port CL_DW registers */
> +#define CNL_PORT_CL1CM_DW5 _MMIO(0x162014)
>
We need to remove this empty line here or it seems the bits for this reg is not
defined.
The rest looks good to me,
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> #define _ICL_PORT_CL_DW5_A 0x162014
> #define _ICL_PORT_CL_DW5_B 0x6C014
> #define ICL_PORT_CL_DW5(port) _MMIO_PORT(port, _ICL_PORT_CL_DW5_A, \
> _ICL_PORT_CL_DW5_B)
> +#define CL_POWER_DOWN_ENABLE (1 << 4)
> +#define SUS_CLOCK_CONFIG (3 << 0)
>
> #define _CNL_PORT_CL_DW10_A 0x162028
> #define _ICL_PORT_CL_DW10_B 0x6c028
> @@ -1660,18 +1688,6 @@ enum i915_power_well_id {
> #define PWR_DOWN_LN_MASK (0xf << 4)
> #define PWR_DOWN_LN_SHIFT 4
>
> -#define _PORT_CL1CM_DW9_A 0x162024
> -#define _PORT_CL1CM_DW9_BC 0x6C024
> -#define IREF0RC_OFFSET_SHIFT 8
> -#define IREF0RC_OFFSET_MASK (0xFF << IREF0RC_OFFSET_SHIFT)
> -#define BXT_PORT_CL1CM_DW9(phy) _BXT_PHY((phy), _PORT_CL1CM_DW9_BC)
> -
> -#define _PORT_CL1CM_DW10_A 0x162028
> -#define _PORT_CL1CM_DW10_BC 0x6C028
> -#define IREF1RC_OFFSET_SHIFT 8
> -#define IREF1RC_OFFSET_MASK (0xFF << IREF1RC_OFFSET_SHIFT)
> -#define BXT_PORT_CL1CM_DW10(phy) _BXT_PHY((phy), _PORT_CL1CM_DW10_BC)
> -
> #define _ICL_PORT_CL_DW12_A 0x162030
> #define _ICL_PORT_CL_DW12_B 0x6C030
> #define ICL_LANE_ENABLE_AUX (1 << 0)
> @@ -1679,18 +1695,49 @@ enum i915_power_well_id {
> _ICL_PORT_CL_DW12_A, \
> _ICL_PORT_CL_DW12_B)
>
> -#define _PORT_CL1CM_DW28_A 0x162070
> -#define _PORT_CL1CM_DW28_BC 0x6C070
> -#define OCL1_POWER_DOWN_EN (1 << 23)
> -#define DW28_OLDO_DYN_PWR_DOWN_EN (1 << 22)
> -#define SUS_CLK_CONFIG 0x3
> -#define BXT_PORT_CL1CM_DW28(phy) _BXT_PHY((phy), _PORT_CL1CM_DW28_BC)
> +/* CNL/ICL Port COMP_DW registers */
> +#define CNL_PORT_COMP_DW0 _MMIO(0x162100)
> +#define _ICL_PORT_COMP_DW0_A 0x162100
> +#define _ICL_PORT_COMP_DW0_B 0x6C100
> +#define ICL_PORT_COMP_DW0(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW0_A, \
> + _ICL_PORT_COMP_DW0_B)
> +#define COMP_INIT (1 << 31)
>
> -#define _PORT_CL1CM_DW30_A 0x162078
> -#define _PORT_CL1CM_DW30_BC 0x6C078
> -#define OCL2_LDOFUSE_PWR_DIS (1 << 6)
> -#define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC)
> +#define CNL_PORT_COMP_DW1 _MMIO(0x162104)
> +#define _ICL_PORT_COMP_DW1_A 0x162104
> +#define _ICL_PORT_COMP_DW1_B 0x6C104
> +#define ICL_PORT_COMP_DW1(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW1_A, \
> + _ICL_PORT_COMP_DW1_B)
> +#define CNL_PORT_COMP_DW3 _MMIO(0x16210c)
> +#define _ICL_PORT_COMP_DW3_A 0x16210C
> +#define _ICL_PORT_COMP_DW3_B 0x6C10C
> +#define ICL_PORT_COMP_DW3(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW3_A, \
> + _ICL_PORT_COMP_DW3_B)
> +#define PROCESS_INFO_DOT_0 (0 << 26)
> +#define PROCESS_INFO_DOT_1 (1 << 26)
> +#define PROCESS_INFO_DOT_4 (2 << 26)
> +#define PROCESS_INFO_MASK (7 << 26)
> +#define PROCESS_INFO_SHIFT 26
> +#define VOLTAGE_INFO_0_85V (0 << 24)
> +#define VOLTAGE_INFO_0_95V (1 << 24)
> +#define VOLTAGE_INFO_1_05V (2 << 24)
> +#define VOLTAGE_INFO_MASK (3 << 24)
> +#define VOLTAGE_INFO_SHIFT 24
>
> +#define CNL_PORT_COMP_DW9 _MMIO(0x162124)
> +#define _ICL_PORT_COMP_DW9_A 0x162124
> +#define _ICL_PORT_COMP_DW9_B 0x6C124
> +#define ICL_PORT_COMP_DW9(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW9_A, \
> + _ICL_PORT_COMP_DW9_B)
> +
> +#define CNL_PORT_COMP_DW10 _MMIO(0x162128)
> +#define _ICL_PORT_COMP_DW10_A 0x162128
> +#define _ICL_PORT_COMP_DW10_B 0x6C128
> +#define ICL_PORT_COMP_DW10(port) _MMIO_PORT(port, \
> + _ICL_PORT_COMP_DW10_A, \
> + _ICL_PORT_COMP_DW10_B)
> +
> +/* CNL/ICL Port PCS registers */
> #define _CNL_PORT_PCS_DW1_GRP_AE 0x162304
> #define _CNL_PORT_PCS_DW1_GRP_B 0x162384
> #define _CNL_PORT_PCS_DW1_GRP_C 0x162B04
> @@ -1734,7 +1781,7 @@ enum i915_power_well_id {
> _ICL_PORT_PCS_DW1_AUX_B)
> #define COMMON_KEEPER_EN (1 << 26)
>
> -/* CNL Port TX registers */
> +/* CNL/ICL Port TX registers */
> #define _CNL_PORT_TX_AE_GRP_OFFSET 0x162340
> #define _CNL_PORT_TX_B_GRP_OFFSET 0x1623C0
> #define _CNL_PORT_TX_C_GRP_OFFSET 0x162B40
> @@ -2054,45 +2101,6 @@ enum i915_power_well_id {
> #define BXT_PORT_CL2CM_DW6(phy) _BXT_PHY((phy), _PORT_CL2CM_DW6_BC)
> #define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28)
>
> -#define CNL_PORT_COMP_DW0 _MMIO(0x162100)
> -#define COMP_INIT (1 << 31)
> -#define CNL_PORT_COMP_DW1 _MMIO(0x162104)
> -#define CNL_PORT_COMP_DW3 _MMIO(0x16210c)
> -#define PROCESS_INFO_DOT_0 (0 << 26)
> -#define PROCESS_INFO_DOT_1 (1 << 26)
> -#define PROCESS_INFO_DOT_4 (2 << 26)
> -#define PROCESS_INFO_MASK (7 << 26)
> -#define PROCESS_INFO_SHIFT 26
> -#define VOLTAGE_INFO_0_85V (0 << 24)
> -#define VOLTAGE_INFO_0_95V (1 << 24)
> -#define VOLTAGE_INFO_1_05V (2 << 24)
> -#define VOLTAGE_INFO_MASK (3 << 24)
> -#define VOLTAGE_INFO_SHIFT 24
> -#define CNL_PORT_COMP_DW9 _MMIO(0x162124)
> -#define CNL_PORT_COMP_DW10 _MMIO(0x162128)
> -
> -#define _ICL_PORT_COMP_DW0_A 0x162100
> -#define _ICL_PORT_COMP_DW0_B 0x6C100
> -#define ICL_PORT_COMP_DW0(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW0_A, \
> - _ICL_PORT_COMP_DW0_B)
> -#define _ICL_PORT_COMP_DW1_A 0x162104
> -#define _ICL_PORT_COMP_DW1_B 0x6C104
> -#define ICL_PORT_COMP_DW1(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW1_A, \
> - _ICL_PORT_COMP_DW1_B)
> -#define _ICL_PORT_COMP_DW3_A 0x16210C
> -#define _ICL_PORT_COMP_DW3_B 0x6C10C
> -#define ICL_PORT_COMP_DW3(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW3_A, \
> - _ICL_PORT_COMP_DW3_B)
> -#define _ICL_PORT_COMP_DW9_A 0x162124
> -#define _ICL_PORT_COMP_DW9_B 0x6C124
> -#define ICL_PORT_COMP_DW9(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW9_A, \
> - _ICL_PORT_COMP_DW9_B)
> -#define _ICL_PORT_COMP_DW10_A 0x162128
> -#define _ICL_PORT_COMP_DW10_B 0x6C128
> -#define ICL_PORT_COMP_DW10(port) _MMIO_PORT(port, \
> - _ICL_PORT_COMP_DW10_A, \
> - _ICL_PORT_COMP_DW10_B)
> -
> /* ICL PHY DFLEX registers */
> #define PORT_TX_DFLEXDPMLE1 _MMIO(0x1638C0)
> #define DFLEXDPMLE1_DPMLETC_MASK(n) (0xf << (4 * (n)))
> --
> 2.16.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2018-10-12 22:09 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-03 7:21 [PATCH 0/8] Refactor and Add helper function for combophy/tc ports Mahesh Kumar
2018-10-03 7:21 ` [PATCH 1/8] drm/i915/icl: create function to identify combophy port Mahesh Kumar
2018-10-03 17:57 ` Rodrigo Vivi
2018-10-03 18:03 ` Lucas De Marchi
2018-10-04 8:50 ` [PATCH v2 " Mahesh Kumar
2018-10-04 20:00 ` Lucas De Marchi
2018-10-15 21:58 ` [PATCH " Manasi Navare
2018-10-03 7:21 ` [PATCH 2/8] drm/i915/icl: use combophy/TC helper functions during display detection Mahesh Kumar
2018-10-03 17:58 ` Rodrigo Vivi
2018-10-04 21:16 ` Lucas De Marchi
2018-10-03 7:21 ` [PATCH 3/8] drm/i915/icl: Refactor get_ddi_pll using helper func Mahesh Kumar
2018-10-04 21:18 ` Lucas De Marchi
2018-10-03 7:21 ` [PATCH 4/8] drm/i915/icl: Use helper functions to classify the ports Mahesh Kumar
2018-10-03 17:59 ` Rodrigo Vivi
2018-10-04 21:21 ` Lucas De Marchi
2018-10-03 7:22 ` [PATCH 5/8] drm/i915/icl: Refactor icl pll functions Mahesh Kumar
2018-10-04 21:24 ` Lucas De Marchi
2018-10-03 7:22 ` [PATCH 6/8] drm/i915/icl: Combine all port/combophy macros at one place Mahesh Kumar
2018-10-12 22:09 ` Rodrigo Vivi [this message]
2018-10-12 23:47 ` [PATCH v2] " Lucas De Marchi
2018-10-03 7:22 ` [PATCH 7/8] drm/i915/icl: Introduce new macros to get combophy registers Mahesh Kumar
2018-10-12 22:25 ` Rodrigo Vivi
2018-10-12 22:58 ` Lucas De Marchi
2018-10-15 16:29 ` Rodrigo Vivi
2018-10-16 2:35 ` [PATCH v2] " Lucas De Marchi
2018-10-16 16:04 ` Rodrigo Vivi
2018-10-03 7:22 ` [PATCH 8/8] drm/i915/icl: Fix DDI/TC port clk_off bits Mahesh Kumar
2018-10-04 21:26 ` Lucas De Marchi
2018-10-16 2:37 ` [PATCH v2] " Lucas De Marchi
2018-10-03 7:35 ` ✗ Fi.CI.CHECKPATCH: warning for Refactor and Add helper function for combophy/tc ports Patchwork
2018-10-03 7:57 ` ✗ Fi.CI.BAT: failure " Patchwork
2018-10-03 13:51 ` ✓ Fi.CI.BAT: success " Patchwork
2018-10-03 23:15 ` ✓ Fi.CI.IGT: " Patchwork
2018-10-04 9:56 ` ✗ Fi.CI.CHECKPATCH: warning for Refactor and Add helper function for combophy/tc ports (rev2) Patchwork
2018-10-04 10:16 ` ✓ Fi.CI.BAT: success " Patchwork
2018-10-04 10:38 ` Patchwork
2018-10-04 16:36 ` ✓ Fi.CI.IGT: " Patchwork
2018-10-04 17:12 ` Patchwork
2018-10-12 23:57 ` ✗ Fi.CI.BAT: failure for Refactor and Add helper function for combophy/tc ports (rev3) Patchwork
2018-10-16 2:57 ` ✗ Fi.CI.CHECKPATCH: warning for Refactor and Add helper function for combophy/tc ports (rev5) Patchwork
2018-10-16 3:28 ` ✓ Fi.CI.BAT: success " Patchwork
2018-10-16 4:22 ` ✓ Fi.CI.IGT: " Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20181012220924.GT10727@intel.com \
--to=rodrigo.vivi@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=lucas.demarchi@intel.com \
--cc=mahesh1.kumar@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.