diff for duplicates of <20181018202457.GA25174@bogus> diff --git a/a/1.txt b/N1/1.txt index a52fef7..0e8ef1d 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -5,7 +5,7 @@ On Thu, Oct 18, 2018 at 06:19:39PM +0000, A.s. Dong wrote: > > Cc: Rob Herring <robh+dt@kernel.org> > Cc: Mark Rutland <mark.rutland@arm.com> -> Cc: devicetree at vger.kernel.org +> Cc: devicetree@vger.kernel.org > Cc: Shawn Guo <shawnguo@kernel.org> > Cc: Sascha Hauer <kernel@pengutronix.de> > Cc: Fabio Estevam <fabio.estevam@nxp.com> @@ -70,7 +70,7 @@ On Thu, Oct 18, 2018 at 06:19:39PM +0000, A.s. Dong wrote: > + #size-cells = <0>; > + > + /* We have 1 clusters with 4 Cortex-A35 cores */ -> + A35_0: cpu at 0 { +> + A35_0: cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a35"; > + reg = <0x0 0x0>; @@ -78,7 +78,7 @@ On Thu, Oct 18, 2018 at 06:19:39PM +0000, A.s. Dong wrote: > + next-level-cache = <&A35_L2>; > + }; > + -> + A35_1: cpu at 1 { +> + A35_1: cpu@1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a35"; > + reg = <0x0 0x1>; @@ -86,7 +86,7 @@ On Thu, Oct 18, 2018 at 06:19:39PM +0000, A.s. Dong wrote: > + next-level-cache = <&A35_L2>; > + }; > + -> + A35_2: cpu at 2 { +> + A35_2: cpu@2 { > + device_type = "cpu"; > + compatible = "arm,cortex-a35"; > + reg = <0x0 0x2>; @@ -94,7 +94,7 @@ On Thu, Oct 18, 2018 at 06:19:39PM +0000, A.s. Dong wrote: > + next-level-cache = <&A35_L2>; > + }; > + -> + A35_3: cpu at 3 { +> + A35_3: cpu@3 { > + device_type = "cpu"; > + compatible = "arm,cortex-a35"; > + reg = <0x0 0x3>; @@ -148,7 +148,7 @@ On Thu, Oct 18, 2018 at 06:19:39PM +0000, A.s. Dong wrote: > + mmc2 = &usdhc3; > + }; > + -> + gic: interrupt-controller at 51a00000 { +> + gic: interrupt-controller@51a00000 { > + compatible = "arm,gic-v3"; > + reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ > + <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ @@ -213,7 +213,7 @@ On Thu, Oct 18, 2018 at 06:19:39PM +0000, A.s. Dong wrote: > + #address-cells = <1>; > + #size-cells = <0>; > + -> + pd_lsio_pwm0: lsio-pwm0 at bf { +> + pd_lsio_pwm0: lsio-pwm0@bf { > + reg = <0xbf>; > + #power-domain-cells = <0>; > + power-domains = <&pd_lsio>; @@ -228,139 +228,139 @@ cell the device ID. > + }; > + -> + pd_lsio_pwm1: lsio-pwm1 at c0 { +> + pd_lsio_pwm1: lsio-pwm1@c0 { > + reg = <0xc0>; > + #power-domain-cells = <0>; > + power-domains = <&pd_lsio>; > + }; > + -> + pd_lsio_pwm2: lsio-pwm2 at c1 { +> + pd_lsio_pwm2: lsio-pwm2@c1 { > + reg = <0xc1>; > + #power-domain-cells = <0>; > + power-domains = <&pd_lsio>; > + }; > + -> + pd_lsio_pwm3: lsio-pwm3 at c2 { +> + pd_lsio_pwm3: lsio-pwm3@c2 { > + reg = <0xc2>; > + #power-domain-cells = <0>; > + power-domains = <&pd_lsio>; > + }; > + -> + pd_lsio_pwm4: lsio-pwm4 at c3 { +> + pd_lsio_pwm4: lsio-pwm4@c3 { > + reg = <0xc3>; > + #power-domain-cells = <0>; > + power-domains = <&pd_lsio>; > + }; > + -> + pd_lsio_pwm5: lsio-pwm5 at c4 { +> + pd_lsio_pwm5: lsio-pwm5@c4 { > + reg = <0xc4>; > + #power-domain-cells = <0>; > + power-domains = <&pd_lsio>; > + }; > + -> + pd_lsio_pwm6: lsio-pwm6 at c5 { +> + pd_lsio_pwm6: lsio-pwm6@c5 { > + reg = <0xc5>; > + #power-domain-cells = <0>; > + power-domains = <&pd_lsio>; > + }; > + -> + pd_lsio_pwm7: lsio-pwm7 at c6 { +> + pd_lsio_pwm7: lsio-pwm7@c6 { > + reg = <0xc6>; > + #power-domain-cells = <0>; > + power-domains = <&pd_lsio>; > + }; > + -> + pd_lsio_gpio0: lsio-gpio0 at c7 { +> + pd_lsio_gpio0: lsio-gpio0@c7 { > + reg = <0xc7>; > + #power-domain-cells = <0>; > + power-domains = <&pd_lsio>; > + }; > + -> + pd_lsio_gpio1: lsio-gpio1 at c8 { +> + pd_lsio_gpio1: lsio-gpio1@c8 { > + reg = <0xc8>; > + #power-domain-cells = <0>; > + power-domains = <&pd_lsio>; > + }; > + -> + pd_lsio_gpio2: lsio-gpio2 at c9 { +> + pd_lsio_gpio2: lsio-gpio2@c9 { > + reg = <0xc9>; > + #power-domain-cells = <0>; > + power-domains = <&pd_lsio>; > + }; > + -> + pd_lsio_gpio3: lsio-gpio3 at ca { +> + pd_lsio_gpio3: lsio-gpio3@ca { > + reg = <0xca>; > + #power-domain-cells = <0>; > + power-domains = <&pd_lsio>; > + }; > + -> + pd_lsio_gpio4: lsio-gpio4 at cb { +> + pd_lsio_gpio4: lsio-gpio4@cb { > + reg = <0xcb>; > + #power-domain-cells = <0>; > + power-domains = <&pd_lsio>; > + }; > + -> + pd_lsio_gpio5: lsio-gpio5 at cc { +> + pd_lsio_gpio5: lsio-gpio5@cc { > + reg = <0xcc>; > + #power-domain-cells = <0>; > + power-domains = <&pd_lsio>; > + }; > + -> + pd_lsio_gpio6: lsio-gpio6 at cd { +> + pd_lsio_gpio6: lsio-gpio6@cd { > + reg = <0xcd>; > + #power-domain-cells = <0>; > + power-domains = <&pd_lsio>; > + }; > + -> + pd_lsio_gpio7: lsio-gpio7 at ce { +> + pd_lsio_gpio7: lsio-gpio7@ce { > + reg = <0xce>; > + #power-domain-cells = <0>; > + power-domains = <&pd_lsio>; > + }; > + -> + pd_lsio_gpt0: lsio-gpt0 at cf { +> + pd_lsio_gpt0: lsio-gpt0@cf { > + reg = <0xcf>; > + #power-domain-cells = <0>; > + power-domains = <&pd_lsio>; > + }; > + -> + pd_lsio_gpt1: lsio-gpt1 at d0 { +> + pd_lsio_gpt1: lsio-gpt1@d0 { > + reg = <0xd0>; > + #power-domain-cells = <0>; > + power-domains = <&pd_lsio>; > + }; > + -> + pd_lsio_gpt2: lsio-gpt2 at d1 { +> + pd_lsio_gpt2: lsio-gpt2@d1 { > + reg = <0xd1>; > + #power-domain-cells = <0>; > + power-domains = <&pd_lsio>; > + }; > + -> + pd_lsio_gpt3: lsio-gpt3 at d2 { +> + pd_lsio_gpt3: lsio-gpt3@d2 { > + reg = <0xd2>; > + #power-domain-cells = <0>; > + power-domains = <&pd_lsio>; > + }; > + -> + pd_lsio_gpt4: lsio-gpt4 at d3 { +> + pd_lsio_gpt4: lsio-gpt4@d3 { > + reg = <0xd3>; > + #power-domain-cells = <0>; > + power-domains = <&pd_lsio>; > + }; > + -> + pd_lsio_kpp: lsio-kpp at d4 { +> + pd_lsio_kpp: lsio-kpp@d4 { > + reg = <0xd4>; > + #power-domain-cells = <0>; > + power-domains = <&pd_lsio>; > + }; > + -> + pd_lsio_flexspi0: lsio-fspi0 at ed { +> + pd_lsio_flexspi0: lsio-fspi0@ed { > + reg = <0xed>; > + #power-domain-cells = <0>; > + power-domains = <&pd_lsio>; > + }; > + -> + pd_lsio_flexspi1: lsio-fspi1 at ee { +> + pd_lsio_flexspi1: lsio-fspi1@ee { > + reg = <0xee>; > + #power-domain-cells = <0>; > + power-domains = <&pd_lsio>; @@ -372,103 +372,103 @@ cell the device ID. > + #address-cells = <1>; > + #size-cells = <0>; > + -> + pd_conn_sdhc0: conn-sdhc0 at f8 { +> + pd_conn_sdhc0: conn-sdhc0@f8 { > + reg = <0xf8>; > + #power-domain-cells = <0>; > + power-domains = <&pd_conn>; > + }; > + -> + pd_conn_sdhc1: conn-sdhc1 at f9 { +> + pd_conn_sdhc1: conn-sdhc1@f9 { > + reg = <0xf9>; > + #power-domain-cells = <0>; > + power-domains = <&pd_conn>; > + }; > + -> + pd_conn_sdhc2: conn-sdhc2 at fa { +> + pd_conn_sdhc2: conn-sdhc2@fa { > + reg = <0xfa>; > + #power-domain-cells = <0>; > + power-domains = <&pd_conn>; > + }; > + -> + pd_conn_enet0: conn-enet0 at fb { +> + pd_conn_enet0: conn-enet0@fb { > + reg = <0xfb>; > + #power-domain-cells = <0>; > + power-domains = <&pd_conn>; > + }; > + -> + pd_conn_enet1: conn-enet1 at fc { +> + pd_conn_enet1: conn-enet1@fc { > + reg = <0xfc>; > + #power-domain-cells = <0>; > + power-domains = <&pd_conn>; > + }; > + -> + pd_conn_mlb0: conn-mlb0 at fd { +> + pd_conn_mlb0: conn-mlb0@fd { > + reg = <0xfd>; > + #power-domain-cells = <0>; > + power-domains = <&pd_conn>; > + }; > + -> + pd_conn_usbotg0: conn-usb0 at 103 { +> + pd_conn_usbotg0: conn-usb0@103 { > + reg = <0x103>; > + #power-domain-cells = <0>; > + power-domains = <&pd_conn>; > + }; > + -> + pd_conn_usbotg1: conn-usb1 at 104 { +> + pd_conn_usbotg1: conn-usb1@104 { > + reg = <0x104>; > + #power-domain-cells = <0>; > + power-domains = <&pd_conn>; > + }; > + -> + pd_conn_usbotg0_phy: conn-usb0-phy at 105 { +> + pd_conn_usbotg0_phy: conn-usb0-phy@105 { > + reg = <0x105>; > + #power-domain-cells = <0>; > + power-domains = <&pd_conn>; > + }; > + -> + pd_conn_usb2: conn-usb2 at 106 { +> + pd_conn_usb2: conn-usb2@106 { > + reg = <0x106>; > + #power-domain-cells = <0>; > + power-domains = <&pd_conn>; > + }; > + -> + pd_conn_usb2_phy: conn-usb2-phy at 107 { +> + pd_conn_usb2_phy: conn-usb2-phy@107 { > + reg = <0x107>; > + #power-domain-cells = <0>; > + power-domains = <&pd_conn>; > + }; > + -> + pd_conn_nand: conn-nand at 109 { +> + pd_conn_nand: conn-nand@109 { > + reg = <0x109>; > + #power-domain-cells = <0>; > + power-domains = <&pd_conn>; > + }; > + -> + pd_conn_edma_ch0: conn-dma4-ch0 at 174 { +> + pd_conn_edma_ch0: conn-dma4-ch0@174 { > + reg = <0x174>; > + #power-domain-cells = <0>; > + power-domains =<&pd_conn>; > + }; > + -> + pd_conn_edma_ch1: conn-dma4-ch1 at 175 { +> + pd_conn_edma_ch1: conn-dma4-ch1@175 { > + reg = <0x175>; > + #power-domain-cells = <0>; > + power-domains =<&pd_conn>; > + }; > + -> + pd_conn_edma_ch2: conn-dma4-ch2 at 176 { +> + pd_conn_edma_ch2: conn-dma4-ch2@176 { > + reg = <0x176>; > + #power-domain-cells = <0>; > + power-domains =<&pd_conn>; > + }; > + -> + pd_conn_edma_ch3: conn-dma4-ch3 at 177 { +> + pd_conn_edma_ch3: conn-dma4-ch3@177 { > + reg = <0x177>; > + #power-domain-cells = <0>; > + power-domains =<&pd_conn>; > + }; > + -> + pd_conn_edma_ch4: conn-dma4-ch4 at 178 { +> + pd_conn_edma_ch4: conn-dma4-ch4@178 { > + reg = <0x178>; > + #power-domain-cells = <0>; > + power-domains =<&pd_conn>; @@ -480,121 +480,121 @@ cell the device ID. > + #address-cells = <1>; > + #size-cells = <0>; > + -> + pd_dma_lpspi0: dma-spi0 at 35 { +> + pd_dma_lpspi0: dma-spi0@35 { > + reg = <0x35>; > + #power-domain-cells = <0>; > + power-domains = <&pd_dma>; > + }; > + -> + pd_dma_lpspi1: dma-spi1 at 36 { +> + pd_dma_lpspi1: dma-spi1@36 { > + reg = <0x36>; > + #power-domain-cells = <0>; > + power-domains = <&pd_dma>; > + }; > + -> + pd_dma_lpspi2: dma-spi2 at 37 { +> + pd_dma_lpspi2: dma-spi2@37 { > + reg = <0x37>; > + #power-domain-cells = <0>; > + power-domains = <&pd_dma>; > + }; > + -> + pd_dma_lpspi3: dma-spi3 at 38 { +> + pd_dma_lpspi3: dma-spi3@38 { > + reg = <0x38>; > + #power-domain-cells = <0>; > + power-domains = <&pd_dma>; > + }; > + -> + pd_dma_lpuart0: dma-lpuart0 at 39 { +> + pd_dma_lpuart0: dma-lpuart0@39 { > + reg = <0x39>; > + #power-domain-cells = <0>; > + power-domains = <&pd_dma>; > + }; > + -> + pd_dma_lpuart1: dma-lpuart1 at 3a { +> + pd_dma_lpuart1: dma-lpuart1@3a { > + reg = <0x3a>; > + #power-domain-cells = <0>; > + power-domains = <&pd_dma>; > + }; > + -> + pd_dma_lpuart2: dma-lpuart2 at 3b { +> + pd_dma_lpuart2: dma-lpuart2@3b { > + reg = <0x3b>; > + #power-domain-cells = <0>; > + power-domains = <&pd_dma>; > + }; > + -> + pd_dma_lpuart3: dma-lpuart3 at 3c { +> + pd_dma_lpuart3: dma-lpuart3@3c { > + reg = <0x3c>; > + #power-domain-cells = <0>; > + power-domains = <&pd_dma>; > + }; > + -> + pd_dma_lpi2c0: dma-lpi2c0 at 60 { +> + pd_dma_lpi2c0: dma-lpi2c0@60 { > + reg = <0x60>; > + #power-domain-cells = <0>; > + power-domains = <&pd_dma>; > + }; > + -> + pd_dma_lpi2c1: dma-lpi2c1 at 61 { +> + pd_dma_lpi2c1: dma-lpi2c1@61 { > + reg = <0x61>; > + #power-domain-cells = <0>; > + power-domains = <&pd_dma>; > + }; > + -> + pd_dma_lpi2c2: dma-lpi2c2 at 62 { +> + pd_dma_lpi2c2: dma-lpi2c2@62 { > + reg = <0x62>; > + #power-domain-cells = <0>; > + power-domains = <&pd_dma>; > + }; > + -> + pd_dma_lpi2c3: dma-lpi2c3 at 63 { +> + pd_dma_lpi2c3: dma-lpi2c3@63 { > + reg = <0x63>; > + #power-domain-cells = <0>; > + power-domains = <&pd_dma>; > + }; > + -> + pd_dma_adc0: dma-adc0 at 65 { +> + pd_dma_adc0: dma-adc0@65 { > + reg = <0x65>; > + #power-domain-cells = <0>; > + power-domains = <&pd_dma>; > + }; > + -> + pd_dma_ftm0: dma-ftm0 at 67 { +> + pd_dma_ftm0: dma-ftm0@67 { > + reg = <0x67>; > + #power-domain-cells = <0>; > + power-domains = <&pd_dma>; > + }; > + -> + pd_dma_ftm1: dma-ftm1 at 68 { +> + pd_dma_ftm1: dma-ftm1@68 { > + reg = <0x68>; > + #power-domain-cells = <0>; > + power-domains = <&pd_dma>; > + }; > + -> + pd_dma_flexcan0: dma-flexcan0 at 69 { +> + pd_dma_flexcan0: dma-flexcan0@69 { > + reg = <0x69>; > + #power-domain-cells = <0>; > + power-domains = <&pd_dma>; > + }; > + -> + pd_dma_flexcan1: dma-flexcan1 at 6a { +> + pd_dma_flexcan1: dma-flexcan1@6a { > + reg = <0x6a>; > + #power-domain-cells = <0>; > + power-domains = <&pd_dma>; > + }; > + -> + pd_dma_flexcan2: dma-flexcan2 at 6b { +> + pd_dma_flexcan2: dma-flexcan2@6b { > + reg = <0x6b>; > + #power-domain-cells = <0>; > + power-domains = <&pd_dma>; > + }; > + -> + pd_dma_lcd0: dma-lcd0 at bb { +> + pd_dma_lcd0: dma-lcd0@bb { > + reg = <0xbb>; > + #power-domain-cells = <0>; > + power-domains = <&pd_dma>; > + }; > + -> + pd_dma_pwm0: dma-pwm0 at bc { +> + pd_dma_pwm0: dma-pwm0@bc { > + reg = <0xbc>; > + #power-domain-cells = <0>; > + power-domains = <&pd_dma>; @@ -606,7 +606,7 @@ cell the device ID. > + #address-cells = <1>; > + #size-cells = <0>; > + -> + pd_gpu0: gpu0 at 90 { +> + pd_gpu0: gpu0@90 { > + reg = <0x90>; > + #power-domain-cells = <0>; > + power-domains =<&pd_gpu>; @@ -615,13 +615,13 @@ cell the device ID. > + }; > + }; > + -> + pd_vpu: vpu-power-domain at 166 { +> + pd_vpu: vpu-power-domain@166 { > + reg = <0x166>; > + #power-domain-cells = <0>; > + #address-cells = <1>; > + #size-cells = <0>; > + -> + pd_vpu_core: vpu-core at 16f { +> + pd_vpu_core: vpu-core@16f { > + reg = <0x16f>; > + #power-domain-cells = <0>; > + power-domains =<&pd_vpu>; @@ -633,7 +633,7 @@ cell the device ID. > + #address-cells = <1>; > + #size-cells = <0>; > + -> + pd_pcie: hsio-pcie-pd at 98 { +> + pd_pcie: hsio-pcie-pd@98 { > + reg = <0x98>; > + #power-domain-cells = <0>; > + power-domains =<&pd_hsio>; @@ -645,47 +645,47 @@ cell the device ID. > + #address-cells = <1>; > + #size-cells = <0>; > + -> + pd_dc0: dc0-power-domain at 20 { +> + pd_dc0: dc0-power-domain@20 { > + reg = <0x20>; > + #power-domain-cells = <0>; > + power-domains =<&pd_dc>; > + }; > + }; > + -> + pd_mipi_dsi: mipi0-dsi-power-domain at 189 { +> + pd_mipi_dsi: mipi0-dsi-power-domain@189 { > + reg = <0x189>; > + #power-domain-cells = <0>; > + #address-cells = <1>; > + #size-cells = <0>; > + -> + pd_mipi_pwm0: mipi0-dsi-pwm0 at 18a { +> + pd_mipi_pwm0: mipi0-dsi-pwm0@18a { > + reg = <0x18a>; > + power-domains =<&pd_mipi_dsi>; > + }; > + -> + pd_mipi_dsi_i2c0: mipi0-dsi-i2c0 at 18b { +> + pd_mipi_dsi_i2c0: mipi0-dsi-i2c0@18b { > + reg = <0x18b>; > + power-domains =<&pd_mipi_dsi>; > + }; > + -> + pd_mipi_dsi_i2c1: mipi0-dsi-i2c1 at 18c { +> + pd_mipi_dsi_i2c1: mipi0-dsi-i2c1@18c { > + reg = <0x18c>; > + power-domains =<&pd_mipi_dsi>; > + }; > + }; > + -> + pd_mipi_csi: mipi-csi0-power-domain at 191 { +> + pd_mipi_csi: mipi-csi0-power-domain@191 { > + reg = <0x191>; > + #power-domain-cells = <0>; > + #address-cells = <1>; > + #size-cells = <0>; > + -> + pd_mipi_csi0_pwm0: mipi-csi0-pwm at 192 { +> + pd_mipi_csi0_pwm0: mipi-csi0-pwm@192 { > + reg = <0x192>; > + power-domains =<&pd_mipi_csi>; > + }; > + -> + pd_mipi_csi0_i2c0: mipi-csi0-i2c at 193 { +> + pd_mipi_csi0_i2c0: mipi-csi0-i2c@193 { > + reg = <0x193>; > + power-domains =<&pd_mipi_csi>; > + }; @@ -693,14 +693,14 @@ cell the device ID. > + }; > + }; > + -> + audio_subsys: bus at 59000000 { +> + audio_subsys: bus@59000000 { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x59000000 0x0 0x59000000 0x1000000>; > + }; > + -> + dma_subsys: bus at 5a000000 { +> + dma_subsys: bus@5a000000 { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; @@ -708,7 +708,7 @@ cell the device ID. Can't you do some actual translation here. > + -> + dma_lpuart0: serial at 5a060000 { +> + dma_lpuart0: serial@5a060000 { > + compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; > + reg = <0x5a060000 0x1000>; > + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; @@ -718,7 +718,7 @@ Can't you do some actual translation here. > + status = "disabled"; > + }; > + -> + dma_i2c0: i2c at 5a800000 { +> + dma_i2c0: i2c@5a800000 { > + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; > + reg = <0x5a800000 0x4000>; > + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; @@ -731,7 +731,7 @@ Can't you do some actual translation here. > + status = "disabled"; > + }; > + -> + dma_i2c1: i2c at 5a810000 { +> + dma_i2c1: i2c@5a810000 { > + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; > + reg = <0x5a810000 0x4000>; > + interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; @@ -743,7 +743,7 @@ Can't you do some actual translation here. > + status = "disabled"; > + }; > + -> + dma_i2c2: i2c at 5a820000 { +> + dma_i2c2: i2c@5a820000 { > + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; > + reg = <0x5a820000 0x4000>; > + interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; @@ -756,7 +756,7 @@ Can't you do some actual translation here. > + status = "disabled"; > + }; > + -> + dma_i2c3: i2c at 5a830000 { +> + dma_i2c3: i2c@5a830000 { > + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; > + reg = <0x5a830000 0x4000>; > + interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; @@ -770,13 +770,13 @@ Can't you do some actual translation here. > + }; > + }; > + -> + conn_subsys: bus at 5b000000 { +> + conn_subsys: bus@5b000000 { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x5b000000 0x0 0x5b000000 0x1000000>; > + -> + usdhc1: mmc at 5b010000 { +> + usdhc1: mmc@5b010000 { > + compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; @@ -791,7 +791,7 @@ Can't you do some actual translation here. > + status = "disabled"; > + }; > + -> + usdhc2: mmc at 5b020000 { +> + usdhc2: mmc@5b020000 { > + compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; @@ -808,7 +808,7 @@ Can't you do some actual translation here. > + status = "disabled"; > + }; > + -> + usdhc3: mmc at 5b030000 { +> + usdhc3: mmc@5b030000 { > + compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; @@ -823,7 +823,7 @@ Can't you do some actual translation here. > + status = "disabled"; > + }; > + -> + fec1: ethernet at 5b040000 { +> + fec1: ethernet@5b040000 { > + compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec"; > + reg = <0x5b040000 0x10000>; > + interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, @@ -841,7 +841,7 @@ Can't you do some actual translation here. > + status = "disabled"; > + }; > + -> + fec2: ethernet at 5b050000 { +> + fec2: ethernet@5b050000 { > + compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec"; > + reg = <0x5b050000 0x10000>; > + interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, @@ -860,24 +860,24 @@ Can't you do some actual translation here. > + }; > + }; > + -> + db_subsys: bus at 5c000000 { +> + db_subsys: bus@5c000000 { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x5c000000 0x0 0x5c000000 0x1000000>; > + -> + ddr_pmu0: pmu at 5c020000 { +> + ddr_pmu0: pmu@5c020000 { > + reg = <0x5c020000 0x10000>; > + }; > + }; > + -> + lsio_subsys: bus at 5d000000 { +> + lsio_subsys: bus@5d000000 { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x5d000000 0x0 0x5d000000 0x1000000>; > + -> + lsio_mu0: mailbox at 5d1b0000 { +> + lsio_mu0: mailbox@5d1b0000 { > + compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; > + reg = <0x5d1b0000 0x10000>; > + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; @@ -885,14 +885,14 @@ Can't you do some actual translation here. > + status = "disabled"; > + }; > + -> + lsio_mu1: mailbox at 5d1c0000 { +> + lsio_mu1: mailbox@5d1c0000 { > + compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; > + reg = <0x5d1c0000 0x10000>; > + interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; > + #mbox-cells = <2>; > + }; > + -> + lsio_mu3: mailbox at 5d1e0000 { +> + lsio_mu3: mailbox@5d1e0000 { > + compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; > + reg = <0x5d1e0000 0x10000>; > + interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; @@ -900,7 +900,7 @@ Can't you do some actual translation here. > + status = "disabled"; > + }; > + -> + lsio_mu4: mailbox at 5d1f0000 { +> + lsio_mu4: mailbox@5d1f0000 { > + compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; > + reg = <0x5d1f0000 0x10000>; > + interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; @@ -908,7 +908,7 @@ Can't you do some actual translation here. > + status = "disabled"; > + }; > + -> + lsio_gpio0: gpio at 5d080000 { +> + lsio_gpio0: gpio@5d080000 { > + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; > + reg = <0x5d080000 0x10000>; > + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; @@ -919,7 +919,7 @@ Can't you do some actual translation here. > + power-domains = <&pd_lsio_gpio0>; > + }; > + -> + lsio_gpio1: gpio at 5d090000 { +> + lsio_gpio1: gpio@5d090000 { > + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; > + reg = <0x5d090000 0x10000>; > + interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; @@ -930,7 +930,7 @@ Can't you do some actual translation here. > + power-domains = <&pd_lsio_gpio1>; > + }; > + -> + lsio_gpio2: gpio at 5d0a0000 { +> + lsio_gpio2: gpio@5d0a0000 { > + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; > + reg = <0x5d0a0000 0x10000>; > + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; @@ -941,7 +941,7 @@ Can't you do some actual translation here. > + power-domains = <&pd_lsio_gpio2>; > + }; > + -> + lsio_gpio3: gpio at 5d0b0000 { +> + lsio_gpio3: gpio@5d0b0000 { > + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; > + reg = <0x5d0b0000 0x10000>; > + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; @@ -952,7 +952,7 @@ Can't you do some actual translation here. > + power-domains = <&pd_lsio_gpio3>; > + }; > + -> + lsio_gpio4: gpio at 5d0c0000 { +> + lsio_gpio4: gpio@5d0c0000 { > + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; > + reg = <0x5d0c0000 0x10000>; > + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; @@ -963,7 +963,7 @@ Can't you do some actual translation here. > + power-domains = <&pd_lsio_gpio4>; > + }; > + -> + lsio_gpio5: gpio at 5d0d0000 { +> + lsio_gpio5: gpio@5d0d0000 { > + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; > + reg = <0x5d0d0000 0x10000>; > + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; @@ -974,7 +974,7 @@ Can't you do some actual translation here. > + power-domains = <&pd_lsio_gpio5>; > + }; > + -> + lsio_gpio6: gpio at 5d0e0000 { +> + lsio_gpio6: gpio@5d0e0000 { > + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; > + reg = <0x5d0e0000 0x10000>; > + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; @@ -985,7 +985,7 @@ Can't you do some actual translation here. > + power-domains = <&pd_lsio_gpio6>; > + }; > + -> + lsio_gpio7: gpio at 5d0f0000 { +> + lsio_gpio7: gpio@5d0f0000 { > + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; > + reg = <0x5d0f0000 0x10000>; > + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; @@ -997,7 +997,7 @@ Can't you do some actual translation here. > + }; > + }; > + -> + hsio_subsys: bus at 5f000000 { +> + hsio_subsys: bus@5f000000 { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; diff --git a/a/content_digest b/N1/content_digest index 412a393..129d2c1 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,9 +1,19 @@ "ref\01539886483-15775-1-git-send-email-aisheng.dong@nxp.com\0" "ref\01539886483-15775-7-git-send-email-aisheng.dong@nxp.com\0" - "From\0robh@kernel.org (Rob Herring)\0" - "Subject\0[PATCH V3 6/8] arm64: dts: imx: add imx8qxp support\0" + "From\0Rob Herring <robh@kernel.org>\0" + "Subject\0Re: [PATCH V3 6/8] arm64: dts: imx: add imx8qxp support\0" "Date\0Thu, 18 Oct 2018 15:24:57 -0500\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0A.s. Dong <aisheng.dong@nxp.com>\0" + "Cc\0Mark Rutland <mark.rutland@arm.com>" + devicetree@vger.kernel.org <devicetree@vger.kernel.org> + dongas86@gmail.com <dongas86@gmail.com> + catalin.marinas@arm.com <catalin.marinas@arm.com> + will.deacon@arm.com <will.deacon@arm.com> + dl-linux-imx <linux-imx@nxp.com> + kernel@pengutronix.de <kernel@pengutronix.de> + Fabio Estevam <fabio.estevam@nxp.com> + shawnguo@kernel.org <shawnguo@kernel.org> + " linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org>\0" "\00:1\0" "b\0" "On Thu, Oct 18, 2018 at 06:19:39PM +0000, A.s. Dong wrote:\n" @@ -13,7 +23,7 @@ "> \n" "> Cc: Rob Herring <robh+dt@kernel.org>\n" "> Cc: Mark Rutland <mark.rutland@arm.com>\n" - "> Cc: devicetree at vger.kernel.org\n" + "> Cc: devicetree@vger.kernel.org\n" "> Cc: Shawn Guo <shawnguo@kernel.org>\n" "> Cc: Sascha Hauer <kernel@pengutronix.de>\n" "> Cc: Fabio Estevam <fabio.estevam@nxp.com>\n" @@ -78,7 +88,7 @@ "> +\t\t#size-cells = <0>;\n" "> +\n" "> +\t\t/* We have 1 clusters with 4 Cortex-A35 cores */\n" - "> +\t\tA35_0: cpu at 0 {\n" + "> +\t\tA35_0: cpu@0 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a35\";\n" "> +\t\t\treg = <0x0 0x0>;\n" @@ -86,7 +96,7 @@ "> +\t\t\tnext-level-cache = <&A35_L2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tA35_1: cpu at 1 {\n" + "> +\t\tA35_1: cpu@1 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a35\";\n" "> +\t\t\treg = <0x0 0x1>;\n" @@ -94,7 +104,7 @@ "> +\t\t\tnext-level-cache = <&A35_L2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tA35_2: cpu at 2 {\n" + "> +\t\tA35_2: cpu@2 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a35\";\n" "> +\t\t\treg = <0x0 0x2>;\n" @@ -102,7 +112,7 @@ "> +\t\t\tnext-level-cache = <&A35_L2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tA35_3: cpu at 3 {\n" + "> +\t\tA35_3: cpu@3 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a35\";\n" "> +\t\t\treg = <0x0 0x3>;\n" @@ -156,7 +166,7 @@ "> +\t\tmmc2 = &usdhc3;\n" "> +\t};\n" "> +\n" - "> +\tgic: interrupt-controller at 51a00000 {\n" + "> +\tgic: interrupt-controller@51a00000 {\n" "> +\t\tcompatible = \"arm,gic-v3\";\n" "> +\t\treg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */\n" "> +\t\t <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */\n" @@ -221,7 +231,7 @@ "> +\t\t\t\t#address-cells = <1>;\n" "> +\t\t\t\t#size-cells = <0>;\n" "> +\n" - "> +\t\t\t\tpd_lsio_pwm0: lsio-pwm0 at bf {\n" + "> +\t\t\t\tpd_lsio_pwm0: lsio-pwm0@bf {\n" "> +\t\t\t\t\treg = <0xbf>;\n" "> +\t\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t\tpower-domains = <&pd_lsio>;\n" @@ -236,139 +246,139 @@ "\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tpd_lsio_pwm1: lsio-pwm1 at c0 {\n" + "> +\t\t\t\tpd_lsio_pwm1: lsio-pwm1@c0 {\n" "> +\t\t\t\t\treg = <0xc0>;\n" "> +\t\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t\tpower-domains = <&pd_lsio>;\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tpd_lsio_pwm2: lsio-pwm2 at c1 {\n" + "> +\t\t\t\tpd_lsio_pwm2: lsio-pwm2@c1 {\n" "> +\t\t\t\t\treg = <0xc1>;\n" "> +\t\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t\tpower-domains = <&pd_lsio>;\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tpd_lsio_pwm3: lsio-pwm3 at c2 {\n" + "> +\t\t\t\tpd_lsio_pwm3: lsio-pwm3@c2 {\n" "> +\t\t\t\t\treg = <0xc2>;\n" "> +\t\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t\tpower-domains = <&pd_lsio>;\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tpd_lsio_pwm4: lsio-pwm4 at c3 {\n" + "> +\t\t\t\tpd_lsio_pwm4: lsio-pwm4@c3 {\n" "> +\t\t\t\t\treg = <0xc3>;\n" "> +\t\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t\tpower-domains = <&pd_lsio>;\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tpd_lsio_pwm5: lsio-pwm5 at c4 {\n" + "> +\t\t\t\tpd_lsio_pwm5: lsio-pwm5@c4 {\n" "> +\t\t\t\t\treg = <0xc4>;\n" "> +\t\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t\tpower-domains = <&pd_lsio>;\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tpd_lsio_pwm6: lsio-pwm6 at c5 {\n" + "> +\t\t\t\tpd_lsio_pwm6: lsio-pwm6@c5 {\n" "> +\t\t\t\t\treg = <0xc5>;\n" "> +\t\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t\tpower-domains = <&pd_lsio>;\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tpd_lsio_pwm7: lsio-pwm7 at c6 {\n" + "> +\t\t\t\tpd_lsio_pwm7: lsio-pwm7@c6 {\n" "> +\t\t\t\t\treg = <0xc6>;\n" "> +\t\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t\tpower-domains = <&pd_lsio>;\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tpd_lsio_gpio0: lsio-gpio0 at c7 {\n" + "> +\t\t\t\tpd_lsio_gpio0: lsio-gpio0@c7 {\n" "> +\t\t\t\t\treg = <0xc7>;\n" "> +\t\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t\tpower-domains = <&pd_lsio>;\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tpd_lsio_gpio1: lsio-gpio1 at c8 {\n" + "> +\t\t\t\tpd_lsio_gpio1: lsio-gpio1@c8 {\n" "> +\t\t\t\t\treg = <0xc8>;\n" "> +\t\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t\tpower-domains = <&pd_lsio>;\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tpd_lsio_gpio2: lsio-gpio2 at c9 {\n" + "> +\t\t\t\tpd_lsio_gpio2: lsio-gpio2@c9 {\n" "> +\t\t\t\t\treg = <0xc9>;\n" "> +\t\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t\tpower-domains = <&pd_lsio>;\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tpd_lsio_gpio3: lsio-gpio3 at ca {\n" + "> +\t\t\t\tpd_lsio_gpio3: lsio-gpio3@ca {\n" "> +\t\t\t\t\treg = <0xca>;\n" "> +\t\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t\tpower-domains = <&pd_lsio>;\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tpd_lsio_gpio4: lsio-gpio4 at cb {\n" + "> +\t\t\t\tpd_lsio_gpio4: lsio-gpio4@cb {\n" "> +\t\t\t\t\treg = <0xcb>;\n" "> +\t\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t\tpower-domains = <&pd_lsio>;\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tpd_lsio_gpio5: lsio-gpio5 at cc {\n" + "> +\t\t\t\tpd_lsio_gpio5: lsio-gpio5@cc {\n" "> +\t\t\t\t\treg = <0xcc>;\n" "> +\t\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t\tpower-domains = <&pd_lsio>;\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tpd_lsio_gpio6: lsio-gpio6 at cd {\n" + "> +\t\t\t\tpd_lsio_gpio6: lsio-gpio6@cd {\n" "> +\t\t\t\t\treg = <0xcd>;\n" "> +\t\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t\tpower-domains = <&pd_lsio>;\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tpd_lsio_gpio7: lsio-gpio7 at ce {\n" + "> +\t\t\t\tpd_lsio_gpio7: lsio-gpio7@ce {\n" "> +\t\t\t\t\treg = <0xce>;\n" "> +\t\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t\tpower-domains = <&pd_lsio>;\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tpd_lsio_gpt0: lsio-gpt0 at cf {\n" + "> +\t\t\t\tpd_lsio_gpt0: lsio-gpt0@cf {\n" "> +\t\t\t\t\treg = <0xcf>;\n" "> +\t\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t\tpower-domains = <&pd_lsio>;\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tpd_lsio_gpt1: lsio-gpt1 at d0 {\n" + "> +\t\t\t\tpd_lsio_gpt1: lsio-gpt1@d0 {\n" "> +\t\t\t\t\treg = <0xd0>;\n" "> +\t\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t\tpower-domains = <&pd_lsio>;\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tpd_lsio_gpt2: lsio-gpt2 at d1 {\n" + "> +\t\t\t\tpd_lsio_gpt2: lsio-gpt2@d1 {\n" "> +\t\t\t\t\treg = <0xd1>;\n" "> +\t\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t\tpower-domains = <&pd_lsio>;\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tpd_lsio_gpt3: lsio-gpt3 at d2 {\n" + "> +\t\t\t\tpd_lsio_gpt3: lsio-gpt3@d2 {\n" "> +\t\t\t\t\treg = <0xd2>;\n" "> +\t\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t\tpower-domains = <&pd_lsio>;\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tpd_lsio_gpt4: lsio-gpt4 at d3 {\n" + "> +\t\t\t\tpd_lsio_gpt4: lsio-gpt4@d3 {\n" "> +\t\t\t\t\treg = <0xd3>;\n" "> +\t\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t\tpower-domains = <&pd_lsio>;\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tpd_lsio_kpp: lsio-kpp at d4 {\n" + "> +\t\t\t\tpd_lsio_kpp: lsio-kpp@d4 {\n" "> +\t\t\t\t\treg = <0xd4>;\n" "> +\t\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t\tpower-domains = <&pd_lsio>;\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tpd_lsio_flexspi0: lsio-fspi0 at ed {\n" + "> +\t\t\t\tpd_lsio_flexspi0: lsio-fspi0@ed {\n" "> +\t\t\t\t\treg = <0xed>;\n" "> +\t\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t\tpower-domains = <&pd_lsio>;\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tpd_lsio_flexspi1: lsio-fspi1 at ee {\n" + "> +\t\t\t\tpd_lsio_flexspi1: lsio-fspi1@ee {\n" "> +\t\t\t\t\treg = <0xee>;\n" "> +\t\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t\tpower-domains = <&pd_lsio>;\n" @@ -380,103 +390,103 @@ "> +\t\t\t\t#address-cells = <1>;\n" "> +\t\t\t\t#size-cells = <0>;\n" "> +\n" - "> +\t\t\t\tpd_conn_sdhc0: conn-sdhc0 at f8 {\n" + "> +\t\t\t\tpd_conn_sdhc0: conn-sdhc0@f8 {\n" "> +\t\t\t\t\treg = <0xf8>;\n" "> +\t\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t\tpower-domains = <&pd_conn>;\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tpd_conn_sdhc1: conn-sdhc1 at f9 {\n" + "> +\t\t\t\tpd_conn_sdhc1: conn-sdhc1@f9 {\n" "> +\t\t\t\t\treg = <0xf9>;\n" "> +\t\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t\tpower-domains = <&pd_conn>;\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tpd_conn_sdhc2: conn-sdhc2 at fa {\n" + "> +\t\t\t\tpd_conn_sdhc2: conn-sdhc2@fa {\n" "> +\t\t\t\t\treg = <0xfa>;\n" "> +\t\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t\tpower-domains = <&pd_conn>;\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tpd_conn_enet0: conn-enet0 at fb {\n" + "> +\t\t\t\tpd_conn_enet0: conn-enet0@fb {\n" "> +\t\t\t\t\treg = <0xfb>;\n" "> +\t\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t\tpower-domains = <&pd_conn>;\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tpd_conn_enet1: conn-enet1 at fc {\n" + "> +\t\t\t\tpd_conn_enet1: conn-enet1@fc {\n" "> +\t\t\t\t\treg = <0xfc>;\n" "> +\t\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t\tpower-domains = <&pd_conn>;\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tpd_conn_mlb0: conn-mlb0 at fd {\n" + "> +\t\t\t\tpd_conn_mlb0: conn-mlb0@fd {\n" "> +\t\t\t\t\treg = <0xfd>;\n" "> +\t\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t\tpower-domains = <&pd_conn>;\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tpd_conn_usbotg0: conn-usb0 at 103 {\n" + "> +\t\t\t\tpd_conn_usbotg0: conn-usb0@103 {\n" "> +\t\t\t\t\treg = <0x103>;\n" "> +\t\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t\tpower-domains = <&pd_conn>;\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tpd_conn_usbotg1: conn-usb1 at 104 {\n" + "> +\t\t\t\tpd_conn_usbotg1: conn-usb1@104 {\n" "> +\t\t\t\t\treg = <0x104>;\n" "> +\t\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t\tpower-domains = <&pd_conn>;\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tpd_conn_usbotg0_phy: conn-usb0-phy at 105 {\n" + "> +\t\t\t\tpd_conn_usbotg0_phy: conn-usb0-phy@105 {\n" "> +\t\t\t\t\treg = <0x105>;\n" "> +\t\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t\tpower-domains = <&pd_conn>;\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tpd_conn_usb2: conn-usb2 at 106 {\n" + "> +\t\t\t\tpd_conn_usb2: conn-usb2@106 {\n" "> +\t\t\t\t\treg = <0x106>;\n" "> +\t\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t\tpower-domains = <&pd_conn>;\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tpd_conn_usb2_phy: conn-usb2-phy at 107 {\n" + "> +\t\t\t\tpd_conn_usb2_phy: conn-usb2-phy@107 {\n" "> +\t\t\t\t\treg = <0x107>;\n" "> +\t\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t\tpower-domains = <&pd_conn>;\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tpd_conn_nand: conn-nand at 109 {\n" + "> +\t\t\t\tpd_conn_nand: conn-nand@109 {\n" "> +\t\t\t\t\treg = <0x109>;\n" "> +\t\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t\tpower-domains = <&pd_conn>;\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tpd_conn_edma_ch0: conn-dma4-ch0 at 174 {\n" + "> +\t\t\t\tpd_conn_edma_ch0: conn-dma4-ch0@174 {\n" "> +\t\t\t\t\treg = <0x174>;\n" "> +\t\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t\tpower-domains =<&pd_conn>;\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tpd_conn_edma_ch1: conn-dma4-ch1 at 175 {\n" + "> +\t\t\t\tpd_conn_edma_ch1: conn-dma4-ch1@175 {\n" "> +\t\t\t\t\treg = <0x175>;\n" "> +\t\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t\tpower-domains =<&pd_conn>;\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tpd_conn_edma_ch2: conn-dma4-ch2 at 176 {\n" + "> +\t\t\t\tpd_conn_edma_ch2: conn-dma4-ch2@176 {\n" "> +\t\t\t\t\treg = <0x176>;\n" "> +\t\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t\tpower-domains =<&pd_conn>;\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tpd_conn_edma_ch3: conn-dma4-ch3 at 177 {\n" + "> +\t\t\t\tpd_conn_edma_ch3: conn-dma4-ch3@177 {\n" "> +\t\t\t\t\treg = <0x177>;\n" "> +\t\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t\tpower-domains =<&pd_conn>;\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tpd_conn_edma_ch4: conn-dma4-ch4 at 178 {\n" + "> +\t\t\t\tpd_conn_edma_ch4: conn-dma4-ch4@178 {\n" "> +\t\t\t\t\treg = <0x178>;\n" "> +\t\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t\tpower-domains =<&pd_conn>;\n" @@ -488,121 +498,121 @@ "> +\t\t\t\t#address-cells = <1>;\n" "> +\t\t\t\t#size-cells = <0>;\n" "> +\n" - "> +\t\t\t\tpd_dma_lpspi0: dma-spi0 at 35 {\n" + "> +\t\t\t\tpd_dma_lpspi0: dma-spi0@35 {\n" "> +\t\t\t\t\treg = <0x35>;\n" "> +\t\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t\tpower-domains = <&pd_dma>;\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tpd_dma_lpspi1: dma-spi1 at 36 {\n" + "> +\t\t\t\tpd_dma_lpspi1: dma-spi1@36 {\n" "> +\t\t\t\t\treg = <0x36>;\n" "> +\t\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t\tpower-domains = <&pd_dma>;\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tpd_dma_lpspi2: dma-spi2 at 37 {\n" + "> +\t\t\t\tpd_dma_lpspi2: dma-spi2@37 {\n" "> +\t\t\t\t\treg = <0x37>;\n" "> +\t\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t\tpower-domains = <&pd_dma>;\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tpd_dma_lpspi3: dma-spi3 at 38 {\n" + "> +\t\t\t\tpd_dma_lpspi3: dma-spi3@38 {\n" "> +\t\t\t\t\treg = <0x38>;\n" "> +\t\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t\tpower-domains = <&pd_dma>;\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tpd_dma_lpuart0: dma-lpuart0 at 39 {\n" + "> +\t\t\t\tpd_dma_lpuart0: dma-lpuart0@39 {\n" "> +\t\t\t\t\treg = <0x39>;\n" "> +\t\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t\tpower-domains = <&pd_dma>;\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tpd_dma_lpuart1: dma-lpuart1 at 3a {\n" + "> +\t\t\t\tpd_dma_lpuart1: dma-lpuart1@3a {\n" "> +\t\t\t\t\treg = <0x3a>;\n" "> +\t\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t\tpower-domains = <&pd_dma>;\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tpd_dma_lpuart2: dma-lpuart2 at 3b {\n" + "> +\t\t\t\tpd_dma_lpuart2: dma-lpuart2@3b {\n" "> +\t\t\t\t\treg = <0x3b>;\n" "> +\t\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t\tpower-domains = <&pd_dma>;\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tpd_dma_lpuart3: dma-lpuart3 at 3c {\n" + "> +\t\t\t\tpd_dma_lpuart3: dma-lpuart3@3c {\n" "> +\t\t\t\t\treg = <0x3c>;\n" "> +\t\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t\tpower-domains = <&pd_dma>;\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tpd_dma_lpi2c0: dma-lpi2c0 at 60 {\n" + "> +\t\t\t\tpd_dma_lpi2c0: dma-lpi2c0@60 {\n" "> +\t\t\t\t\treg = <0x60>;\n" "> +\t\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t\tpower-domains = <&pd_dma>;\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tpd_dma_lpi2c1: dma-lpi2c1 at 61 {\n" + "> +\t\t\t\tpd_dma_lpi2c1: dma-lpi2c1@61 {\n" "> +\t\t\t\t\treg = <0x61>;\n" "> +\t\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t\tpower-domains = <&pd_dma>;\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tpd_dma_lpi2c2: dma-lpi2c2 at 62 {\n" + "> +\t\t\t\tpd_dma_lpi2c2: dma-lpi2c2@62 {\n" "> +\t\t\t\t\treg = <0x62>;\n" "> +\t\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t\tpower-domains = <&pd_dma>;\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tpd_dma_lpi2c3: dma-lpi2c3 at 63 {\n" + "> +\t\t\t\tpd_dma_lpi2c3: dma-lpi2c3@63 {\n" "> +\t\t\t\t\treg = <0x63>;\n" "> +\t\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t\tpower-domains = <&pd_dma>;\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tpd_dma_adc0: dma-adc0 at 65 {\n" + "> +\t\t\t\tpd_dma_adc0: dma-adc0@65 {\n" "> +\t\t\t\t\treg = <0x65>;\n" "> +\t\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t\tpower-domains = <&pd_dma>;\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tpd_dma_ftm0: dma-ftm0 at 67 {\n" + "> +\t\t\t\tpd_dma_ftm0: dma-ftm0@67 {\n" "> +\t\t\t\t\treg = <0x67>;\n" "> +\t\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t\tpower-domains = <&pd_dma>;\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tpd_dma_ftm1: dma-ftm1 at 68 {\n" + "> +\t\t\t\tpd_dma_ftm1: dma-ftm1@68 {\n" "> +\t\t\t\t\treg = <0x68>;\n" "> +\t\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t\tpower-domains = <&pd_dma>;\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tpd_dma_flexcan0: dma-flexcan0 at 69 {\n" + "> +\t\t\t\tpd_dma_flexcan0: dma-flexcan0@69 {\n" "> +\t\t\t\t\treg = <0x69>;\n" "> +\t\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t\tpower-domains = <&pd_dma>;\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tpd_dma_flexcan1: dma-flexcan1 at 6a {\n" + "> +\t\t\t\tpd_dma_flexcan1: dma-flexcan1@6a {\n" "> +\t\t\t\t\treg = <0x6a>;\n" "> +\t\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t\tpower-domains = <&pd_dma>;\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tpd_dma_flexcan2: dma-flexcan2 at 6b {\n" + "> +\t\t\t\tpd_dma_flexcan2: dma-flexcan2@6b {\n" "> +\t\t\t\t\treg = <0x6b>;\n" "> +\t\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t\tpower-domains = <&pd_dma>;\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tpd_dma_lcd0: dma-lcd0 at bb {\n" + "> +\t\t\t\tpd_dma_lcd0: dma-lcd0@bb {\n" "> +\t\t\t\t\treg = <0xbb>;\n" "> +\t\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t\tpower-domains = <&pd_dma>;\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tpd_dma_pwm0: dma-pwm0 at bc {\n" + "> +\t\t\t\tpd_dma_pwm0: dma-pwm0@bc {\n" "> +\t\t\t\t\treg = <0xbc>;\n" "> +\t\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t\tpower-domains = <&pd_dma>;\n" @@ -614,7 +624,7 @@ "> +\t\t\t\t#address-cells = <1>;\n" "> +\t\t\t\t#size-cells = <0>;\n" "> +\n" - "> +\t\t\t\tpd_gpu0: gpu0 at 90 {\n" + "> +\t\t\t\tpd_gpu0: gpu0@90 {\n" "> +\t\t\t\t\treg = <0x90>;\n" "> +\t\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t\tpower-domains =<&pd_gpu>;\n" @@ -623,13 +633,13 @@ "> +\t\t\t\t};\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tpd_vpu: vpu-power-domain at 166 {\n" + "> +\t\t\tpd_vpu: vpu-power-domain@166 {\n" "> +\t\t\t\treg = <0x166>;\n" "> +\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t#address-cells = <1>;\n" "> +\t\t\t\t#size-cells = <0>;\n" "> +\n" - "> +\t\t\t\tpd_vpu_core: vpu-core at 16f {\n" + "> +\t\t\t\tpd_vpu_core: vpu-core@16f {\n" "> +\t\t\t\t\treg = <0x16f>;\n" "> +\t\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t\tpower-domains =<&pd_vpu>;\n" @@ -641,7 +651,7 @@ "> +\t\t\t\t#address-cells = <1>;\n" "> +\t\t\t\t#size-cells = <0>;\n" "> +\n" - "> +\t\t\t\tpd_pcie: hsio-pcie-pd at 98 {\n" + "> +\t\t\t\tpd_pcie: hsio-pcie-pd@98 {\n" "> +\t\t\t\t\treg = <0x98>;\n" "> +\t\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t\tpower-domains =<&pd_hsio>;\n" @@ -653,47 +663,47 @@ "> +\t\t\t\t#address-cells = <1>;\n" "> +\t\t\t\t#size-cells = <0>;\n" "> +\n" - "> +\t\t\t\tpd_dc0: dc0-power-domain at 20 {\n" + "> +\t\t\t\tpd_dc0: dc0-power-domain@20 {\n" "> +\t\t\t\t\treg = <0x20>;\n" "> +\t\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t\tpower-domains =<&pd_dc>;\n" "> +\t\t\t\t};\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tpd_mipi_dsi: mipi0-dsi-power-domain at 189 {\n" + "> +\t\t\tpd_mipi_dsi: mipi0-dsi-power-domain@189 {\n" "> +\t\t\t\treg = <0x189>;\n" "> +\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t#address-cells = <1>;\n" "> +\t\t\t\t#size-cells = <0>;\n" "> +\n" - "> +\t\t\t\tpd_mipi_pwm0: mipi0-dsi-pwm0 at 18a {\n" + "> +\t\t\t\tpd_mipi_pwm0: mipi0-dsi-pwm0@18a {\n" "> +\t\t\t\t\treg = <0x18a>;\n" "> +\t\t\t\t\tpower-domains =<&pd_mipi_dsi>;\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tpd_mipi_dsi_i2c0: mipi0-dsi-i2c0 at 18b {\n" + "> +\t\t\t\tpd_mipi_dsi_i2c0: mipi0-dsi-i2c0@18b {\n" "> +\t\t\t\t\treg = <0x18b>;\n" "> +\t\t\t\t\tpower-domains =<&pd_mipi_dsi>;\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tpd_mipi_dsi_i2c1: mipi0-dsi-i2c1 at 18c {\n" + "> +\t\t\t\tpd_mipi_dsi_i2c1: mipi0-dsi-i2c1@18c {\n" "> +\t\t\t\t\treg = <0x18c>;\n" "> +\t\t\t\t\tpower-domains =<&pd_mipi_dsi>;\n" "> +\t\t\t\t};\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tpd_mipi_csi: mipi-csi0-power-domain at 191 {\n" + "> +\t\t\tpd_mipi_csi: mipi-csi0-power-domain@191 {\n" "> +\t\t\t\treg = <0x191>;\n" "> +\t\t\t\t#power-domain-cells = <0>;\n" "> +\t\t\t\t#address-cells = <1>;\n" "> +\t\t\t\t#size-cells = <0>;\n" "> +\n" - "> +\t\t\t\tpd_mipi_csi0_pwm0: mipi-csi0-pwm at 192 {\n" + "> +\t\t\t\tpd_mipi_csi0_pwm0: mipi-csi0-pwm@192 {\n" "> +\t\t\t\t\treg = <0x192>;\n" "> +\t\t\t\t\tpower-domains =<&pd_mipi_csi>;\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tpd_mipi_csi0_i2c0: mipi-csi0-i2c at 193 {\n" + "> +\t\t\t\tpd_mipi_csi0_i2c0: mipi-csi0-i2c@193 {\n" "> +\t\t\t\t\treg = <0x193>;\n" "> +\t\t\t\t\tpower-domains =<&pd_mipi_csi>;\n" "> +\t\t\t\t};\n" @@ -701,14 +711,14 @@ "> +\t\t};\n" "> +\t};\n" "> +\n" - "> +\taudio_subsys: bus at 59000000 {\n" + "> +\taudio_subsys: bus@59000000 {\n" "> +\t\tcompatible = \"simple-bus\";\n" "> +\t\t#address-cells = <1>;\n" "> +\t\t#size-cells = <1>;\n" "> +\t\tranges = <0x59000000 0x0 0x59000000 0x1000000>;\n" "> +\t};\n" "> +\n" - "> +\tdma_subsys: bus at 5a000000 {\n" + "> +\tdma_subsys: bus@5a000000 {\n" "> +\t\tcompatible = \"simple-bus\";\n" "> +\t\t#address-cells = <1>;\n" "> +\t\t#size-cells = <1>;\n" @@ -716,7 +726,7 @@ "\n" "Can't you do some actual translation here.\n" "> +\n" - "> +\t\tdma_lpuart0: serial at 5a060000 {\n" + "> +\t\tdma_lpuart0: serial@5a060000 {\n" "> +\t\t\tcompatible = \"fsl,imx8qxp-lpuart\", \"fsl,imx7ulp-lpuart\";\n" "> +\t\t\treg = <0x5a060000 0x1000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -726,7 +736,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tdma_i2c0: i2c at 5a800000 {\n" + "> +\t\tdma_i2c0: i2c@5a800000 {\n" "> +\t\t\tcompatible = \"fsl,imx8qxp-lpi2c\", \"fsl,imx7ulp-lpi2c\";\n" "> +\t\t\treg = <0x5a800000 0x4000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -739,7 +749,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tdma_i2c1: i2c at 5a810000 {\n" + "> +\t\tdma_i2c1: i2c@5a810000 {\n" "> +\t\t\tcompatible = \"fsl,imx8qxp-lpi2c\", \"fsl,imx7ulp-lpi2c\";\n" "> +\t\t\treg = <0x5a810000 0x4000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -751,7 +761,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tdma_i2c2: i2c at 5a820000 {\n" + "> +\t\tdma_i2c2: i2c@5a820000 {\n" "> +\t\t\tcompatible = \"fsl,imx8qxp-lpi2c\", \"fsl,imx7ulp-lpi2c\";\n" "> +\t\t\treg = <0x5a820000 0x4000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -764,7 +774,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tdma_i2c3: i2c at 5a830000 {\n" + "> +\t\tdma_i2c3: i2c@5a830000 {\n" "> +\t\t\tcompatible = \"fsl,imx8qxp-lpi2c\", \"fsl,imx7ulp-lpi2c\";\n" "> +\t\t\treg = <0x5a830000 0x4000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -778,13 +788,13 @@ "> +\t\t};\n" "> +\t};\n" "> +\n" - "> +\tconn_subsys: bus at 5b000000 {\n" + "> +\tconn_subsys: bus@5b000000 {\n" "> +\t\tcompatible = \"simple-bus\";\n" "> +\t\t#address-cells = <1>;\n" "> +\t\t#size-cells = <1>;\n" "> +\t\tranges = <0x5b000000 0x0 0x5b000000 0x1000000>;\n" "> +\n" - "> +\t\tusdhc1: mmc at 5b010000 {\n" + "> +\t\tusdhc1: mmc@5b010000 {\n" "> +\t\t\tcompatible = \"fsl,imx8qxp-usdhc\", \"fsl,imx7d-usdhc\";\n" "> +\t\t\tinterrupt-parent = <&gic>;\n" "> +\t\t\tinterrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -799,7 +809,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tusdhc2: mmc at 5b020000 {\n" + "> +\t\tusdhc2: mmc@5b020000 {\n" "> +\t\t\tcompatible = \"fsl,imx8qxp-usdhc\", \"fsl,imx7d-usdhc\";\n" "> +\t\t\tinterrupt-parent = <&gic>;\n" "> +\t\t\tinterrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -816,7 +826,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tusdhc3: mmc at 5b030000 {\n" + "> +\t\tusdhc3: mmc@5b030000 {\n" "> +\t\t\tcompatible = \"fsl,imx8qxp-usdhc\", \"fsl,imx7d-usdhc\";\n" "> +\t\t\tinterrupt-parent = <&gic>;\n" "> +\t\t\tinterrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -831,7 +841,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tfec1: ethernet at 5b040000 {\n" + "> +\t\tfec1: ethernet@5b040000 {\n" "> +\t\t\tcompatible = \"fsl,imx8qxp-fec\", \"fsl,imx6sx-fec\";\n" "> +\t\t\treg = <0x5b040000 0x10000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,\n" @@ -849,7 +859,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tfec2: ethernet at 5b050000 {\n" + "> +\t\tfec2: ethernet@5b050000 {\n" "> +\t\t\tcompatible = \"fsl,imx8qxp-fec\", \"fsl,imx6sx-fec\";\n" "> +\t\t\treg = <0x5b050000 0x10000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,\n" @@ -868,24 +878,24 @@ "> +\t\t};\n" "> +\t};\n" "> +\n" - "> +\tdb_subsys: bus at 5c000000 {\n" + "> +\tdb_subsys: bus@5c000000 {\n" "> +\t\tcompatible = \"simple-bus\";\n" "> +\t\t#address-cells = <1>;\n" "> +\t\t#size-cells = <1>;\n" "> +\t\tranges = <0x5c000000 0x0 0x5c000000 0x1000000>;\n" "> +\n" - "> +\t\tddr_pmu0: pmu at 5c020000 {\n" + "> +\t\tddr_pmu0: pmu@5c020000 {\n" "> +\t\t\treg = <0x5c020000 0x10000>;\n" "> +\t\t};\n" "> +\t};\n" "> +\n" - "> +\tlsio_subsys: bus at 5d000000 {\n" + "> +\tlsio_subsys: bus@5d000000 {\n" "> +\t\tcompatible = \"simple-bus\";\n" "> +\t\t#address-cells = <1>;\n" "> +\t\t#size-cells = <1>;\n" "> +\t\tranges = <0x5d000000 0x0 0x5d000000 0x1000000>;\n" "> +\n" - "> +\t\tlsio_mu0: mailbox at 5d1b0000 {\n" + "> +\t\tlsio_mu0: mailbox@5d1b0000 {\n" "> +\t\t\tcompatible = \"fsl,imx8qxp-mu\", \"fsl,imx6sx-mu\";\n" "> +\t\t\treg = <0x5d1b0000 0x10000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -893,14 +903,14 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tlsio_mu1: mailbox at 5d1c0000 {\n" + "> +\t\tlsio_mu1: mailbox@5d1c0000 {\n" "> +\t\t\tcompatible = \"fsl,imx8qxp-mu\", \"fsl,imx6sx-mu\";\n" "> +\t\t\treg = <0x5d1c0000 0x10000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;\n" "> +\t\t\t#mbox-cells = <2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tlsio_mu3: mailbox at 5d1e0000 {\n" + "> +\t\tlsio_mu3: mailbox@5d1e0000 {\n" "> +\t\t\tcompatible = \"fsl,imx8qxp-mu\", \"fsl,imx6sx-mu\";\n" "> +\t\t\treg = <0x5d1e0000 0x10000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -908,7 +918,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tlsio_mu4: mailbox at 5d1f0000 {\n" + "> +\t\tlsio_mu4: mailbox@5d1f0000 {\n" "> +\t\t\tcompatible = \"fsl,imx8qxp-mu\", \"fsl,imx6sx-mu\";\n" "> +\t\t\treg = <0x5d1f0000 0x10000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -916,7 +926,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tlsio_gpio0: gpio at 5d080000 {\n" + "> +\t\tlsio_gpio0: gpio@5d080000 {\n" "> +\t\t\tcompatible = \"fsl,imx8qxp-gpio\", \"fsl,imx35-gpio\";\n" "> +\t\t\treg = <0x5d080000 0x10000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -927,7 +937,7 @@ "> +\t\t\tpower-domains = <&pd_lsio_gpio0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tlsio_gpio1: gpio at 5d090000 {\n" + "> +\t\tlsio_gpio1: gpio@5d090000 {\n" "> +\t\t\tcompatible = \"fsl,imx8qxp-gpio\", \"fsl,imx35-gpio\";\n" "> +\t\t\treg = <0x5d090000 0x10000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -938,7 +948,7 @@ "> +\t\t\tpower-domains = <&pd_lsio_gpio1>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tlsio_gpio2: gpio at 5d0a0000 {\n" + "> +\t\tlsio_gpio2: gpio@5d0a0000 {\n" "> +\t\t\tcompatible = \"fsl,imx8qxp-gpio\", \"fsl,imx35-gpio\";\n" "> +\t\t\treg = <0x5d0a0000 0x10000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -949,7 +959,7 @@ "> +\t\t\tpower-domains = <&pd_lsio_gpio2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tlsio_gpio3: gpio at 5d0b0000 {\n" + "> +\t\tlsio_gpio3: gpio@5d0b0000 {\n" "> +\t\t\tcompatible = \"fsl,imx8qxp-gpio\", \"fsl,imx35-gpio\";\n" "> +\t\t\treg = <0x5d0b0000 0x10000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -960,7 +970,7 @@ "> +\t\t\tpower-domains = <&pd_lsio_gpio3>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tlsio_gpio4: gpio at 5d0c0000 {\n" + "> +\t\tlsio_gpio4: gpio@5d0c0000 {\n" "> +\t\t\tcompatible = \"fsl,imx8qxp-gpio\", \"fsl,imx35-gpio\";\n" "> +\t\t\treg = <0x5d0c0000 0x10000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -971,7 +981,7 @@ "> +\t\t\tpower-domains = <&pd_lsio_gpio4>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tlsio_gpio5: gpio at 5d0d0000 {\n" + "> +\t\tlsio_gpio5: gpio@5d0d0000 {\n" "> +\t\t\tcompatible = \"fsl,imx8qxp-gpio\", \"fsl,imx35-gpio\";\n" "> +\t\t\treg = <0x5d0d0000 0x10000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -982,7 +992,7 @@ "> +\t\t\tpower-domains = <&pd_lsio_gpio5>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tlsio_gpio6: gpio at 5d0e0000 {\n" + "> +\t\tlsio_gpio6: gpio@5d0e0000 {\n" "> +\t\t\tcompatible = \"fsl,imx8qxp-gpio\", \"fsl,imx35-gpio\";\n" "> +\t\t\treg = <0x5d0e0000 0x10000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -993,7 +1003,7 @@ "> +\t\t\tpower-domains = <&pd_lsio_gpio6>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tlsio_gpio7: gpio at 5d0f0000 {\n" + "> +\t\tlsio_gpio7: gpio@5d0f0000 {\n" "> +\t\t\tcompatible = \"fsl,imx8qxp-gpio\", \"fsl,imx35-gpio\";\n" "> +\t\t\treg = <0x5d0f0000 0x10000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -1005,7 +1015,7 @@ "> +\t\t};\n" "> +\t};\n" "> +\n" - "> +\thsio_subsys: bus at 5f000000 {\n" + "> +\thsio_subsys: bus@5f000000 {\n" "> +\t\tcompatible = \"simple-bus\";\n" "> +\t\t#address-cells = <1>;\n" "> +\t\t#size-cells = <1>;\n" @@ -1016,4 +1026,4 @@ "> 2.7.4\n" > -980a9d97a78379c52b270a566e677c0f5b05dd3f09f77c9c2a9b39e6904d546d +60517281cf80553b85bc26cb8108316f0677860fae73db0510612c12f27df4cb
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.