Re: [PATCH v2] drm/i915: Don't apply the 16Gb DIMM wm latency w/a to BXT/GLK

[Rodrigo Vivi <rodrigo.vivi@intel.com>]

On Tue, Oct 23, 2018 at 09:21:02PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> The 16Gb DIMM w/a is not applicable to BXT or GLK. Limit it to
> the appropriate platforms.
> 
> This was especially harsh on GLK since we don't even try to read
> the DIMM information on that platforms, hence valid_dimm was
> always false and thus we always tried to apply the w/a.
> Furthermore the w/a pushed the level 0 latency above the
> level 1 latency, which doesn't really make sense.
> 
> v2: Do the check when populating is_16gb_dimm (Mahesh)
> 
> Cc: Mahesh Kumar <mahesh1.kumar@intel.com>
> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Fixes: 86b592876cb6 ("drm/i915: Implement 16GB dimm wa for latency level-0")
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.c | 15 ++++++++-------
>  drivers/gpu/drm/i915/i915_drv.h |  1 -
>  drivers/gpu/drm/i915/intel_pm.c |  3 +--
>  3 files changed, 9 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index baac35f698f9..6571044c9286 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1165,8 +1165,6 @@ skl_dram_get_channels_info(struct drm_i915_private *dev_priv)
>  		return -EINVAL;
>  	}
>  
> -	dram_info->valid_dimm = true;
> -
>  	/*
>  	 * If any of the channel is single rank channel, worst case output
>  	 * will be same as if single rank memory, so consider single rank
> @@ -1183,8 +1181,7 @@ skl_dram_get_channels_info(struct drm_i915_private *dev_priv)
>  		return -EINVAL;
>  	}
>  
> -	if (ch0.is_16gb_dimm || ch1.is_16gb_dimm)
> -		dram_info->is_16gb_dimm = true;
> +	dram_info->is_16gb_dimm = ch0.is_16gb_dimm || ch1.is_16gb_dimm;
>  
>  	dev_priv->dram_info.symmetric_memory = intel_is_dram_symmetric(val_ch0,
>  								       val_ch1,
> @@ -1304,7 +1301,6 @@ bxt_get_dram_info(struct drm_i915_private *dev_priv)
>  		return -EINVAL;
>  	}
>  
> -	dram_info->valid_dimm = true;
>  	dram_info->valid = true;
>  	return 0;
>  }
> @@ -1317,12 +1313,17 @@ intel_get_dram_info(struct drm_i915_private *dev_priv)
>  	int ret;
>  
>  	dram_info->valid = false;
> -	dram_info->valid_dimm = false;
> -	dram_info->is_16gb_dimm = false;
>  	dram_info->rank = I915_DRAM_RANK_INVALID;
>  	dram_info->bandwidth_kbps = 0;
>  	dram_info->num_channels = 0;
>  
> +	/*
> +	 * Assume 16Gb DIMMs are present until proven otherwise.
> +	 * This is only used for the level 0 watermark latency
> +	 * w/a which does not apply to bxt/glk.
> +	 */
> +	dram_info->is_16gb_dimm = !IS_GEN9_LP(dev_priv);
> +
>  	if (INTEL_GEN(dev_priv) < 9 || IS_GEMINILAKE(dev_priv))
>  		return;
>  
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 22cf3c75558c..2d7761b8ac07 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1933,7 +1933,6 @@ struct drm_i915_private {
>  
>  	struct dram_info {
>  		bool valid;
> -		bool valid_dimm;
>  		bool is_16gb_dimm;
>  		u8 num_channels;
>  		enum dram_rank {
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 67a4d0735291..faef7f528269 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2881,8 +2881,7 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
>  		 * any underrun. If not able to get Dimm info assume 16GB dimm
>  		 * to avoid any underrun.
>  		 */
> -		if (!dev_priv->dram_info.valid_dimm ||
> -		    dev_priv->dram_info.is_16gb_dimm)
> +		if (dev_priv->dram_info.is_16gb_dimm)
>  			wm[0] += 1;
>  
>  	} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> -- 
> 2.18.1
> 
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