From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH v1 1/2] drm: Add missing flags for pixel clock & data enable Date: Wed, 24 Oct 2018 10:16:58 +0200 Message-ID: <20181024081658.GD324@phenom.ffwll.local> References: <1537788981-21479-1-git-send-email-yannick.fertre@st.com> <1537788981-21479-2-git-send-email-yannick.fertre@st.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mail-ed1-x544.google.com (mail-ed1-x544.google.com [IPv6:2a00:1450:4864:20::544]) by gabe.freedesktop.org (Postfix) with ESMTPS id B3FEA6E1D4 for ; Wed, 24 Oct 2018 08:17:02 +0000 (UTC) Received: by mail-ed1-x544.google.com with SMTP id e5-v6so4159701eds.6 for ; Wed, 24 Oct 2018 01:17:02 -0700 (PDT) Content-Disposition: inline In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Benjamin Gaignard Cc: sean@poorly.run, Benjamin GAIGNARD , David Airlie , Philippe Cornu , ML dri-devel , Linux Kernel Mailing List , Yannick Fertre , Vincent Abriou List-Id: dri-devel@lists.freedesktop.org T24gVHVlLCBPY3QgMjMsIDIwMTggYXQgMDQ6NTA6MTlQTSArMDIwMCwgQmVuamFtaW4gR2FpZ25h cmQgd3JvdGU6Cj4gTGUgbHVuLiAxNSBvY3QuIDIwMTggw6AgMTM6MTUsIEJlbmphbWluIEdhaWdu YXJkCj4gPGJlbmphbWluLmdhaWduYXJkQGxpbmFyby5vcmc+IGEgw6ljcml0IDoKPiA+Cj4gPiBM ZSBsdW4uIDI0IHNlcHQuIDIwMTggw6AgMTM6NTksIFlhbm5pY2sgRmVydHLDqSA8eWFubmljay5m ZXJ0cmVAc3QuY29tPiBhIMOpY3JpdCA6Cj4gPiA+Cj4gPiA+IEFkZCBtaXNzaW5nIGZsYWdzIGZv ciBwaXhlbCBjbG9jayAmIGRhdGEgZW5hYmxlIHBvbGFyaXRpZXMuCj4gPiA+IFRoZXNlIGZsYWdz IGFyZSBzaW1pbGFyIHRvIG90aGVyIHN5bmNocm9uaXphdGlvbiBzaWduYWxzIChoc3luYywgdnN5 bmMuLi4pLgo+ID4gPgo+ID4gPiBTaWduZWQtb2ZmLWJ5OiBZYW5uaWNrIEZlcnRyw6kgPHlhbm5p Y2suZmVydHJlQHN0LmNvbT4KPiA+Cj4gPiBSZXZpZXdlZC1ieTogQmVuamFtaW4gR2FpZ25hcmQg PGJlbmphbWluLmdhaWduYXJkQGxpbmFyby5vcmc+Cj4gCj4gRGF2ZSBvciBEYW5pZWwgY291bGQg eW91IGdpdmUgdXMgeW91ciBQb1Ygb24gdGhpcyBwYXRjaCA/CgpEb2VzIGl0IHdvcms/IElpcmMg d2UgaGFkIHNvbWUgdXNlcnNwYWNlIGNob2NraW5nIG9uIG5ldyBtb2RlIGZsYWdzLCBhbmQKbmVl ZGVkIGV4cGxpY2l0IG9wdC1pbi4gSWYgdGhhdCBsb29rcyBnb29kIChjaGVjayB3ZXN0b24sIC1t b2Rlc2V0dGluZyBhbmQKZHJtX2h3YywgdGhhdCBzaG91bGQgaGF2ZSB5b3UgY292ZXJlZCBJIGhv cGUpIHRoZW4gaGFzIG15IGFjay4KLURhbmllbAoKPiBUaGFua3MKPiAKPiA+Cj4gPiA+IC0tLQo+ ID4gPiAgZHJpdmVycy9ncHUvZHJtL2RybV9tb2Rlcy5jIHwgMTkgKysrKysrKysrKysrKysrKysr LQo+ID4gPiAgaW5jbHVkZS91YXBpL2RybS9kcm1fbW9kZS5oIHwgIDYgKysrKysrCj4gPiA+ICAy IGZpbGVzIGNoYW5nZWQsIDI0IGluc2VydGlvbnMoKyksIDEgZGVsZXRpb24oLSkKPiA+ID4KPiA+ ID4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9kcm1fbW9kZXMuYyBiL2RyaXZlcnMvZ3B1 L2RybS9kcm1fbW9kZXMuYwo+ID4gPiBpbmRleCAwMmRiOWFjLi41OTZmOGIzIDEwMDY0NAo+ID4g PiAtLS0gYS9kcml2ZXJzL2dwdS9kcm0vZHJtX21vZGVzLmMKPiA+ID4gKysrIGIvZHJpdmVycy9n cHUvZHJtL2RybV9tb2Rlcy5jCj4gPiA+IEBAIC0xMzAsNyArMTMwLDcgQEAgRVhQT1JUX1NZTUJP TChkcm1fbW9kZV9wcm9iZWRfYWRkKTsKPiA+ID4gICAqIGFjY29yZGluZyB0byB0aGUgaGRpc3Bs YXksIHZkaXNwbGF5LCB2cmVmcmVzaC4KPiA+ID4gICAqIEl0IGlzIGJhc2VkIGZyb20gdGhlIFZF U0EoVE0pIENvb3JkaW5hdGVkIFZpZGVvIFRpbWluZyBHZW5lcmF0b3IgYnkKPiA+ID4gICAqIEdy YWhhbSBMb3ZlcmlkZ2UgQXByaWwgOSwgMjAwMyBhdmFpbGFibGUgYXQKPiA+ID4gLSAqIGh0dHA6 Ly93d3cuZWxvLnV0ZnNtLmNsL35lbG8yMTIvZG9jcy9DVlRkNnIxLnhscwo+ID4gPiArICogaHR0 cDovL3d3dy5lbG8udXRmc20uY2wvfmVsbzIxMi9kb2NzL0NWVGQ2cjEueGxzCj4gPiA+ICAgKgo+ ID4gPiAgICogQW5kIGl0IGlzIGNvcGllZCBmcm9tIHhmODZDVlRtb2RlIGluIHhzZXJ2ZXIvaHcv eGZyZWU4Ni9tb2Rlcy94Zjg2Y3Z0LmMuCj4gPiA+ICAgKiBXaGF0IEkgaGF2ZSBkb25lIGlzIHRv IHRyYW5zbGF0ZSBpdCBieSB1c2luZyBpbnRlZ2VyIGNhbGN1bGF0aW9uLgo+ID4gPiBAQCAtNjEx LDYgKzYxMSwxNSBAQCB2b2lkIGRybV9kaXNwbGF5X21vZGVfZnJvbV92aWRlb21vZGUoY29uc3Qg c3RydWN0IHZpZGVvbW9kZSAqdm0sCj4gPiA+ICAgICAgICAgICAgICAgICBkbW9kZS0+ZmxhZ3Mg fD0gRFJNX01PREVfRkxBR19EQkxTQ0FOOwo+ID4gPiAgICAgICAgIGlmICh2bS0+ZmxhZ3MgJiBE SVNQTEFZX0ZMQUdTX0RPVUJMRUNMSykKPiA+ID4gICAgICAgICAgICAgICAgIGRtb2RlLT5mbGFn cyB8PSBEUk1fTU9ERV9GTEFHX0RCTENMSzsKPiA+ID4gKyAgICAgICBpZiAodm0tPmZsYWdzICYg RElTUExBWV9GTEFHU19QSVhEQVRBX1BPU0VER0UpCj4gPiA+ICsgICAgICAgICAgICAgICBkbW9k ZS0+ZmxhZ3MgfD0gRFJNX01PREVfRkxBR19QUElYQ0xLOwo+ID4gPiArICAgICAgIGVsc2UgaWYg KHZtLT5mbGFncyAmIERJU1BMQVlfRkxBR1NfUElYREFUQV9ORUdFREdFKQo+ID4gPiArICAgICAg ICAgICAgICAgZG1vZGUtPmZsYWdzIHw9IERSTV9NT0RFX0ZMQUdfTlBJWENMSzsKPiA+ID4gKyAg ICAgICBpZiAodm0tPmZsYWdzICYgRElTUExBWV9GTEFHU19ERV9ISUdIKQo+ID4gPiArICAgICAg ICAgICAgICAgZG1vZGUtPmZsYWdzIHw9IERSTV9NT0RFX0ZMQUdfUERBVEFFTjsKPiA+ID4gKyAg ICAgICBlbHNlIGlmICh2bS0+ZmxhZ3MgJiBESVNQTEFZX0ZMQUdTX0RFX0xPVykKPiA+ID4gKyAg ICAgICAgICAgICAgIGRtb2RlLT5mbGFncyB8PSBEUk1fTU9ERV9GTEFHX05ERTsKPiA+ID4gKwo+ ID4gPiAgICAgICAgIGRybV9tb2RlX3NldF9uYW1lKGRtb2RlKTsKPiA+ID4gIH0KPiA+ID4gIEVY UE9SVF9TWU1CT0xfR1BMKGRybV9kaXNwbGF5X21vZGVfZnJvbV92aWRlb21vZGUpOwo+ID4gPiBA QCAtNjUyLDYgKzY2MSwxNCBAQCB2b2lkIGRybV9kaXNwbGF5X21vZGVfdG9fdmlkZW9tb2RlKGNv bnN0IHN0cnVjdCBkcm1fZGlzcGxheV9tb2RlICpkbW9kZSwKPiA+ID4gICAgICAgICAgICAgICAg IHZtLT5mbGFncyB8PSBESVNQTEFZX0ZMQUdTX0RPVUJMRVNDQU47Cj4gPiA+ICAgICAgICAgaWYg KGRtb2RlLT5mbGFncyAmIERSTV9NT0RFX0ZMQUdfREJMQ0xLKQo+ID4gPiAgICAgICAgICAgICAg ICAgdm0tPmZsYWdzIHw9IERJU1BMQVlfRkxBR1NfRE9VQkxFQ0xLOwo+ID4gPiArICAgICAgIGlm IChkbW9kZS0+ZmxhZ3MgJiBEUk1fTU9ERV9GTEFHX1BQSVhEQVRBKQo+ID4gPiArICAgICAgICAg ICAgICAgdm0tPmZsYWdzIHw9IERJU1BMQVlfRkxBR1NfUElYREFUQV9QT1NFREdFOwo+ID4gPiAr ICAgICAgIGVsc2UgaWYgKGRtb2RlLT5mbGFncyAmIERSTV9NT0RFX0ZMQUdfTlBJWERBVEEpCj4g PiA+ICsgICAgICAgICAgICAgICB2bS0+ZmxhZ3MgfD0gRElTUExBWV9GTEFHU19QSVhEQVRBX05F R0VER0U7Cj4gPiA+ICsgICAgICAgaWYgKGRtb2RlLT5mbGFncyAmIERSTV9NT0RFX0ZMQUdfUERF KQo+ID4gPiArICAgICAgICAgICAgICAgdm0tPmZsYWdzIHw9IERJU1BMQVlfRkxBR1NfREVfSElH SDsKPiA+ID4gKyAgICAgICBlbHNlIGlmIChkbW9kZS0+ZmxhZ3MgJiBEUk1fTU9ERV9GTEFHX05E RSkKPiA+ID4gKyAgICAgICAgICAgICAgIHZtLT5mbGFncyB8PSBESVNQTEFZX0ZMQUdTX0RFX0xP VzsKPiA+ID4gIH0KPiA+ID4gIEVYUE9SVF9TWU1CT0xfR1BMKGRybV9kaXNwbGF5X21vZGVfdG9f dmlkZW9tb2RlKTsKPiA+ID4KPiA+ID4gZGlmZiAtLWdpdCBhL2luY2x1ZGUvdWFwaS9kcm0vZHJt X21vZGUuaCBiL2luY2x1ZGUvdWFwaS9kcm0vZHJtX21vZGUuaAo+ID4gPiBpbmRleCBkM2UwZmUz Li5iMzM1YTE3IDEwMDY0NAo+ID4gPiAtLS0gYS9pbmNsdWRlL3VhcGkvZHJtL2RybV9tb2RlLmgK PiA+ID4gKysrIGIvaW5jbHVkZS91YXBpL2RybS9kcm1fbW9kZS5oCj4gPiA+IEBAIC04OSw2ICs4 OSwxMiBAQCBleHRlcm4gIkMiIHsKPiA+ID4gICNkZWZpbmUgIERSTV9NT0RFX0ZMQUdfM0RfVE9Q X0FORF9CT1RUT00gICAgICAgKDc8PDE0KQo+ID4gPiAgI2RlZmluZSAgRFJNX01PREVfRkxBR18z RF9TSURFX0JZX1NJREVfSEFMRiAgICAoODw8MTQpCj4gPiA+Cj4gPiA+ICsvKiBmbGFncyBmb3Ig cG9sYXJpdHkgY2xvY2sgJiBkYXRhIGVuYWJsZSBwb2xhcml0aWVzICovCj4gPiA+ICsjZGVmaW5l IERSTV9NT0RFX0ZMQUdfUFBJWERBVEEgICAgICAgICAgICAgICAgICgxIDw8IDE5KQo+ID4gPiAr I2RlZmluZSBEUk1fTU9ERV9GTEFHX05QSVhEQVRBICAgICAgICAgICAgICAgICAoMSA8PCAyMCkK PiA+ID4gKyNkZWZpbmUgRFJNX01PREVfRkxBR19QREUgICAgICAgICAgICAgICAgICAgICAgKDEg PDwgMjEpCj4gPiA+ICsjZGVmaW5lIERSTV9NT0RFX0ZMQUdfTkRFICAgICAgICAgICAgICAgICAg ICAgICgxIDw8IDIyKQo+ID4gPiArCj4gPiA+ICAvKiBQaWN0dXJlIGFzcGVjdCByYXRpbyBvcHRp b25zICovCj4gPiA+ICAjZGVmaW5lIERSTV9NT0RFX1BJQ1RVUkVfQVNQRUNUX05PTkUgICAgICAg ICAgIDAKPiA+ID4gICNkZWZpbmUgRFJNX01PREVfUElDVFVSRV9BU1BFQ1RfNF8zICAgICAgICAg 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with ESMTPSA id a3-v6sm847384ejr.55.2018.10.24.01.17.00 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Oct 2018 01:17:00 -0700 (PDT) Date: Wed, 24 Oct 2018 10:16:58 +0200 From: Daniel Vetter To: Benjamin Gaignard Cc: Yannick Fertre , Philippe Cornu , Benjamin GAIGNARD , Vincent Abriou , Gustavo Padovan , Maarten Lankhorst , sean@poorly.run, David Airlie , ML dri-devel , Linux Kernel Mailing List , Daniel Vetter Subject: Re: [PATCH v1 1/2] drm: Add missing flags for pixel clock & data enable Message-ID: <20181024081658.GD324@phenom.ffwll.local> Mail-Followup-To: Benjamin Gaignard , Yannick Fertre , Philippe Cornu , Benjamin GAIGNARD , Vincent Abriou , Gustavo Padovan , Maarten Lankhorst , sean@poorly.run, David Airlie , ML dri-devel , Linux Kernel Mailing List References: <1537788981-21479-1-git-send-email-yannick.fertre@st.com> <1537788981-21479-2-git-send-email-yannick.fertre@st.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: X-Operating-System: Linux phenom 4.18.0-2-amd64 User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Oct 23, 2018 at 04:50:19PM +0200, Benjamin Gaignard wrote: > Le lun. 15 oct. 2018 à 13:15, Benjamin Gaignard > a écrit : > > > > Le lun. 24 sept. 2018 à 13:59, Yannick Fertré a écrit : > > > > > > Add missing flags for pixel clock & data enable polarities. > > > These flags are similar to other synchronization signals (hsync, vsync...). > > > > > > Signed-off-by: Yannick Fertré > > > > Reviewed-by: Benjamin Gaignard > > Dave or Daniel could you give us your PoV on this patch ? Does it work? Iirc we had some userspace chocking on new mode flags, and needed explicit opt-in. If that looks good (check weston, -modesetting and drm_hwc, that should have you covered I hope) then has my ack. -Daniel > Thanks > > > > > > --- > > > drivers/gpu/drm/drm_modes.c | 19 ++++++++++++++++++- > > > include/uapi/drm/drm_mode.h | 6 ++++++ > > > 2 files changed, 24 insertions(+), 1 deletion(-) > > > > > > diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c > > > index 02db9ac..596f8b3 100644 > > > --- a/drivers/gpu/drm/drm_modes.c > > > +++ b/drivers/gpu/drm/drm_modes.c > > > @@ -130,7 +130,7 @@ EXPORT_SYMBOL(drm_mode_probed_add); > > > * according to the hdisplay, vdisplay, vrefresh. > > > * It is based from the VESA(TM) Coordinated Video Timing Generator by > > > * Graham Loveridge April 9, 2003 available at > > > - * http://www.elo.utfsm.cl/~elo212/docs/CVTd6r1.xls > > > + * http://www.elo.utfsm.cl/~elo212/docs/CVTd6r1.xls > > > * > > > * And it is copied from xf86CVTmode in xserver/hw/xfree86/modes/xf86cvt.c. > > > * What I have done is to translate it by using integer calculation. > > > @@ -611,6 +611,15 @@ void drm_display_mode_from_videomode(const struct videomode *vm, > > > dmode->flags |= DRM_MODE_FLAG_DBLSCAN; > > > if (vm->flags & DISPLAY_FLAGS_DOUBLECLK) > > > dmode->flags |= DRM_MODE_FLAG_DBLCLK; > > > + if (vm->flags & DISPLAY_FLAGS_PIXDATA_POSEDGE) > > > + dmode->flags |= DRM_MODE_FLAG_PPIXCLK; > > > + else if (vm->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE) > > > + dmode->flags |= DRM_MODE_FLAG_NPIXCLK; > > > + if (vm->flags & DISPLAY_FLAGS_DE_HIGH) > > > + dmode->flags |= DRM_MODE_FLAG_PDATAEN; > > > + else if (vm->flags & DISPLAY_FLAGS_DE_LOW) > > > + dmode->flags |= DRM_MODE_FLAG_NDE; > > > + > > > drm_mode_set_name(dmode); > > > } > > > EXPORT_SYMBOL_GPL(drm_display_mode_from_videomode); > > > @@ -652,6 +661,14 @@ void drm_display_mode_to_videomode(const struct drm_display_mode *dmode, > > > vm->flags |= DISPLAY_FLAGS_DOUBLESCAN; > > > if (dmode->flags & DRM_MODE_FLAG_DBLCLK) > > > vm->flags |= DISPLAY_FLAGS_DOUBLECLK; > > > + if (dmode->flags & DRM_MODE_FLAG_PPIXDATA) > > > + vm->flags |= DISPLAY_FLAGS_PIXDATA_POSEDGE; > > > + else if (dmode->flags & DRM_MODE_FLAG_NPIXDATA) > > > + vm->flags |= DISPLAY_FLAGS_PIXDATA_NEGEDGE; > > > + if (dmode->flags & DRM_MODE_FLAG_PDE) > > > + vm->flags |= DISPLAY_FLAGS_DE_HIGH; > > > + else if (dmode->flags & DRM_MODE_FLAG_NDE) > > > + vm->flags |= DISPLAY_FLAGS_DE_LOW; > > > } > > > EXPORT_SYMBOL_GPL(drm_display_mode_to_videomode); > > > > > > diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h > > > index d3e0fe3..b335a17 100644 > > > --- a/include/uapi/drm/drm_mode.h > > > +++ b/include/uapi/drm/drm_mode.h > > > @@ -89,6 +89,12 @@ extern "C" { > > > #define DRM_MODE_FLAG_3D_TOP_AND_BOTTOM (7<<14) > > > #define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF (8<<14) > > > > > > +/* flags for polarity clock & data enable polarities */ > > > +#define DRM_MODE_FLAG_PPIXDATA (1 << 19) > > > +#define DRM_MODE_FLAG_NPIXDATA (1 << 20) > > > +#define DRM_MODE_FLAG_PDE (1 << 21) > > > +#define DRM_MODE_FLAG_NDE (1 << 22) > > > + > > > /* Picture aspect ratio options */ > > > #define DRM_MODE_PICTURE_ASPECT_NONE 0 > > > #define DRM_MODE_PICTURE_ASPECT_4_3 1 > > > -- > > > 2.7.4 > > > > > > _______________________________________________ > > > dri-devel mailing list > > > dri-devel@lists.freedesktop.org > > > https://lists.freedesktop.org/mailman/listinfo/dri-devel > > > > -- > Benjamin Gaignard > > Graphic Study Group > > Linaro.org │ Open source software for ARM SoCs > > Follow Linaro: Facebook | Twitter | Blog -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch