diff for duplicates of <20181024220213.GA26789@bogus>

diff --git a/a/1.txt b/N1/1.txt
index bbc46d2..bd8ee3a 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -1,9 +1,9 @@
 On Tue, Oct 23, 2018 at 11:49:25AM +0000, A.s. Dong wrote:
-> The i.MX 7ULP family of processors represents NXP?s latest achievement
+> The i.MX 7ULP family of processors represents NXP’s latest achievement
 > in ultra-low-power processing for use cases demanding long battery life.
 > Targeted towards the growing market of portable devices, the i.MX 7ULP
-> family of processors features NXP's advanced implementation of the Arm?
-> Cortex?-A7 core, the Arm Cortex-M4 core, as well as a 3D and 2D Graphics
+> family of processors features NXP's advanced implementation of the Arm®
+> Cortex®-A7 core, the Arm Cortex-M4 core, as well as a 3D and 2D Graphics
 > Processing Units (GPUs).
 > 
 > This patch aims to add the initial support including:
@@ -15,7 +15,7 @@ On Tue, Oct 23, 2018 at 11:49:25AM +0000, A.s. Dong wrote:
 > 
 > Cc: Rob Herring <robh+dt@kernel.org>
 > Cc: Shawn Guo <shawnguo@kernel.org>
-> Cc: devicetree at vger.kernel.org
+> Cc: devicetree@vger.kernel.org
 > Cc: Sascha Hauer <kernel@pengutronix.de>
 > Cc: Fabio Estevam <fabio.estevam@nxp.com>
 > Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
@@ -73,14 +73,14 @@ On Tue, Oct 23, 2018 at 11:49:25AM +0000, A.s. Dong wrote:
 > +		#address-cells = <1>;
 > +		#size-cells = <0>;
 > +
-> +		cpu0: cpu at 0 {
+> +		cpu0: cpu@0 {
 > +			compatible = "arm,cortex-a7";
 > +			device_type = "cpu";
 > +			reg = <0>;
 > +		};
 > +	};
 > +
-> +	intc: interrupt-controller at 40021000 {
+> +	intc: interrupt-controller@40021000 {
 > +		compatible = "arm,cortex-a7-gic";
 > +		#interrupt-cells = <3>;
 > +		interrupt-controller;
@@ -149,14 +149,14 @@ I think enabled should be the norm.
 
 > +	};
 > +
-> +	ahbbridge0: bus at 40000000 {
+> +	ahbbridge0: bus@40000000 {
 > +		compatible = "simple-bus";
 > +		#address-cells = <1>;
 > +		#size-cells = <1>;
 > +		reg = <0x40000000 0x800000>;
 > +		ranges;
 > +
-> +		lpuart4: serial at 402d0000 {
+> +		lpuart4: serial@402d0000 {
 > +			compatible = "fsl,imx7ulp-lpuart";
 > +			reg = <0x402d0000 0x1000>;
 > +			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
@@ -168,7 +168,7 @@ I think enabled should be the norm.
 > +			status = "disabled";
 > +		};
 > +
-> +		lpuart5: serial at 402e0000 {
+> +		lpuart5: serial@402e0000 {
 > +			compatible = "fsl,imx7ulp-lpuart";
 > +			reg = <0x402e0000 0x1000>;
 > +			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
@@ -180,7 +180,7 @@ I think enabled should be the norm.
 > +			status = "disabled";
 > +		};
 > +
-> +		tpm5: tpm at 40260000 {
+> +		tpm5: tpm@40260000 {
 > +			compatible = "fsl,imx7ulp-tpm";
 > +			reg = <0x40260000 0x1000>;
 > +			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
@@ -189,9 +189,9 @@ I think enabled should be the norm.
 > +			clock-names = "ipg", "per";
 > +		};
 > +
-> +		usdhc0: usdhc at 40370000 {
+> +		usdhc0: usdhc@40370000 {
 
-mmc at ... is the standard name.
+mmc@... is the standard name.
 
 > +			compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc";
 > +			reg = <0x40370000 0x10000>;
@@ -208,7 +208,7 @@ mmc at ... is the standard name.
 > +			status = "disabled";
 > +		};
 > +
-> +		usdhc1: usdhc at 40380000 {
+> +		usdhc1: usdhc@40380000 {
 
 ditto.
 
@@ -227,9 +227,9 @@ ditto.
 > +			status = "disabled";
 > +		};
 > +
-> +		scg1: scg1 at 403e0000 {
+> +		scg1: scg1@403e0000 {
 
-clock-controller at ...
+clock-controller@...
 
 > +			compatible = "fsl,imx7ulp-scg1";
 > +			reg = <0x403e0000 0x10000>;
@@ -240,9 +240,9 @@ clock-controller at ...
 > +			#clock-cells = <1>;
 > +		};
 > +
-> +		pcc2: pcc2 at 403f0000 {
+> +		pcc2: pcc2@403f0000 {
 
-clock-controller at ...
+clock-controller@...
 
 > +			compatible = "fsl,imx7ulp-pcc2";
 > +			reg = <0x403f0000 0x10000>;
@@ -251,14 +251,14 @@ clock-controller at ...
 > +			assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
 > +		};
 > +
-> +		smc1: smc1 at 40410000 {
+> +		smc1: smc1@40410000 {
 > +			compatible = "fsl,imx7ulp-smc1";
 > +			reg = <0x40410000 0x1000>;
 > +		};
 > +
-> +		pcc3: pcc3 at 40b30000 {
+> +		pcc3: pcc3@40b30000 {
 
-clock-controller at ...
+clock-controller@...
 
 > +			compatible = "fsl,imx7ulp-pcc3";
 > +			reg = <0x40b30000 0x10000>;
@@ -266,16 +266,16 @@ clock-controller at ...
 > +		};
 > +	};
 > +
-> +	ahbbridge1: bus at 40800000 {
+> +	ahbbridge1: bus@40800000 {
 > +		compatible = "simple-bus";
 > +		#address-cells = <1>;
 > +		#size-cells = <1>;
 > +		reg = <0x40800000 0x800000>;
 > +		ranges;
 > +
-> +		lpi2c6: lpi2c at 40a40000 {
+> +		lpi2c6: lpi2c@40a40000 {
 
-i2c at ...
+i2c@...
 
 > +			compatible = "fsl,imx7ulp-lpi2c";
 > +			reg = <0x40a40000 0x10000>;
@@ -288,9 +288,9 @@ i2c at ...
 > +			status = "disabled";
 > +		};
 > +
-> +		lpi2c7: lpi2c at 40a50000 {
+> +		lpi2c7: lpi2c@40a50000 {
 
-i2c at ...
+i2c@...
 
 > +			compatible = "fsl,imx7ulp-lpi2c";
 > +			reg = <0x40a50000 0x10000>;
@@ -303,7 +303,7 @@ i2c at ...
 > +			status = "disabled";
 > +		};
 > +
-> +		lpuart6: serial at 40a60000 {
+> +		lpuart6: serial@40a60000 {
 > +			compatible = "fsl,imx7ulp-lpuart";
 > +			reg = <0x40a60000 0x1000>;
 > +			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
@@ -315,7 +315,7 @@ i2c at ...
 > +			status = "disabled";
 > +		};
 > +
-> +		lpuart7: serial at 40a70000 {
+> +		lpuart7: serial@40a70000 {
 > +			compatible = "fsl,imx7ulp-lpuart";
 > +			reg = <0x40a70000 0x1000>;
 > +			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
@@ -327,15 +327,15 @@ i2c at ...
 > +			status = "disabled";
 > +		};
 > +
-> +		iomuxc1: iomuxc at 40ac0000 {
+> +		iomuxc1: iomuxc@40ac0000 {
 
-pinctrl at ...
+pinctrl@...
 
 > +			compatible = "fsl,imx7ulp-iomuxc1";
 > +			reg = <0x40ac0000 0x1000>;
 > +		};
 > +
-> +		gpio_ptc: gpio at 40ae0000 {
+> +		gpio_ptc: gpio@40ae0000 {
 > +			compatible = "fsl,vf610-gpio";
 > +			reg = <0x40ae0000 0x1000 0x400f0000 0x40>;
 > +			gpio-controller;
@@ -349,7 +349,7 @@ pinctrl at ...
 > +			gpio-ranges = <&iomuxc1 0 0 32>;
 > +		};
 > +
-> +		gpio_ptd: gpio at 40af0000 {
+> +		gpio_ptd: gpio@40af0000 {
 > +			compatible = "fsl,vf610-gpio";
 > +			reg = <0x40af0000 0x1000 0x400f0040 0x40>;
 > +			gpio-controller;
@@ -363,7 +363,7 @@ pinctrl at ...
 > +			gpio-ranges = <&iomuxc1 0 32 32>;
 > +		};
 > +
-> +		gpio_pte: gpio at 40b00000 {
+> +		gpio_pte: gpio@40b00000 {
 > +			compatible = "fsl,vf610-gpio";
 > +			reg = <0x40b00000 0x1000 0x400f0080 0x40>;
 > +			gpio-controller;
@@ -377,7 +377,7 @@ pinctrl at ...
 > +			gpio-ranges = <&iomuxc1 0 64 32>;
 > +		};
 > +
-> +		gpio_ptf: gpio at 40b10000 {
+> +		gpio_ptf: gpio@40b10000 {
 > +			compatible = "fsl,vf610-gpio";
 > +			reg = <0x40b10000 0x1000 0x400f00c0 0x40>;
 > +			gpio-controller;
@@ -394,4 +394,9 @@ pinctrl at ...
 > +};
 > -- 
 > 2.7.4
->
+> 
+
+_______________________________________________
+linux-arm-kernel mailing list
+linux-arm-kernel@lists.infradead.org
+http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
diff --git a/a/content_digest b/N1/content_digest
index aec01f0..96776f8 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -1,17 +1,25 @@
  "ref\01540295058-26090-1-git-send-email-aisheng.dong@nxp.com\0"
  "ref\01540295058-26090-7-git-send-email-aisheng.dong@nxp.com\0"
- "From\0robh@kernel.org (Rob Herring)\0"
- "Subject\0[PATCH V2 6/8] dts: imx: add common imx7ulp dtsi support\0"
+ "From\0Rob Herring <robh@kernel.org>\0"
+ "Subject\0Re: [PATCH V2 6/8] dts: imx: add common imx7ulp dtsi support\0"
  "Date\0Wed, 24 Oct 2018 17:02:13 -0500\0"
- "To\0linux-arm-kernel@lists.infradead.org\0"
+ "To\0A.s. Dong <aisheng.dong@nxp.com>\0"
+ "Cc\0devicetree@vger.kernel.org <devicetree@vger.kernel.org>"
+  dongas86@gmail.com <dongas86@gmail.com>
+  linux@armlinux.org.uk <linux@armlinux.org.uk>
+  dl-linux-imx <linux-imx@nxp.com>
+  kernel@pengutronix.de <kernel@pengutronix.de>
+  Fabio Estevam <fabio.estevam@nxp.com>
+  shawnguo@kernel.org <shawnguo@kernel.org>
+ " linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org>\0"
  "\00:1\0"
  "b\0"
  "On Tue, Oct 23, 2018 at 11:49:25AM +0000, A.s. Dong wrote:\n"
- "> The i.MX 7ULP family of processors represents NXP?s latest achievement\n"
+ "> The i.MX 7ULP family of processors represents NXP\342\200\231s latest achievement\n"
  "> in ultra-low-power processing for use cases demanding long battery life.\n"
  "> Targeted towards the growing market of portable devices, the i.MX 7ULP\n"
- "> family of processors features NXP's advanced implementation of the Arm?\n"
- "> Cortex?-A7 core, the Arm Cortex-M4 core, as well as a 3D and 2D Graphics\n"
+ "> family of processors features NXP's advanced implementation of the Arm\302\256\n"
+ "> Cortex\302\256-A7 core, the Arm Cortex-M4 core, as well as a 3D and 2D Graphics\n"
  "> Processing Units (GPUs).\n"
  "> \n"
  "> This patch aims to add the initial support including:\n"
@@ -23,7 +31,7 @@
  "> \n"
  "> Cc: Rob Herring <robh+dt@kernel.org>\n"
  "> Cc: Shawn Guo <shawnguo@kernel.org>\n"
- "> Cc: devicetree at vger.kernel.org\n"
+ "> Cc: devicetree@vger.kernel.org\n"
  "> Cc: Sascha Hauer <kernel@pengutronix.de>\n"
  "> Cc: Fabio Estevam <fabio.estevam@nxp.com>\n"
  "> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>\n"
@@ -81,14 +89,14 @@
  "> +\t\t#address-cells = <1>;\n"
  "> +\t\t#size-cells = <0>;\n"
  "> +\n"
- "> +\t\tcpu0: cpu at 0 {\n"
+ "> +\t\tcpu0: cpu@0 {\n"
  "> +\t\t\tcompatible = \"arm,cortex-a7\";\n"
  "> +\t\t\tdevice_type = \"cpu\";\n"
  "> +\t\t\treg = <0>;\n"
  "> +\t\t};\n"
  "> +\t};\n"
  "> +\n"
- "> +\tintc: interrupt-controller at 40021000 {\n"
+ "> +\tintc: interrupt-controller@40021000 {\n"
  "> +\t\tcompatible = \"arm,cortex-a7-gic\";\n"
  "> +\t\t#interrupt-cells = <3>;\n"
  "> +\t\tinterrupt-controller;\n"
@@ -157,14 +165,14 @@
  "\n"
  "> +\t};\n"
  "> +\n"
- "> +\tahbbridge0: bus at 40000000 {\n"
+ "> +\tahbbridge0: bus@40000000 {\n"
  "> +\t\tcompatible = \"simple-bus\";\n"
  "> +\t\t#address-cells = <1>;\n"
  "> +\t\t#size-cells = <1>;\n"
  "> +\t\treg = <0x40000000 0x800000>;\n"
  "> +\t\tranges;\n"
  "> +\n"
- "> +\t\tlpuart4: serial at 402d0000 {\n"
+ "> +\t\tlpuart4: serial@402d0000 {\n"
  "> +\t\t\tcompatible = \"fsl,imx7ulp-lpuart\";\n"
  "> +\t\t\treg = <0x402d0000 0x1000>;\n"
  "> +\t\t\tinterrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;\n"
@@ -176,7 +184,7 @@
  "> +\t\t\tstatus = \"disabled\";\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tlpuart5: serial at 402e0000 {\n"
+ "> +\t\tlpuart5: serial@402e0000 {\n"
  "> +\t\t\tcompatible = \"fsl,imx7ulp-lpuart\";\n"
  "> +\t\t\treg = <0x402e0000 0x1000>;\n"
  "> +\t\t\tinterrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;\n"
@@ -188,7 +196,7 @@
  "> +\t\t\tstatus = \"disabled\";\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\ttpm5: tpm at 40260000 {\n"
+ "> +\t\ttpm5: tpm@40260000 {\n"
  "> +\t\t\tcompatible = \"fsl,imx7ulp-tpm\";\n"
  "> +\t\t\treg = <0x40260000 0x1000>;\n"
  "> +\t\t\tinterrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;\n"
@@ -197,9 +205,9 @@
  "> +\t\t\tclock-names = \"ipg\", \"per\";\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tusdhc0: usdhc at 40370000 {\n"
+ "> +\t\tusdhc0: usdhc@40370000 {\n"
  "\n"
- "mmc at ... is the standard name.\n"
+ "mmc@... is the standard name.\n"
  "\n"
  "> +\t\t\tcompatible = \"fsl,imx7ulp-usdhc\", \"fsl,imx6sx-usdhc\";\n"
  "> +\t\t\treg = <0x40370000 0x10000>;\n"
@@ -216,7 +224,7 @@
  "> +\t\t\tstatus = \"disabled\";\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tusdhc1: usdhc at 40380000 {\n"
+ "> +\t\tusdhc1: usdhc@40380000 {\n"
  "\n"
  "ditto.\n"
  "\n"
@@ -235,9 +243,9 @@
  "> +\t\t\tstatus = \"disabled\";\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tscg1: scg1 at 403e0000 {\n"
+ "> +\t\tscg1: scg1@403e0000 {\n"
  "\n"
- "clock-controller at ...\n"
+ "clock-controller@...\n"
  "\n"
  "> +\t\t\tcompatible = \"fsl,imx7ulp-scg1\";\n"
  "> +\t\t\treg = <0x403e0000 0x10000>;\n"
@@ -248,9 +256,9 @@
  "> +\t\t\t#clock-cells = <1>;\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tpcc2: pcc2 at 403f0000 {\n"
+ "> +\t\tpcc2: pcc2@403f0000 {\n"
  "\n"
- "clock-controller at ...\n"
+ "clock-controller@...\n"
  "\n"
  "> +\t\t\tcompatible = \"fsl,imx7ulp-pcc2\";\n"
  "> +\t\t\treg = <0x403f0000 0x10000>;\n"
@@ -259,14 +267,14 @@
  "> +\t\t\tassigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tsmc1: smc1 at 40410000 {\n"
+ "> +\t\tsmc1: smc1@40410000 {\n"
  "> +\t\t\tcompatible = \"fsl,imx7ulp-smc1\";\n"
  "> +\t\t\treg = <0x40410000 0x1000>;\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tpcc3: pcc3 at 40b30000 {\n"
+ "> +\t\tpcc3: pcc3@40b30000 {\n"
  "\n"
- "clock-controller at ...\n"
+ "clock-controller@...\n"
  "\n"
  "> +\t\t\tcompatible = \"fsl,imx7ulp-pcc3\";\n"
  "> +\t\t\treg = <0x40b30000 0x10000>;\n"
@@ -274,16 +282,16 @@
  "> +\t\t};\n"
  "> +\t};\n"
  "> +\n"
- "> +\tahbbridge1: bus at 40800000 {\n"
+ "> +\tahbbridge1: bus@40800000 {\n"
  "> +\t\tcompatible = \"simple-bus\";\n"
  "> +\t\t#address-cells = <1>;\n"
  "> +\t\t#size-cells = <1>;\n"
  "> +\t\treg = <0x40800000 0x800000>;\n"
  "> +\t\tranges;\n"
  "> +\n"
- "> +\t\tlpi2c6: lpi2c at 40a40000 {\n"
+ "> +\t\tlpi2c6: lpi2c@40a40000 {\n"
  "\n"
- "i2c at ...\n"
+ "i2c@...\n"
  "\n"
  "> +\t\t\tcompatible = \"fsl,imx7ulp-lpi2c\";\n"
  "> +\t\t\treg = <0x40a40000 0x10000>;\n"
@@ -296,9 +304,9 @@
  "> +\t\t\tstatus = \"disabled\";\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tlpi2c7: lpi2c at 40a50000 {\n"
+ "> +\t\tlpi2c7: lpi2c@40a50000 {\n"
  "\n"
- "i2c at ...\n"
+ "i2c@...\n"
  "\n"
  "> +\t\t\tcompatible = \"fsl,imx7ulp-lpi2c\";\n"
  "> +\t\t\treg = <0x40a50000 0x10000>;\n"
@@ -311,7 +319,7 @@
  "> +\t\t\tstatus = \"disabled\";\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tlpuart6: serial at 40a60000 {\n"
+ "> +\t\tlpuart6: serial@40a60000 {\n"
  "> +\t\t\tcompatible = \"fsl,imx7ulp-lpuart\";\n"
  "> +\t\t\treg = <0x40a60000 0x1000>;\n"
  "> +\t\t\tinterrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;\n"
@@ -323,7 +331,7 @@
  "> +\t\t\tstatus = \"disabled\";\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tlpuart7: serial at 40a70000 {\n"
+ "> +\t\tlpuart7: serial@40a70000 {\n"
  "> +\t\t\tcompatible = \"fsl,imx7ulp-lpuart\";\n"
  "> +\t\t\treg = <0x40a70000 0x1000>;\n"
  "> +\t\t\tinterrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;\n"
@@ -335,15 +343,15 @@
  "> +\t\t\tstatus = \"disabled\";\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tiomuxc1: iomuxc at 40ac0000 {\n"
+ "> +\t\tiomuxc1: iomuxc@40ac0000 {\n"
  "\n"
- "pinctrl at ...\n"
+ "pinctrl@...\n"
  "\n"
  "> +\t\t\tcompatible = \"fsl,imx7ulp-iomuxc1\";\n"
  "> +\t\t\treg = <0x40ac0000 0x1000>;\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tgpio_ptc: gpio at 40ae0000 {\n"
+ "> +\t\tgpio_ptc: gpio@40ae0000 {\n"
  "> +\t\t\tcompatible = \"fsl,vf610-gpio\";\n"
  "> +\t\t\treg = <0x40ae0000 0x1000 0x400f0000 0x40>;\n"
  "> +\t\t\tgpio-controller;\n"
@@ -357,7 +365,7 @@
  "> +\t\t\tgpio-ranges = <&iomuxc1 0 0 32>;\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tgpio_ptd: gpio at 40af0000 {\n"
+ "> +\t\tgpio_ptd: gpio@40af0000 {\n"
  "> +\t\t\tcompatible = \"fsl,vf610-gpio\";\n"
  "> +\t\t\treg = <0x40af0000 0x1000 0x400f0040 0x40>;\n"
  "> +\t\t\tgpio-controller;\n"
@@ -371,7 +379,7 @@
  "> +\t\t\tgpio-ranges = <&iomuxc1 0 32 32>;\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tgpio_pte: gpio at 40b00000 {\n"
+ "> +\t\tgpio_pte: gpio@40b00000 {\n"
  "> +\t\t\tcompatible = \"fsl,vf610-gpio\";\n"
  "> +\t\t\treg = <0x40b00000 0x1000 0x400f0080 0x40>;\n"
  "> +\t\t\tgpio-controller;\n"
@@ -385,7 +393,7 @@
  "> +\t\t\tgpio-ranges = <&iomuxc1 0 64 32>;\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tgpio_ptf: gpio at 40b10000 {\n"
+ "> +\t\tgpio_ptf: gpio@40b10000 {\n"
  "> +\t\t\tcompatible = \"fsl,vf610-gpio\";\n"
  "> +\t\t\treg = <0x40b10000 0x1000 0x400f00c0 0x40>;\n"
  "> +\t\t\tgpio-controller;\n"
@@ -402,6 +410,11 @@
  "> +};\n"
  "> -- \n"
  "> 2.7.4\n"
- >
+ "> \n"
+ "\n"
+ "_______________________________________________\n"
+ "linux-arm-kernel mailing list\n"
+ "linux-arm-kernel@lists.infradead.org\n"
+ http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
 
-15909cd4d7bb068b01e4286c83c196fb6c5e09ea9a2c753fd7b009bcc1435f40
+efb279b8f53055802ab3a6baccdf1b2730fd5718fbc4a2c597eddcafbfc2d4d2
