From mboxrd@z Thu Jan 1 00:00:00 1970 From: Zhenyu Wang Subject: Re: [PULL] gvt-next-fixes for 4.20 Date: Fri, 26 Oct 2018 14:43:20 +0800 Message-ID: <20181026064320.GC22842@zhen-hp.sh.intel.com> References: <20181023034658.GU4714@zhen-hp.sh.intel.com> <154047283464.4519.17775741336888895862@jlahtine-desk.ger.corp.intel.com> Reply-To: Zhenyu Wang Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0870516252==" Return-path: In-Reply-To: <154047283464.4519.17775741336888895862@jlahtine-desk.ger.corp.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Joonas Lahtinen Cc: Jani Nikula , intel-gfx , "Yuan, Hang" , "Lv, Zhiyuan" , "Vivi, Rodrigo" , intel-gvt-dev List-Id: intel-gfx@lists.freedesktop.org --===============0870516252== Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="rJwd6BRFiFCcLxzm" Content-Disposition: inline --rJwd6BRFiFCcLxzm Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On 2018.10.25 16:07:14 +0300, Joonas Lahtinen wrote: > Quoting Zhenyu Wang (2018-10-23 06:46:59) > >=20 > > Hi, > >=20 > > Here's gvt-next-fixes for 4.20 with three changes. Mostly > > to fix possible arbitrary update on guest GGTT entry and > > with proper invalidate of old entry. Another one for one > > chicken reg mask fix. > >=20 > > thanks >=20 > Hi, >=20 > DIM seems to be (rightfully) complaining about one commit: >=20 > 3e740f0ec37acecaa364c19d2d2826df83c8bf20 is lacking committer of sign-off >=20 > Probably better if you re-submit the PR for -fixes (rebased for > v4.20-rc1). >=20 Looks -fixes is still 4.19? So I still regenerate against -next-fixes, let me know if that's ok for you. Thanks -- The following changes since commit 835fe6d75d14c1513910ed7f5665127fee12acc8: firmware/dmc/icl: Add missing MODULE_FIRMWARE() for Icelake. (2018-10-18 = 10:36:10 +0300) are available in the Git repository at: https://github.com/intel/gvt-linux.git tags/gvt-next-fixes-2018-10-26 for you to fetch changes up to 348589205265049eda2e365371eec18d56809699: drm/i915/gvt: correct mask setting for CSFE_CHICKEN1 (2018-10-26 10:57:48= +0800) ---------------------------------------------------------------- gvt-next-fixes-2018-10-26 - Fix invalidate of old ggtt entry (Hang) - Fix partial ggtt entry update in any order (Hang) - Fix one mask setting for chicken reg (Xinyun) ---------------------------------------------------------------- Hang Yuan (2): drm/i915/gvt: invalidate old ggtt page when update ggtt entry drm/i915/gvt: support inconsecutive partial gtt entry write Xinyun Liu (1): drm/i915/gvt: correct mask setting for CSFE_CHICKEN1 drivers/gpu/drm/i915/gvt/gtt.c | 115 ++++++++++++++++------------= ---- drivers/gpu/drm/i915/gvt/gtt.h | 9 ++- drivers/gpu/drm/i915/gvt/mmio_context.c | 2 +- 3 files changed, 66 insertions(+), 60 deletions(-) --=20 Open Source Technology Center, Intel ltd. $gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827 --rJwd6BRFiFCcLxzm Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iF0EARECAB0WIQTXuabgHDW6LPt9CICxBBozTXgYJwUCW9K3iAAKCRCxBBozTXgY J2wkAJ4v2kChSUYwiweB/KaZCPQfuw5vbgCbBPk7sTwIIte0332JJ4g2/zJtPgc= =YFEV -----END PGP SIGNATURE----- --rJwd6BRFiFCcLxzm-- --===============0870516252== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KSW50ZWwtZ2Z4 IG1haWxpbmcgbGlzdApJbnRlbC1nZnhAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlz dHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vaW50ZWwtZ2Z4Cg== --===============0870516252==--