From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [01/10] dt-bindings: usb: add support for dwc3 controller on HiSilicon SoCs From: Yu Chen Message-Id: <20181027095820.40056-2-chenyu56@huawei.com> Date: Sat, 27 Oct 2018 17:58:11 +0800 To: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: suzhuangluan@hisilicon.com, kongfei@hisilicon.com, Yu Chen , Greg Kroah-Hartman , Rob Herring , Mark Rutland , John Stultz List-ID: VGhpcyBwYXRjaCBhZGRzIGJpbmRpbmcgZGVzY3JpcHRpb25zIHRvIHN1cHBvcnQgdGhlIGR3YzMg Y29udHJvbGxlcgpvbiBIaVNpbGljb24gU29DcyBhbmQgYm9hcmRzIGxpa2UgdGhlIEhpS2V5OTYw LgoKQ2M6IEdyZWcgS3JvYWgtSGFydG1hbiA8Z3JlZ2toQGxpbnV4Zm91bmRhdGlvbi5vcmc+CkNj OiBSb2IgSGVycmluZyA8cm9iaCtkdEBrZXJuZWwub3JnPgpDYzogTWFyayBSdXRsYW5kIDxtYXJr LnJ1dGxhbmRAYXJtLmNvbT4KQ2M6IEpvaG4gU3R1bHR6IDxqb2huLnN0dWx0ekBsaW5hcm8ub3Jn PgpTaWduZWQtb2ZmLWJ5OiBZdSBDaGVuIDxjaGVueXU1NkBodWF3ZWkuY29tPgotLS0KIC4uLi9k ZXZpY2V0cmVlL2JpbmRpbmdzL3VzYi9kd2MzLWhpc2kudHh0ICAgICAgICAgIHwgNTMgKysrKysr KysrKysrKysrKysrKysrKwogMSBmaWxlIGNoYW5nZWQsIDUzIGluc2VydGlvbnMoKykKIGNyZWF0 ZSBtb2RlIDEwMDY0NCBEb2N1bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGluZ3MvdXNiL2R3YzMt aGlzaS50eHQKCmRpZmYgLS1naXQgYS9Eb2N1bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGluZ3Mv dXNiL2R3YzMtaGlzaS50eHQgYi9Eb2N1bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGluZ3MvdXNi L2R3YzMtaGlzaS50eHQKbmV3IGZpbGUgbW9kZSAxMDA2NDQKaW5kZXggMDAwMDAwMDAwMDAwLi5l NzE1ZTdiMWMzMjQKLS0tIC9kZXYvbnVsbAorKysgYi9Eb2N1bWVudGF0aW9uL2RldmljZXRyZWUv YmluZGluZ3MvdXNiL2R3YzMtaGlzaS50eHQKQEAgLTAsMCArMSw1MyBAQAorSGlTaWxpY29uIERX QzMgVVNCIFNvQyBjb250cm9sbGVyCisKK1RoaXMgZmlsZSBkb2N1bWVudHMgdGhlIHBhcmFtZXRl cnMgZm9yIHRoZSBkd2MzLWhpc2kgZHJpdmVyLgorCitSZXF1aXJlZCBwcm9wZXJ0aWVzOgorLSBj b21wYXRpYmxlOglzaG91bGQgYmUgImhpc2lsaWNvbixoaTM2NjAtZHdjMyIKKy0gY2xvY2tzOglB IGxpc3Qgb2YgcGhhbmRsZSArIGNsb2NrLXNwZWNpZmllciBwYWlycyBmb3IgdGhlCisJCWNsb2Nr cyBsaXN0ZWQgaW4gY2xvY2stbmFtZXMKKy0gY2xvY2stbmFtZXM6CVNwZWNpZnkgY2xvY2sgbmFt ZXMKKy0gcmVzZXRzOglsaXN0IG9mIHBoYW5kbGUgYW5kIHJlc2V0IHNwZWNpZmllciBwYWlycy4K KworU3ViLW5vZGVzOgorVGhlIGR3YzMgY29yZSBzaG91bGQgYmUgYWRkZWQgYXMgc3Vibm9kZSB0 byBIaVNpbGljb24gRFdDMyBhcyBzaG93biBpbiB0aGUKK2V4YW1wbGUgYmVsb3cuIFRoZSBEVCBi aW5kaW5nIGRldGFpbHMgb2YgZHdjMyBjYW4gYmUgZm91bmQgaW46CitEb2N1bWVudGF0aW9uL2Rl dmljZXRyZWUvYmluZGluZ3MvdXNiL2R3YzMudHh0CisKK0V4YW1wbGU6CisJdXNiMzogaGlzaV9k d2MzIHsKKwkJY29tcGF0aWJsZSA9ICJoaXNpbGljb24saGkzNjYwLWR3YzMiOworCQkjYWRkcmVz cy1jZWxscyA9IDwyPjsKKwkJI3NpemUtY2VsbHMgPSA8Mj47CisJCXJhbmdlczsKKworCQljbG9j a3MgPSA8JmNyZ19jdHJsIEhJMzY2MF9DTEtfQUJCX1VTQj4sCisJCQkgPCZjcmdfY3RybCBISTM2 NjBfQUNMS19HQVRFX1VTQjNPVEc+OworCQljbG9jay1uYW1lcyA9ICJjbGtfdXNiM3BoeV9yZWYi LCAiYWNsa191c2Izb3RnIjsKKwkJYXNzaWduZWQtY2xvY2tzID0gPCZjcmdfY3RybCBISTM2NjBf QUNMS19HQVRFX1VTQjNPVEc+OworCQlhc3NpZ25lZC1jbG9jay1yYXRlcyA9IDwyMjkwMDAwMDA+ OworCQlyZXNldHMgPSA8JmNyZ19yc3QgMHg5MCA4PiwKKwkJCSA8JmNyZ19yc3QgMHg5MCA3PiwK KwkJCSA8JmNyZ19yc3QgMHg5MCA2PiwKKwkJCSA8JmNyZ19yc3QgMHg5MCA1PjsKKworCQlkd2Mz OiBkd2MzQGZmMTAwMDAwIHsKKwkJCWNvbXBhdGlibGUgPSAic25wcyxkd2MzIjsKKwkJCXJlZyA9 IDwweDAgMHhmZjEwMDAwMCAweDAgMHgxMDAwMDA+OworCQkJaW50ZXJydXB0cyA9IDwwIDE1OSA0 PiwgPDAgMTYxIDQ+OworCQkJcGh5cyA9IDwmdXNiX3BoeT47CisJCQlwaHktbmFtZXMgPSAidXNi My1waHkiOworCQkJZHJfbW9kZSA9ICJvdGciOworCQkJbWF4aW11bS1zcGVlZCA9ICJzdXBlci1z cGVlZCI7CisJCQlwaHlfdHlwZSA9ICJ1dG1pIjsKKwkJCXNucHMsZGlzLWRlbC1waHktcG93ZXIt Y2hnLXF1aXJrOworCQkJc25wcyxsZnBzX2ZpbHRlcl9xdWlyazsKKwkJCXNucHMsZGlzX3UyX3N1 c3BoeV9xdWlyazsKKwkJCXNucHMsZGlzX3UzX3N1c3BoeV9xdWlyazsKKwkJCXNucHMsdHhfZGVf ZW1waGFzaXNfcXVpcms7CisJCQlzbnBzLHR4X2RlX2VtcGhhc2lzID0gPDE+OworCQkJc25wcyxk aXNfZW5ibHNscG1fcXVpcms7CisJCQlzbnBzLGdjdGwtcmVzZXQtcXVpcms7CisJCQlleHRjb24g PSA8Jmhpc2lfaGlrZXlfdXNiPjsKKwkJfTsKKwl9Owo= From mboxrd@z Thu Jan 1 00:00:00 1970 From: Yu Chen Subject: [PATCH 01/10] dt-bindings: usb: add support for dwc3 controller on HiSilicon SoCs Date: Sat, 27 Oct 2018 17:58:11 +0800 Message-ID: <20181027095820.40056-2-chenyu56@huawei.com> References: <20181027095820.40056-1-chenyu56@huawei.com> Mime-Version: 1.0 Content-Type: text/plain Return-path: In-Reply-To: <20181027095820.40056-1-chenyu56@huawei.com> Sender: linux-kernel-owner@vger.kernel.org To: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: suzhuangluan@hisilicon.com, kongfei@hisilicon.com, Yu Chen , Greg Kroah-Hartman , Rob Herring , Mark Rutland , John Stultz List-Id: devicetree@vger.kernel.org This patch adds binding descriptions to support the dwc3 controller on HiSilicon SoCs and boards like the HiKey960. Cc: Greg Kroah-Hartman Cc: Rob Herring Cc: Mark Rutland Cc: John Stultz Signed-off-by: Yu Chen --- .../devicetree/bindings/usb/dwc3-hisi.txt | 53 ++++++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/dwc3-hisi.txt diff --git a/Documentation/devicetree/bindings/usb/dwc3-hisi.txt b/Documentation/devicetree/bindings/usb/dwc3-hisi.txt new file mode 100644 index 000000000000..e715e7b1c324 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/dwc3-hisi.txt @@ -0,0 +1,53 @@ +HiSilicon DWC3 USB SoC controller + +This file documents the parameters for the dwc3-hisi driver. + +Required properties: +- compatible: should be "hisilicon,hi3660-dwc3" +- clocks: A list of phandle + clock-specifier pairs for the + clocks listed in clock-names +- clock-names: Specify clock names +- resets: list of phandle and reset specifier pairs. + +Sub-nodes: +The dwc3 core should be added as subnode to HiSilicon DWC3 as shown in the +example below. The DT binding details of dwc3 can be found in: +Documentation/devicetree/bindings/usb/dwc3.txt + +Example: + usb3: hisi_dwc3 { + compatible = "hisilicon,hi3660-dwc3"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&crg_ctrl HI3660_CLK_ABB_USB>, + <&crg_ctrl HI3660_ACLK_GATE_USB3OTG>; + clock-names = "clk_usb3phy_ref", "aclk_usb3otg"; + assigned-clocks = <&crg_ctrl HI3660_ACLK_GATE_USB3OTG>; + assigned-clock-rates = <229000000>; + resets = <&crg_rst 0x90 8>, + <&crg_rst 0x90 7>, + <&crg_rst 0x90 6>, + <&crg_rst 0x90 5>; + + dwc3: dwc3@ff100000 { + compatible = "snps,dwc3"; + reg = <0x0 0xff100000 0x0 0x100000>; + interrupts = <0 159 4>, <0 161 4>; + phys = <&usb_phy>; + phy-names = "usb3-phy"; + dr_mode = "otg"; + maximum-speed = "super-speed"; + phy_type = "utmi"; + snps,dis-del-phy-power-chg-quirk; + snps,lfps_filter_quirk; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + snps,tx_de_emphasis_quirk; + snps,tx_de_emphasis = <1>; + snps,dis_enblslpm_quirk; + snps,gctl-reset-quirk; + extcon = <&hisi_hikey_usb>; + }; + }; -- 2.15.0-rc2 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id ECB5EECDE44 for ; Sat, 27 Oct 2018 10:00:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id BF37D20869 for ; Sat, 27 Oct 2018 10:00:03 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org BF37D20869 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=huawei.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728480AbeJ0SkZ (ORCPT ); Sat, 27 Oct 2018 14:40:25 -0400 Received: from szxga07-in.huawei.com ([45.249.212.35]:46128 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1728337AbeJ0SkZ (ORCPT ); Sat, 27 Oct 2018 14:40:25 -0400 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 349935D1EAD16; Sat, 27 Oct 2018 17:59:57 +0800 (CST) Received: from vm100-107-113-134.huawei.com (100.107.113.134) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.408.0; Sat, 27 Oct 2018 17:59:47 +0800 From: Yu Chen To: , , CC: , , Yu Chen , Greg Kroah-Hartman , "Rob Herring" , Mark Rutland , "John Stultz" Subject: [PATCH 01/10] dt-bindings: usb: add support for dwc3 controller on HiSilicon SoCs Date: Sat, 27 Oct 2018 17:58:11 +0800 Message-ID: <20181027095820.40056-2-chenyu56@huawei.com> X-Mailer: git-send-email 2.15.0-rc2 In-Reply-To: <20181027095820.40056-1-chenyu56@huawei.com> References: <20181027095820.40056-1-chenyu56@huawei.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [100.107.113.134] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch adds binding descriptions to support the dwc3 controller on HiSilicon SoCs and boards like the HiKey960. Cc: Greg Kroah-Hartman Cc: Rob Herring Cc: Mark Rutland Cc: John Stultz Signed-off-by: Yu Chen --- .../devicetree/bindings/usb/dwc3-hisi.txt | 53 ++++++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/dwc3-hisi.txt diff --git a/Documentation/devicetree/bindings/usb/dwc3-hisi.txt b/Documentation/devicetree/bindings/usb/dwc3-hisi.txt new file mode 100644 index 000000000000..e715e7b1c324 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/dwc3-hisi.txt @@ -0,0 +1,53 @@ +HiSilicon DWC3 USB SoC controller + +This file documents the parameters for the dwc3-hisi driver. + +Required properties: +- compatible: should be "hisilicon,hi3660-dwc3" +- clocks: A list of phandle + clock-specifier pairs for the + clocks listed in clock-names +- clock-names: Specify clock names +- resets: list of phandle and reset specifier pairs. + +Sub-nodes: +The dwc3 core should be added as subnode to HiSilicon DWC3 as shown in the +example below. The DT binding details of dwc3 can be found in: +Documentation/devicetree/bindings/usb/dwc3.txt + +Example: + usb3: hisi_dwc3 { + compatible = "hisilicon,hi3660-dwc3"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&crg_ctrl HI3660_CLK_ABB_USB>, + <&crg_ctrl HI3660_ACLK_GATE_USB3OTG>; + clock-names = "clk_usb3phy_ref", "aclk_usb3otg"; + assigned-clocks = <&crg_ctrl HI3660_ACLK_GATE_USB3OTG>; + assigned-clock-rates = <229000000>; + resets = <&crg_rst 0x90 8>, + <&crg_rst 0x90 7>, + <&crg_rst 0x90 6>, + <&crg_rst 0x90 5>; + + dwc3: dwc3@ff100000 { + compatible = "snps,dwc3"; + reg = <0x0 0xff100000 0x0 0x100000>; + interrupts = <0 159 4>, <0 161 4>; + phys = <&usb_phy>; + phy-names = "usb3-phy"; + dr_mode = "otg"; + maximum-speed = "super-speed"; + phy_type = "utmi"; + snps,dis-del-phy-power-chg-quirk; + snps,lfps_filter_quirk; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + snps,tx_de_emphasis_quirk; + snps,tx_de_emphasis = <1>; + snps,dis_enblslpm_quirk; + snps,gctl-reset-quirk; + extcon = <&hisi_hikey_usb>; + }; + }; -- 2.15.0-rc2