From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [05/10] usb: dwc3: Add two quirks for Hisilicon Kirin Soc Platform From: Yu Chen Message-Id: <20181027095820.40056-6-chenyu56@huawei.com> Date: Sat, 27 Oct 2018 17:58:15 +0800 To: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: suzhuangluan@hisilicon.com, kongfei@hisilicon.com, Yu Chen , Felipe Balbi , Greg Kroah-Hartman , John Stultz , Binghui Wang List-ID: VGhlcmUgYXJlIHRvdyBxdWlya3MgZm9yIERlc2lnbldhcmUgVVNCMyBEUkQgQ29yZSBvZiBIaXNp bGljb24gS2lyaW4gU29jLgoxKVNQTElUX0JPVU5EQVJZX0RJU0FCTEUgc2hvdWxkIGJlIHNldCBm b3IgSG9zdCBtb2RlCjIpQSBHQ1RMIHNvZnQgcmVzZXQgc2hvdWxkIGJlIGV4ZWN1dGVkIHdoZW4g c3dpdGNoIG1vZGUKCkNjOiBGZWxpcGUgQmFsYmkgPGJhbGJpQGtlcm5lbC5vcmc+CkNjOiBHcmVn IEtyb2FoLUhhcnRtYW4gPGdyZWdraEBsaW51eGZvdW5kYXRpb24ub3JnPgpDYzogSm9obiBTdHVs dHogPGpvaG4uc3R1bHR6QGxpbmFyby5vcmc+CkNjOiBCaW5naHVpIFdhbmcgPHdhbmdiaW5naHVp QGhpc2lsaWNvbi5jb20+ClNpZ25lZC1vZmYtYnk6IFl1IENoZW4gPGNoZW55dTU2QGh1YXdlaS5j b20+Ci0tLQogZHJpdmVycy91c2IvZHdjMy9jb3JlLmMgICB8IDQzICsrKysrKysrKysrKysrKysr KysrKysrKysrKysrKysrKysrKysrKysrKysKIGRyaXZlcnMvdXNiL2R3YzMvY29yZS5oICAgfCAg NyArKysrKysrCiBkcml2ZXJzL3VzYi9kd2MzL2dhZGdldC5jIHwgIDIgKy0KIDMgZmlsZXMgY2hh bmdlZCwgNTEgaW5zZXJ0aW9ucygrKSwgMSBkZWxldGlvbigtKQoKZGlmZiAtLWdpdCBhL2RyaXZl cnMvdXNiL2R3YzMvY29yZS5jIGIvZHJpdmVycy91c2IvZHdjMy9jb3JlLmMKaW5kZXggYmVjZmJi ODdmNzkxLi42OGMyOWU1NDliZmIgMTAwNjQ0Ci0tLSBhL2RyaXZlcnMvdXNiL2R3YzMvY29yZS5j CisrKyBiL2RyaXZlcnMvdXNiL2R3YzMvY29yZS5jCkBAIC0xMTEsMTEgKzExMSwyNSBAQCB2b2lk IGR3YzNfc2V0X3BydGNhcChzdHJ1Y3QgZHdjMyAqZHdjLCB1MzIgbW9kZSkKIAlkd2MtPmN1cnJl bnRfZHJfcm9sZSA9IG1vZGU7CiB9CiAKK3N0YXRpYyB2b2lkIGR3YzNfZ2N0bF9jb3JlX3NvZnRf cmVzZXQoc3RydWN0IGR3YzMgKmR3YykKK3sKKwlpbnQgcmVnOworCisJcmVnID0gZHdjM19yZWFk bChkd2MtPnJlZ3MsIERXQzNfR0NUTCk7CisJcmVnIHw9IChEV0MzX0dDVExfQ09SRVNPRlRSRVNF VCk7CisJZHdjM193cml0ZWwoZHdjLT5yZWdzLCBEV0MzX0dDVEwsIHJlZyk7CisKKwlyZWcgPSBk d2MzX3JlYWRsKGR3Yy0+cmVncywgRFdDM19HQ1RMKTsKKwlyZWcgJj0gfihEV0MzX0dDVExfQ09S RVNPRlRSRVNFVCk7CisJZHdjM193cml0ZWwoZHdjLT5yZWdzLCBEV0MzX0dDVEwsIHJlZyk7Cit9 CisKIHN0YXRpYyB2b2lkIF9fZHdjM19zZXRfbW9kZShzdHJ1Y3Qgd29ya19zdHJ1Y3QgKndvcmsp CiB7CiAJc3RydWN0IGR3YzMgKmR3YyA9IHdvcmtfdG9fZHdjKHdvcmspOwogCXVuc2lnbmVkIGxv bmcgZmxhZ3M7CiAJaW50IHJldDsKKwlpbnQgcmVnOwogCiAJaWYgKGR3Yy0+ZHJfbW9kZSAhPSBV U0JfRFJfTU9ERV9PVEcpCiAJCXJldHVybjsKQEAgLTE2OCw5ICsxODIsMTggQEAgc3RhdGljIHZv aWQgX19kd2MzX3NldF9tb2RlKHN0cnVjdCB3b3JrX3N0cnVjdCAqd29yaykKIAkJCXBoeV9zZXRf bW9kZShkd2MtPnVzYjJfZ2VuZXJpY19waHksIFBIWV9NT0RFX1VTQl9IT1NUKTsKIAkJCXBoeV9z ZXRfbW9kZShkd2MtPnVzYjNfZ2VuZXJpY19waHksIFBIWV9NT0RFX1VTQl9IT1NUKTsKIAkJCXBo eV9jYWxpYnJhdGUoZHdjLT51c2IyX2dlbmVyaWNfcGh5KTsKKwkJCWlmIChkd2MtPmRpc19zcGxp dF9xdWlyaykgeworCQkJCXJlZyA9IGR3YzNfcmVhZGwoZHdjLT5yZWdzLCBEV0MzX0dVQ1RMMyk7 CisJCQkJcmVnIHw9IERXQzNfR1VDVEwzX1NQTElURElTQUJMRTsKKwkJCQlkd2MzX3dyaXRlbChk d2MtPnJlZ3MsIERXQzNfR1VDVEwzLCByZWcpOworCQkJfQogCQl9CiAJCWJyZWFrOwogCWNhc2Ug RFdDM19HQ1RMX1BSVENBUF9ERVZJQ0U6CisJCS8qIEV4ZWN1dGUgYSBHQ1RMIENvcmUgU29mdCBS ZXNldCB3aGVuIHN3aXRjaCBtb2RlICovCisJCWlmIChkd2MtPmdjdGxfcmVzZXRfcXVpcmspCisJ CQlkd2MzX2djdGxfY29yZV9zb2Z0X3Jlc2V0KGR3Yyk7CisKIAkJZHdjM19ldmVudF9idWZmZXJz X3NldHVwKGR3Yyk7CiAKIAkJaWYgKGR3Yy0+dXNiMl9waHkpCkBAIC0xMjk4LDYgKzEzMjEsMTEg QEAgc3RhdGljIHZvaWQgZHdjM19nZXRfcHJvcGVydGllcyhzdHJ1Y3QgZHdjMyAqZHdjKQogCWR3 Yy0+ZGlzX21ldGFzdGFiaWxpdHlfcXVpcmsgPSBkZXZpY2VfcHJvcGVydHlfcmVhZF9ib29sKGRl diwKIAkJCQkic25wcyxkaXNfbWV0YXN0YWJpbGl0eV9xdWlyayIpOwogCisJZHdjLT5kaXNfc3Bs aXRfcXVpcmsgPSBkZXZpY2VfcHJvcGVydHlfcmVhZF9ib29sKGRldiwKKwkJCQkic25wcyxkaXMt c3BsaXQtcXVpcmsiKTsKKwlkd2MtPmdjdGxfcmVzZXRfcXVpcmsgPSBkZXZpY2VfcHJvcGVydHlf cmVhZF9ib29sKGRldiwKKwkJCQkic25wcyxnY3RsLXJlc2V0LXF1aXJrIik7CisKIAlkd2MtPmxw bV9ueWV0X3RocmVzaG9sZCA9IGxwbV9ueWV0X3RocmVzaG9sZDsKIAlkd2MtPnR4X2RlX2VtcGhh c2lzID0gdHhfZGVfZW1waGFzaXM7CiAKQEAgLTE4MTUsMTAgKzE4NDMsMjUgQEAgc3RhdGljIGlu dCBkd2MzX3Jlc3VtZShzdHJ1Y3QgZGV2aWNlICpkZXYpCiAKIAlyZXR1cm4gMDsKIH0KKworc3Rh dGljIHZvaWQgZHdjM19jb21wbGV0ZShzdHJ1Y3QgZGV2aWNlICpkZXYpCit7CisJc3RydWN0IGR3 YzMJKmR3YyA9IGRldl9nZXRfZHJ2ZGF0YShkZXYpOworCXUzMgkJcmVnOworCisJaWYgKGR3Yy0+ Y3VycmVudF9kcl9yb2xlID09IERXQzNfR0NUTF9QUlRDQVBfSE9TVCAmJgorCQkJZHdjLT5kaXNf c3BsaXRfcXVpcmspIHsKKwkJZGV2X2RiZyhkd2MtPmRldiwgInNldCBEV0MzX0dVQ1RMM19TUExJ VERJU0FCTEVcbiIpOworCQlyZWcgPSBkd2MzX3JlYWRsKGR3Yy0+cmVncywgRFdDM19HVUNUTDMp OworCQlyZWcgfD0gRFdDM19HVUNUTDNfU1BMSVRESVNBQkxFOworCQlkd2MzX3dyaXRlbChkd2Mt PnJlZ3MsIERXQzNfR1VDVEwzLCByZWcpOworCX0KK30KICNlbmRpZiAvKiBDT05GSUdfUE1fU0xF RVAgKi8KIAogc3RhdGljIGNvbnN0IHN0cnVjdCBkZXZfcG1fb3BzIGR3YzNfZGV2X3BtX29wcyA9 IHsKIAlTRVRfU1lTVEVNX1NMRUVQX1BNX09QUyhkd2MzX3N1c3BlbmQsIGR3YzNfcmVzdW1lKQor CS5jb21wbGV0ZSA9IGR3YzNfY29tcGxldGUsCiAJU0VUX1JVTlRJTUVfUE1fT1BTKGR3YzNfcnVu dGltZV9zdXNwZW5kLCBkd2MzX3J1bnRpbWVfcmVzdW1lLAogCQkJZHdjM19ydW50aW1lX2lkbGUp CiB9OwpkaWZmIC0tZ2l0IGEvZHJpdmVycy91c2IvZHdjMy9jb3JlLmggYi9kcml2ZXJzL3VzYi9k d2MzL2NvcmUuaAppbmRleCA1YmZiNjI1MzNlMGYuLmIzY2VhOTVmNzcyMCAxMDA2NDQKLS0tIGEv ZHJpdmVycy91c2IvZHdjMy9jb3JlLmgKKysrIGIvZHJpdmVycy91c2IvZHdjMy9jb3JlLmgKQEAg LTEzNSw2ICsxMzUsNyBAQAogI2RlZmluZSBEV0MzX0dFVk5UQ09VTlQobikJKDB4YzQwYyArICgo bikgKiAweDEwKSkKIAogI2RlZmluZSBEV0MzX0dIV1BBUkFNUzgJCTB4YzYwMAorI2RlZmluZSBE V0MzX0dVQ1RMMwkJMHhjNjBjCiAjZGVmaW5lIERXQzNfR0ZMQURKCQkweGM2MzAKIAogLyogRGV2 aWNlIFJlZ2lzdGVycyAqLwpAQCAtMzU5LDYgKzM2MCw5IEBACiAvKiBHbG9iYWwgVXNlciBDb250 cm9sIFJlZ2lzdGVyIDIgKi8KICNkZWZpbmUgRFdDM19HVUNUTDJfUlNUX0FDVEJJVExBVEVSCQlC SVQoMTQpCiAKKy8qIEdsb2JhbCBVc2VyIENvbnRyb2wgUmVnaXN0ZXIgMyAqLworI2RlZmluZSBE V0MzX0dVQ1RMM19TUExJVERJU0FCTEUJCUJJVCgxNCkKKwogLyogRGV2aWNlIENvbmZpZ3VyYXRp b24gUmVnaXN0ZXIgKi8KICNkZWZpbmUgRFdDM19EQ0ZHX0RFVkFERFIoYWRkcikJKChhZGRyKSA8 PCAzKQogI2RlZmluZSBEV0MzX0RDRkdfREVWQUREUl9NQVNLCURXQzNfRENGR19ERVZBRERSKDB4 N2YpCkBAIC0xMTY4LDYgKzExNzIsOSBAQCBzdHJ1Y3QgZHdjMyB7CiAKIAl1bnNpZ25lZAkJZGlz X21ldGFzdGFiaWxpdHlfcXVpcms6MTsKIAorCXVuc2lnbmVkCQlkaXNfc3BsaXRfcXVpcms6MTsK Kwl1bnNpZ25lZAkJZ2N0bF9yZXNldF9xdWlyazoxOworCiAJdTE2CQkJaW1vZF9pbnRlcnZhbDsK IH07CiAKZGlmZiAtLWdpdCBhL2RyaXZlcnMvdXNiL2R3YzMvZ2FkZ2V0LmMgYi9kcml2ZXJzL3Vz Yi9kd2MzL2dhZGdldC5jCmluZGV4IDY3OWMxMmUxNDUyMi4uY2Q1NGFkM2VhZjAxIDEwMDY0NAot LS0gYS9kcml2ZXJzL3VzYi9kd2MzL2dhZGdldC5jCisrKyBiL2RyaXZlcnMvdXNiL2R3YzMvZ2Fk Z2V0LmMKQEAgLTI2OSw3ICsyNjksNyBAQCBpbnQgZHdjM19zZW5kX2dhZGdldF9lcF9jbWQoc3Ry dWN0IGR3YzNfZXAgKmRlcCwgdW5zaWduZWQgY21kLAogewogCWNvbnN0IHN0cnVjdCB1c2JfZW5k cG9pbnRfZGVzY3JpcHRvciAqZGVzYyA9IGRlcC0+ZW5kcG9pbnQuZGVzYzsKIAlzdHJ1Y3QgZHdj MwkJKmR3YyA9IGRlcC0+ZHdjOwotCXUzMgkJCXRpbWVvdXQgPSAxMDAwOworCXUzMgkJCXRpbWVv dXQgPSA1MDAwOwogCXUzMgkJCXNhdmVkX2NvbmZpZyA9IDA7CiAJdTMyCQkJcmVnOwogCg== From mboxrd@z Thu Jan 1 00:00:00 1970 From: Yu Chen Subject: [PATCH 05/10] usb: dwc3: Add two quirks for Hisilicon Kirin Soc Platform Date: Sat, 27 Oct 2018 17:58:15 +0800 Message-ID: <20181027095820.40056-6-chenyu56@huawei.com> References: <20181027095820.40056-1-chenyu56@huawei.com> Mime-Version: 1.0 Content-Type: text/plain Return-path: In-Reply-To: <20181027095820.40056-1-chenyu56@huawei.com> Sender: linux-kernel-owner@vger.kernel.org To: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: suzhuangluan@hisilicon.com, kongfei@hisilicon.com, Yu Chen , Felipe Balbi , Greg Kroah-Hartman , John Stultz , Binghui Wang List-Id: devicetree@vger.kernel.org There are tow quirks for DesignWare USB3 DRD Core of Hisilicon Kirin Soc. 1)SPLIT_BOUNDARY_DISABLE should be set for Host mode 2)A GCTL soft reset should be executed when switch mode Cc: Felipe Balbi Cc: Greg Kroah-Hartman Cc: John Stultz Cc: Binghui Wang Signed-off-by: Yu Chen --- drivers/usb/dwc3/core.c | 43 +++++++++++++++++++++++++++++++++++++++++++ drivers/usb/dwc3/core.h | 7 +++++++ drivers/usb/dwc3/gadget.c | 2 +- 3 files changed, 51 insertions(+), 1 deletion(-) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index becfbb87f791..68c29e549bfb 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -111,11 +111,25 @@ void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode) dwc->current_dr_role = mode; } +static void dwc3_gctl_core_soft_reset(struct dwc3 *dwc) +{ + int reg; + + reg = dwc3_readl(dwc->regs, DWC3_GCTL); + reg |= (DWC3_GCTL_CORESOFTRESET); + dwc3_writel(dwc->regs, DWC3_GCTL, reg); + + reg = dwc3_readl(dwc->regs, DWC3_GCTL); + reg &= ~(DWC3_GCTL_CORESOFTRESET); + dwc3_writel(dwc->regs, DWC3_GCTL, reg); +} + static void __dwc3_set_mode(struct work_struct *work) { struct dwc3 *dwc = work_to_dwc(work); unsigned long flags; int ret; + int reg; if (dwc->dr_mode != USB_DR_MODE_OTG) return; @@ -168,9 +182,18 @@ static void __dwc3_set_mode(struct work_struct *work) phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); phy_calibrate(dwc->usb2_generic_phy); + if (dwc->dis_split_quirk) { + reg = dwc3_readl(dwc->regs, DWC3_GUCTL3); + reg |= DWC3_GUCTL3_SPLITDISABLE; + dwc3_writel(dwc->regs, DWC3_GUCTL3, reg); + } } break; case DWC3_GCTL_PRTCAP_DEVICE: + /* Execute a GCTL Core Soft Reset when switch mode */ + if (dwc->gctl_reset_quirk) + dwc3_gctl_core_soft_reset(dwc); + dwc3_event_buffers_setup(dwc); if (dwc->usb2_phy) @@ -1298,6 +1321,11 @@ static void dwc3_get_properties(struct dwc3 *dwc) dwc->dis_metastability_quirk = device_property_read_bool(dev, "snps,dis_metastability_quirk"); + dwc->dis_split_quirk = device_property_read_bool(dev, + "snps,dis-split-quirk"); + dwc->gctl_reset_quirk = device_property_read_bool(dev, + "snps,gctl-reset-quirk"); + dwc->lpm_nyet_threshold = lpm_nyet_threshold; dwc->tx_de_emphasis = tx_de_emphasis; @@ -1815,10 +1843,25 @@ static int dwc3_resume(struct device *dev) return 0; } + +static void dwc3_complete(struct device *dev) +{ + struct dwc3 *dwc = dev_get_drvdata(dev); + u32 reg; + + if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST && + dwc->dis_split_quirk) { + dev_dbg(dwc->dev, "set DWC3_GUCTL3_SPLITDISABLE\n"); + reg = dwc3_readl(dwc->regs, DWC3_GUCTL3); + reg |= DWC3_GUCTL3_SPLITDISABLE; + dwc3_writel(dwc->regs, DWC3_GUCTL3, reg); + } +} #endif /* CONFIG_PM_SLEEP */ static const struct dev_pm_ops dwc3_dev_pm_ops = { SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume) + .complete = dwc3_complete, SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume, dwc3_runtime_idle) }; diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 5bfb62533e0f..b3cea95f7720 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -135,6 +135,7 @@ #define DWC3_GEVNTCOUNT(n) (0xc40c + ((n) * 0x10)) #define DWC3_GHWPARAMS8 0xc600 +#define DWC3_GUCTL3 0xc60c #define DWC3_GFLADJ 0xc630 /* Device Registers */ @@ -359,6 +360,9 @@ /* Global User Control Register 2 */ #define DWC3_GUCTL2_RST_ACTBITLATER BIT(14) +/* Global User Control Register 3 */ +#define DWC3_GUCTL3_SPLITDISABLE BIT(14) + /* Device Configuration Register */ #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3) #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f) @@ -1168,6 +1172,9 @@ struct dwc3 { unsigned dis_metastability_quirk:1; + unsigned dis_split_quirk:1; + unsigned gctl_reset_quirk:1; + u16 imod_interval; }; diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c index 679c12e14522..cd54ad3eaf01 100644 --- a/drivers/usb/dwc3/gadget.c +++ b/drivers/usb/dwc3/gadget.c @@ -269,7 +269,7 @@ int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd, { const struct usb_endpoint_descriptor *desc = dep->endpoint.desc; struct dwc3 *dwc = dep->dwc; - u32 timeout = 1000; + u32 timeout = 5000; u32 saved_config = 0; u32 reg; -- 2.15.0-rc2 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 251D7ECDE47 for ; Sat, 27 Oct 2018 10:00:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id ECCC92086B for ; Sat, 27 Oct 2018 10:00:03 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org ECCC92086B Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=huawei.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728513AbeJ0Sk0 (ORCPT ); Sat, 27 Oct 2018 14:40:26 -0400 Received: from szxga07-in.huawei.com ([45.249.212.35]:46131 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1728434AbeJ0SkZ (ORCPT ); Sat, 27 Oct 2018 14:40:25 -0400 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 3AAE9A5806C17; Sat, 27 Oct 2018 17:59:57 +0800 (CST) Received: from vm100-107-113-134.huawei.com (100.107.113.134) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.408.0; Sat, 27 Oct 2018 17:59:50 +0800 From: Yu Chen To: , , CC: , , Yu Chen , Felipe Balbi , Greg Kroah-Hartman , John Stultz , "Binghui Wang" Subject: [PATCH 05/10] usb: dwc3: Add two quirks for Hisilicon Kirin Soc Platform Date: Sat, 27 Oct 2018 17:58:15 +0800 Message-ID: <20181027095820.40056-6-chenyu56@huawei.com> X-Mailer: git-send-email 2.15.0-rc2 In-Reply-To: <20181027095820.40056-1-chenyu56@huawei.com> References: <20181027095820.40056-1-chenyu56@huawei.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [100.107.113.134] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org There are tow quirks for DesignWare USB3 DRD Core of Hisilicon Kirin Soc. 1)SPLIT_BOUNDARY_DISABLE should be set for Host mode 2)A GCTL soft reset should be executed when switch mode Cc: Felipe Balbi Cc: Greg Kroah-Hartman Cc: John Stultz Cc: Binghui Wang Signed-off-by: Yu Chen --- drivers/usb/dwc3/core.c | 43 +++++++++++++++++++++++++++++++++++++++++++ drivers/usb/dwc3/core.h | 7 +++++++ drivers/usb/dwc3/gadget.c | 2 +- 3 files changed, 51 insertions(+), 1 deletion(-) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index becfbb87f791..68c29e549bfb 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -111,11 +111,25 @@ void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode) dwc->current_dr_role = mode; } +static void dwc3_gctl_core_soft_reset(struct dwc3 *dwc) +{ + int reg; + + reg = dwc3_readl(dwc->regs, DWC3_GCTL); + reg |= (DWC3_GCTL_CORESOFTRESET); + dwc3_writel(dwc->regs, DWC3_GCTL, reg); + + reg = dwc3_readl(dwc->regs, DWC3_GCTL); + reg &= ~(DWC3_GCTL_CORESOFTRESET); + dwc3_writel(dwc->regs, DWC3_GCTL, reg); +} + static void __dwc3_set_mode(struct work_struct *work) { struct dwc3 *dwc = work_to_dwc(work); unsigned long flags; int ret; + int reg; if (dwc->dr_mode != USB_DR_MODE_OTG) return; @@ -168,9 +182,18 @@ static void __dwc3_set_mode(struct work_struct *work) phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); phy_calibrate(dwc->usb2_generic_phy); + if (dwc->dis_split_quirk) { + reg = dwc3_readl(dwc->regs, DWC3_GUCTL3); + reg |= DWC3_GUCTL3_SPLITDISABLE; + dwc3_writel(dwc->regs, DWC3_GUCTL3, reg); + } } break; case DWC3_GCTL_PRTCAP_DEVICE: + /* Execute a GCTL Core Soft Reset when switch mode */ + if (dwc->gctl_reset_quirk) + dwc3_gctl_core_soft_reset(dwc); + dwc3_event_buffers_setup(dwc); if (dwc->usb2_phy) @@ -1298,6 +1321,11 @@ static void dwc3_get_properties(struct dwc3 *dwc) dwc->dis_metastability_quirk = device_property_read_bool(dev, "snps,dis_metastability_quirk"); + dwc->dis_split_quirk = device_property_read_bool(dev, + "snps,dis-split-quirk"); + dwc->gctl_reset_quirk = device_property_read_bool(dev, + "snps,gctl-reset-quirk"); + dwc->lpm_nyet_threshold = lpm_nyet_threshold; dwc->tx_de_emphasis = tx_de_emphasis; @@ -1815,10 +1843,25 @@ static int dwc3_resume(struct device *dev) return 0; } + +static void dwc3_complete(struct device *dev) +{ + struct dwc3 *dwc = dev_get_drvdata(dev); + u32 reg; + + if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST && + dwc->dis_split_quirk) { + dev_dbg(dwc->dev, "set DWC3_GUCTL3_SPLITDISABLE\n"); + reg = dwc3_readl(dwc->regs, DWC3_GUCTL3); + reg |= DWC3_GUCTL3_SPLITDISABLE; + dwc3_writel(dwc->regs, DWC3_GUCTL3, reg); + } +} #endif /* CONFIG_PM_SLEEP */ static const struct dev_pm_ops dwc3_dev_pm_ops = { SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume) + .complete = dwc3_complete, SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume, dwc3_runtime_idle) }; diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 5bfb62533e0f..b3cea95f7720 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -135,6 +135,7 @@ #define DWC3_GEVNTCOUNT(n) (0xc40c + ((n) * 0x10)) #define DWC3_GHWPARAMS8 0xc600 +#define DWC3_GUCTL3 0xc60c #define DWC3_GFLADJ 0xc630 /* Device Registers */ @@ -359,6 +360,9 @@ /* Global User Control Register 2 */ #define DWC3_GUCTL2_RST_ACTBITLATER BIT(14) +/* Global User Control Register 3 */ +#define DWC3_GUCTL3_SPLITDISABLE BIT(14) + /* Device Configuration Register */ #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3) #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f) @@ -1168,6 +1172,9 @@ struct dwc3 { unsigned dis_metastability_quirk:1; + unsigned dis_split_quirk:1; + unsigned gctl_reset_quirk:1; + u16 imod_interval; }; diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c index 679c12e14522..cd54ad3eaf01 100644 --- a/drivers/usb/dwc3/gadget.c +++ b/drivers/usb/dwc3/gadget.c @@ -269,7 +269,7 @@ int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd, { const struct usb_endpoint_descriptor *desc = dep->endpoint.desc; struct dwc3 *dwc = dep->dwc; - u32 timeout = 1000; + u32 timeout = 5000; u32 saved_config = 0; u32 reg; -- 2.15.0-rc2