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diff for duplicates of <20181029131614.GA14616@ulmo>

diff --git a/a/1.txt b/N1/1.txt
index 211b5d3..6679bff 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -138,7 +138,7 @@ Thierry
 > > about the direction when it starts up, so how would it make the decision
 > > about how to program the registers?
 > > 
-> > > One entity typically owns one shared interrupt only.  For the
+> > > One entity typically owns one shared interrupt only.? For the
 > > > BPMP/SCE/RCE/SPE HSP blocks the shared interrupt 0 is owned by the auxiliary
 > > > processor itself, the shared interrupts 1..4 are connected to LIC and are
 > > > available to other entities. The convention is to go through the interrupts
@@ -201,4 +201,11 @@ Thierry
 > > only.
 > > 
 > > Thierry
->
+> 
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diff --git a/a/2.bin b/a/2.bin
deleted file mode 100644
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--- a/a/2.bin
+++ /dev/null
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diff --git a/a/2.hdr b/a/2.hdr
deleted file mode 100644
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--- a/a/2.hdr
+++ /dev/null
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diff --git a/a/content_digest b/N1/content_digest
index 7797a48..165c2cb 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -3,23 +3,11 @@
  "ref\0bfc78c91-73f1-4f64-9196-5268a73b5c42@nvidia.com\0"
  "ref\020181029103937.GB26393@ulmo\0"
  "ref\09dfa7669-9401-a55c-8959-8d31cf193ca7@nvidia.com\0"
- "From\0Thierry Reding <thierry.reding@gmail.com>\0"
- "Subject\0Re: [PATCH 4/9] mailbox: tegra-hsp: Add support for shared mailboxes\0"
+ "From\0thierry.reding@gmail.com (Thierry Reding)\0"
+ "Subject\0[PATCH 4/9] mailbox: tegra-hsp: Add support for shared mailboxes\0"
  "Date\0Mon, 29 Oct 2018 14:16:14 +0100\0"
- "To\0Pekka Pessi <ppessi@nvidia.com>\0"
- "Cc\0Jassi Brar <jassisinghbrar@gmail.com>"
-  Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-  Jiri Slaby <jslaby@suse.com>
-  Mikko Perttunen <mperttunen@nvidia.com>
-  Jon Hunter <jonathanh@nvidia.com>
-  Timo Alho <talho@nvidia.com>
-  Mika Liljeberg <mliljeberg@nvidia.com>
-  linux-tegra@vger.kernel.org
-  linux-serial@vger.kernel.org
-  devicetree@vger.kernel.org
-  linux-arm-kernel@lists.infradead.org
- " linux-kernel@vger.kernel.org\0"
- "\01:1\0"
+ "To\0linux-arm-kernel@lists.infradead.org\0"
+ "\00:1\0"
  "b\0"
  "On Mon, Oct 29, 2018 at 02:25:42PM +0200, Pekka Pessi wrote:\n"
  "> Hi Thierry,\n"
@@ -161,7 +149,7 @@
  "> > about the direction when it starts up, so how would it make the decision\n"
  "> > about how to program the registers?\n"
  "> > \n"
- "> > > One entity typically owns one shared interrupt only.\302\240 For the\n"
+ "> > > One entity typically owns one shared interrupt only.? For the\n"
  "> > > BPMP/SCE/RCE/SPE HSP blocks the shared interrupt 0 is owned by the auxiliary\n"
  "> > > processor itself, the shared interrupts 1..4 are connected to LIC and are\n"
  "> > > available to other entities. The convention is to go through the interrupts\n"
@@ -224,25 +212,13 @@
  "> > only.\n"
  "> > \n"
  "> > Thierry\n"
- >
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+ "> \n"
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