From mboxrd@z Thu Jan 1 00:00:00 1970 From: Manasi Navare Subject: Re: [PATCH v2 1/2] drm/i915/icl: Fix the macros for DFLEXDPMLE register bits Date: Wed, 31 Oct 2018 16:37:35 -0700 Message-ID: <20181031233735.GE3481@intel.com> References: <20181023191248.26418-1-manasi.d.navare@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9D4F26E3D2 for ; Wed, 31 Oct 2018 23:34:46 +0000 (UTC) Content-Disposition: inline In-Reply-To: <20181023191248.26418-1-manasi.d.navare@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: intel-gfx@lists.freedesktop.org Cc: Paulo Zanoni List-Id: intel-gfx@lists.freedesktop.org UHVzaGVkIHRvIGRpbnEsdGhhbmtzIGZvciB0aGUgcGF0Y2ggYW5kIHJldmlld3MuCgpNYW5hc2kK Ck9uIFR1ZSwgT2N0IDIzLCAyMDE4IGF0IDEyOjEyOjQ3UE0gLTA3MDAsIE1hbmFzaSBOYXZhcmUg d3JvdGU6Cj4gVGhpcyBwYXRjaCBmaXhlcyB0aGUgbWFjcm9zIHVzZWQgZm9yIGRlZmluaW5nIHRo ZSBERkxFWERQTUxFCj4gcmVnaXN0ZXIgYml0IGZpZWxkcy4gVGhpcyBhY2NvdW50cyBmb3IgY2hh bmdlcyBpbiB0aGUgc3BlYy4KPiAKPiBGaXhlczogYTJiYzY5YTFhOWQ2ICgiZHJtL2k5MTUvaWNs OiBBZGQgcmVnaXN0ZXIgZGVmaW5pdGlvbiBmb3IgREZMRVhEUE1MRSIpCj4gQ2M6IEFuaW1lc2gg TWFubmEgPGFuaW1lc2gubWFubmFAaW50ZWwuY29tPgo+IENjOiBQYXVsbyBaYW5vbmkgPHBhdWxv LnIuemFub25pQGludGVsLmNvbT4KPiBDYzogSm9zZSBSb2JlcnRvIGRlIFNvdXphIDxqb3NlLnNv dXphQGludGVsLmNvbT4KPiBTaWduZWQtb2ZmLWJ5OiBNYW5hc2kgTmF2YXJlIDxtYW5hc2kuZC5u YXZhcmVAaW50ZWwuY29tPgo+IFJldmlld2VkLWJ5OiBKb3PDqSBSb2JlcnRvIGRlIFNvdXphIDxq b3NlLnNvdXphQGludGVsLmNvbT4KPiAtLS0KPiAgZHJpdmVycy9ncHUvZHJtL2k5MTUvaTkxNV9y ZWcuaCB8IDggKysrKysrLS0KPiAgMSBmaWxlIGNoYW5nZWQsIDYgaW5zZXJ0aW9ucygrKSwgMiBk ZWxldGlvbnMoLSkKPiAKPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL2k5MTUvaTkxNV9y ZWcuaCBiL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2k5MTVfcmVnLmgKPiBpbmRleCA4YmQ2MWY5NDY3 MTQuLjlkYTQ4OWIxNzZjOSAxMDA2NDQKPiAtLS0gYS9kcml2ZXJzL2dwdS9kcm0vaTkxNS9pOTE1 X3JlZy5oCj4gKysrIGIvZHJpdmVycy9ncHUvZHJtL2k5MTUvaTkxNV9yZWcuaAo+IEBAIC0yMDU3 LDggKzIwNTcsMTIgQEAgZW51bSBpOTE1X3Bvd2VyX3dlbGxfaWQgewo+ICAKPiAgLyogSUNMIFBI WSBERkxFWCByZWdpc3RlcnMgKi8KPiAgI2RlZmluZSBQT1JUX1RYX0RGTEVYRFBNTEUxCQlfTU1J TygweDE2MzhDMCkKPiAtI2RlZmluZSAgIERGTEVYRFBNTEUxX0RQTUxFVENfTUFTSyhuKQkoMHhm IDw8ICg0ICogKG4pKSkKPiAtI2RlZmluZSAgIERGTEVYRFBNTEUxX0RQTUxFVEMobiwgeCkJKCh4 KSA8PCAoNCAqIChuKSkpCj4gKyNkZWZpbmUgICBERkxFWERQTUxFMV9EUE1MRVRDX01BU0sodGNf cG9ydCkJKDB4ZiA8PCAoNCAqICh0Y19wb3J0KSkpCj4gKyNkZWZpbmUgICBERkxFWERQTUxFMV9E UE1MRVRDX01MMCh0Y19wb3J0KQkoMSA8PCAoNCAqICh0Y19wb3J0KSkpCj4gKyNkZWZpbmUgICBE RkxFWERQTUxFMV9EUE1MRVRDX01MMV8wKHRjX3BvcnQpCSgzIDw8ICg0ICogKHRjX3BvcnQpKSkK PiArI2RlZmluZSAgIERGTEVYRFBNTEUxX0RQTUxFVENfTUwzKHRjX3BvcnQpCSg4IDw8ICg0ICog KHRjX3BvcnQpKSkKPiArI2RlZmluZSAgIERGTEVYRFBNTEUxX0RQTUxFVENfTUwzXzIodGNfcG9y dCkJKDEyIDw8ICg0ICogKHRjX3BvcnQpKSkKPiArI2RlZmluZSAgIERGTEVYRFBNTEUxX0RQTUxF VENfTUwzXzAodGNfcG9ydCkJKDE1IDw8ICg0ICogKHRjX3BvcnQpKSkKPiAgCj4gIC8qIEJYVCBQ SFkgUmVmIHJlZ2lzdGVycyAqLwo+ICAjZGVmaW5lIF9QT1JUX1JFRl9EVzNfQQkJCTB4MTYyMThD Cj4gLS0gCj4gMi4xOC4wCj4gCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fCkludGVsLWdmeCBtYWlsaW5nIGxpc3QKSW50ZWwtZ2Z4QGxpc3RzLmZyZWVkZXNr dG9wLm9yZwpodHRwczovL2xpc3RzLmZyZWVkZXNrdG9wLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2lu dGVsLWdmeAo=