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Date: Thu, 1 Nov 2018 20:32:03 +0100
From: Wolfram Sang <wsa@the-dreams.de>
To: Niklas =?utf-8?Q?S=C3=B6derlund?= <niklas.soderlund@ragnatech.se>
Cc: Wolfram Sang <wsa+renesas@sang-engineering.com>,
        Masahiro Yamada <yamada.masahiro@socionext.com>,
        Ulf Hansson <ulf.hansson@linaro.org>,
        linux-mmc@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
        Niklas =?utf-8?Q?S=C3=B6derlund?=
        <niklas.soderlund+renesas@ragnatech.se>
Subject: Re: [PATCH v2 2/3] mmc: renesas_sdhi: align compatibility properties
 for H3 and M3-W
Message-ID: <20181101193200.GI2433@kunai>
References: <20181031231340.1958-1-niklas.soderlund@ragnatech.se>
 <20181031231340.1958-3-niklas.soderlund@ragnatech.se>
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On Thu, Nov 01, 2018 at 12:13:39AM +0100, Niklas S=C3=B6derlund wrote:
> From: Niklas S=C3=B6derlund <niklas.soderlund+renesas@ragnatech.se>
>=20
> It was though all ES revisions of H3 and M3-W SoCs required the
> TMIO_MMC_HAVE_4TAP_HS400 flag. Recent datasheet updates tells us this is
> not true, only early ES revisions of the SoC do.
>=20
> Since quirk matching based on ES revisions is now used to handle the
> flag it's possible to align all Gen3 compatibility properties. This will
> allow later ES revisions of H3 and M3-W to use the correct 8-tap HS400
> mode.
>=20
> Signed-off-by: Niklas S=C3=B6derlund <niklas.soderlund+renesas@ragnatech.=
se>

Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>


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